DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
2. The Amendments filed February 27th, 2026 are noted in response to the Non-Final Office Action mailed 11/25/2025 are noted.
Applicant’s amendments to the claims are noted.
3. Claims 1-10, 18, and 24 are now canceled; Claims 11-17, 19-23, and 25-32 remain pending in the application.
4. Claims 11-17, 19-23, and 25-32 have been fully considered in examination.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 11-12, 14-15, 21-23, 25-28, and 30-31 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang (U.S. PG Pub No US2020/0176552A1) (of record).
Regarding claim 11, Chang teaches a semiconductor arrangement (2200) fig. 22 [0092] (see annotated fig. 22 of Chang below), comprising:
a first conductive layer (lower 114) fig. 22 [0028, 0094] (formed of electrically conductive material such as doped polysilicon or titanium nitride) [0028];
a first dielectric layer (lower 112) fig. 22 [0090] over the first conductive layer (lower 114) (see annotated fig. 22 of Chang below);
a second conductive layer (upper 114) fig. 22 [0028, 0094] (formed of electrically conductive material such as doped polysilicon or titanium nitride) [0028] over a portion of the first dielectric layer (lower 112) and having a sidewall surface (left sidewall of upper 114) (see annotated fig. 22 of Chang below);
a second dielectric layer (upper 112) fig. 22 [0090] over the second conductive layer (upper 114) and having a sidewall surface (left sidewall of upper 112);
a spacer (portion of 1010b) fig. 22 [0091] (see annotated fig. 22 of Chang below) over (partially above) a portion of the sidewall surface of the second conductive layer (left sidewall of upper 114), over a portion of the sidewall surface of the second dielectric layer (left sidewall of upper 112), and covering an interface (partially covering left portions of interface) between the second conductive layer (upper 114) and the first dielectric layer (lower 112),
wherein:
the first conductive layer (lower 114), the first dielectric layer (lower 112), and the second conductive layer (upper 114) define a capacitor (are capacitor dielectric layers and electrodes [0090]),
the spacer (portion on 1010b) comprises a first (inner, right sidewall) sidewall surface facing (towards) the second conductive layer (upper 114) and the second dielectric layer (upper 112) and a second (outer, left) sidewall surface facing opposite the first (inner, right) sidewall surface; and
a third dielectric layer (1020a) fig. 22 [0094] in direct physical contact with the second (outer, left) sidewall surface and overlying an uppermost surface of the spacer (uppermost surface of 1010b portion) such that a line (LINE; annotated fig. 22 below) perpendicular to a top surface of the first conductive layer (lower 114) intersects the third dielectric layer (1020a) and the spacer (1010b portion) (see annotated fig. 22 of Chang below).
[AltContent: arrow][AltContent: textbox (Interconnect 304c)][AltContent: textbox (LINE)]
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Annotated fig. 22 of Chang for independent claim 11 and dependents
Regarding claim 12, Chang teaches the semiconductor arrangement (2200) fig. 22 [0092] of claim 11. Chang also teaches wherein a bottom surface of the second dielectric layer (upper 112) fig. 22 [0090] is in direct physical contact with a top surface of the second conductive layer (upper 114) fig. 22 [0028, 0094].
Regarding claim 14, Chang teaches the semiconductor arrangement (2200) fig. 22 [0092] of claim 11. Chang also teaches comprising:
an interconnect structure (left 304c) fig. 22 [0094] physically contacting the first conductive layer (lower 114) fig. 22 [0028, 0094], wherein the third dielectric layer (1020a) fig. 22 [0094] is laterally between the second (outer) sidewall surface of the spacer (portion of 1010b) annotated fig. 22 above [0091] and a sidewall surface of the interconnect structure (left 304c) such that the interconnect structure (left 304c) is spaced apart from the spacer (portion of 1010b) by the third dielectric layer (1020a).
Regarding claim 15, Chang teaches the semiconductor arrangement (2200) fig. 22 [0092] of claim 11. Chang also teaches wherein the second conductive layer (upper 114) fig. 22 [0028, 0094] and the second dielectric layer (upper 112) fig. 22 [0090] are (vertically) spaced apart from the third dielectric layer (1020a) fig. 22 [0094] by the spacer (portion of 1010b) annotated fig. 22 above [0091].
Regarding claim 21, Chang teaches a semiconductor arrangement (2200) fig. 22 [0092-0094] (capacitor), comprising (refer to annotated fig. 22 below):
a first conductive layer (lower 114 = “first conductive layer”) annotated fig. 22 below [0028, 0094];
a first dielectric layer (112 atop first conductive layer) annotated fig. 22 below [0027] over the first conductive layer (lower 114);
a first spacer (first spacer portion of 1010a and 1020b) annotated fig. 22 below [0065] having a first (right) sidewall surface in direct physical contact with a sidewall surface of the first conductive layer (lower 114) and a sidewall surface of the first dielectric layer (112 between first and second conductive layers) that is co-planar with the sidewall surface of the first conductive layer (lower 114 = “first conductive layer”);
a second dielectric layer (1010b/1020a) fig. 22 [0093-0094] over the first dielectric layer (112 between first and second conductive layers) and the first spacer (first spacer portion of 1010a), wherein the first (right) sidewall surface of the first spacer is in direct physical contact with a first sidewall surface of the second dielectric layer (inner 1010b surface bordering redefined spacer boundaries in annotated fig. 22 below) that is co-planar with the sidewall surface of the first conductive layer (lower 114);
a portion of the first spacer (first spacer portion of 1010a) annotated fig. 22 below [0065] in direct physical contact with the second dielectric layer (1010b) fig. 22 [0093-0094] has a composition that is different than a composition of the second dielectric layer (1010b) fig. 22 [0093-0094] ([0091 Chang] ‘the first etch stop layer 1010 a may be USG oxide while 1010 b may be silicon nitride’ – which are different compositions);
a second spacer (second spacer portion of 1010a) annotated fig. 22 below [0065] over the first dielectric layer (112 between first and second conductive layers); and
an interconnect structure (304c) annotated fig. 22 below [0094] extending through the first dielectric layer (112 atop first conductive layer 114) and through the second dielectric layer (1010b/1020a) to contact the first conductive layer (lower 114 = “first conductive layer”), wherein:
the first spacer (first spacer portion of 1010a) is spaced apart from the interconnect structure (304c), and
the interconnect structure is (diagonally) between the first spacer (first spacer portion of 1010a) and the second spacer (second spacer portion of 1010a) (refer to annotated fig. 22 below).
.
[AltContent: textbox (First spacer including portions of 1010a and 1010b)][AltContent: rect]
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Annotated fig. 22 of Chang designating relevant features
Regarding claim 22, Chang teaches the semiconductor arrangement (2200) fig. 22 [0092-0094] (capacitor) of claim 21. Chang also teaches wherein the first dielectric layer (112 atop first conductive layer) annotated fig. 22 above [0027] is disposed (laterally) between the interconnect structure (304c) annotated fig. 22 above [0094] and the first spacer (first spacer portion of 1010a) annotated fig. 22 above [0065].
Regarding claim 23, Chang teaches the semiconductor arrangement (2200) fig. 22 [0092-0094] (capacitor) of claim 21. Chang also teaches comprising:
a second spacer (second spacer portion of 1010a) annotated fig. 22 above [0065], wherein the second dielectric layer (1010b/1020a) fig. 22 [0093-0094] is disposed between the interconnect structure (304c) annotated fig. 22 above [0094] and the second spacer (second spacer portion of 1010a) annotated fig. 22 above [0065].
Regarding claim 25, Chang teaches the semiconductor arrangement (2200) fig. 22 [0092-0094] (capacitor) of claim 21. Chang also teaches wherein a second sidewall surface of the first spacer (first spacer portion of 1010a and 1010b) annotated fig. 22 above [0065] is in (direct) contact with a second (left) sidewall surface (right, inner sidewall bordering 1010b) of the second dielectric layer (1020a) fig. 22 [0093-0094].
Regarding claim 26, Chang teaches the semiconductor arrangement (2200) fig. 22 [0092-0094] (capacitor) of claim 21. Chang also teaches comprising:
a third spacer (third spacer portion of 1010a) annotated fig. 22 below [0065], wherein the second dielectric layer (1010b) fig. 22 [0093-0094] is disposed (diagonally) between the first spacer (first spacer portion of 1010a) annotated fig. 22 below [0065] and the third spacer (third spacer portion of 1010a) (see annotated fig. 22 below).
[AltContent: arrow][AltContent: textbox (Third spacer portion of 1010a)][AltContent: rect]
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Annotated fig. 22 of Chang designating third spacer
Regarding claim 27, Chang teaches the semiconductor arrangement (2200) fig. 22 [0092-0094] (capacitor) of claim 26. Chang also teaches comprising:
a third dielectric layer (110) fig. 22 [0027] under the first conductive layer (lower 114) fig. 22 [0092-0094], wherein the third dielectric layer (110) fig. 22 [0027] is in direct physical contact with the first spacer (first spacer portion of 1010a) annotated fig. 22 above [0065] and the third spacer (third spacer portion of 1010a) annotated fig. 22 above [0065].
Regarding claim 28, Chang teaches the semiconductor arrangement (2200) fig. 22 [0092-0094] (capacitor) of claim 27. Chang also teaches the third dielectric layer (110) fig. 22 [0027] is in contact with a bottom surface of the first spacer (first spacer portion of 1010a) annotated fig. 22 above [0065] and a sidewall surface of the third spacer (third spacer portion of 1010a with sidewalls as defined above) annotated fig. 22 above [0065].
Regarding claim 30, Chang teaches the semiconductor arrangement (2200) fig. 22 [0092-0094] (capacitor) of claim 21. Chang also teaches wherein a top of the first spacer (first spacer portion of 1010a) annotated fig. 22 above [0065] is above a top surface of the first dielectric layer (112 atop first conductive layer) annotated fig. 22 above [0027].
Regarding claim 31, Chang teaches the semiconductor arrangement (2200) fig. 22 [0092-0094] (capacitor) of claim 21. Chang also teaches wherein the interconnect structure (304c) annotated fig. 22 above [0094] is in direct physical contact with the first conductive layer (lower 114 = “first conductive layer”) annotated fig. 22 above [0028, 0094].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Chang (U.S. PG Pub No US2020/0176552A1) (of record), as applied in claim 11 above, in view of Kim (U.S. PG Pub No US2019/0131367A1) (of record).
Regarding claim 13, Chang teaches the semiconductor arrangement (2200) fig. 22 [0092] of claim 11. However, Chang does not explicitly disclose wherein the spacer (portion of 1010b) fig. 22 [0091] comprises a metal halide (possibly silicon nitride SiN instead [0091]).
Kim teaches a semiconductor arrangement (comprising a capacitor) [0045-0046, 0109] wherein the spacer (comprising I-INS, O-INS, and BR) fig. 1 [0062] comprises a metal halide (such as titanium fluoride [0065]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have annotated the spacer material in the semiconductor structure comprising a capacitor of Chang to include a titanium-fluoride comprising barrier layer interfacing the metal layer and insulating material [0062-0065] in order to provide etch protection to the spacer layer [0069] as well as protect metal material in the semiconductor structure from corrosion and diffusion [0066-0068], as taught by Kim.
10. Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Chang (U.S. PG Pub No US2020/0176552A1) (of record), as applied in claim 11 above, in view of Chou (U.S. PG Pub No US2018/0076276A1) (of record).
Regarding claim 16, Chang teaches the semiconductor arrangement (2200) fig. 22 [0092] of claim 11. However, Chang does not explicitly disclose comprising:
an interconnect structure contacting the second conductive layer (upper 114) fig. 22 [0028, 0094].
Chou teaches a semiconductor arrangement (1) fig. 1 [0009], comprising:
an interconnect structure (13b) fig. 1 [0009] (physically) contacting the second conductive layer (12b) fig. 1 [0009].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor arrangement of Chang such that an additional interconnect structure is disposed in direct physical contact with the claimed second conductive layer [0009] in order to enhance the integration density of electrical interconnects with the capacitor layers [0002], as taught by Chou.
Claims 17, 19-20, and 32 are rejected under 35 U.S.C. 103 as being unpatentable over Chang (U.S. PG Pub No US2020/0176552A1) (of record) in view of Tsai (U.S. PG Pub No US2021/0036097A1).
Regarding claim 17, Chang teaches a capacitor (2200) fig. 22 [0092-0094], comprising (refer to annotated fig. 22 below):
a first metal layer (lower 114 = “first metal”) annotated fig. 22 below [0028, 0094];
a second metal layer (upper 114 = “second metal”) annotated fig. 22 below [0028, 0094];
a first dielectric layer (112 between first and second metal) annotated fig. 22 below [0027] vertically between the first metal layer (lower 114) and the second metal layer (upper 114) such that a line perpendicular to a top surface of the first metal layer (lower 114) intersects the first metal layer (lower 114), the second metal layer (upper 114), and the first dielectric layer (112 between lower and upper 114) (see line of annotated fig. 22 below);
a spacer (first spacer portion of 1010a) annotated fig. 22 below [0065], wherein the spacer (first spacer portion of 1010a) covers an interface between the first dielectric layer (112) and the second metal layer (upper 114) (see annotated fig. 22 below);
an interconnect structure (304c) annotated fig. 22 below [0094] (directly) contacting the first metal layer (lower 114 = “first metal”); and
wherein:
the interconnect structure (304c) extends through the first dielectric layer (112) such that a first (right) sidewall surface of the interconnect structure (304c) and a second (left) sidewall surface of the interconnect structure (304c) opposite the first sidewall surface both face (interface) the first dielectric layer (112), and
the spacer (first spacer portion of 1010a) is entirely laterally between the interconnect structure (304c) and the second metal layer (upper 114) (refer to annotated fig. 22 below), and
an uppermost surface of the first dielectric layer (112) (diagonally) between the interconnect structure (304c) and the spacer (first spacer portion of 1010a).
[AltContent: textbox (Upper 112 = third dielectric )][AltContent: arrow]
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Annotated fig. 22 of Chang designating relevant features
However, the embodiment of fig. 22 of Chang does not explicitly disclose a second dielectric layer over the first dielectric layer (112), and
the second dielectric layer physically directly contacts an uppermost surface of the first dielectric layer (112) between the interconnect structure (304c) and the spacer (first spacer portion of 1010a).
Tsai teaches a capacitor (100 comprising 213) fig. 7 [0013, 0020] comprising a second dielectric layer (207B) fig. 7 [0018-0019] (refer to annotated fig.7 below for label) over the first dielectric layer (205A) fig. 7 [0018], and
the second dielectric layer (207B) physically directly contacts an uppermost surface of the first dielectric layer (205A) (diagonally) between the interconnect structure (307B) fig. 7 [0027] and the spacer (portions of layer 211) fig. 7 [0022] (as indicated by diagonal line below).
[AltContent: arrow][AltContent: connector][AltContent: textbox (Diagonal line )][AltContent: arrow][AltContent: textbox (207B)]
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Annotated fig. 7 of Tsai
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have annotated the capacitor structure of the embodiment of fig. 22 of Chang such that additional dielectric spacer layers are disposed against sidewalls of the conductive layers and atop the dielectric layers of the capacitors [0018-0019] in order to enhance the amount of dielectric material beside to the capacitor electrodes [0020] so as to increase the integration density of capacitor electrode layers which may be incorporated in a given space [0003, 0012, 0018-0020], as taught by Tsai.
Regarding claim 19, Chang teaches the capacitor (2200) fig. 22 [0092-0094] of claim 17. Chang also teaches wherein:
the first metal layer (lower 114 = “first metal”) annotated fig. 22 above [0028, 0094] is under the first dielectric layer (112 between first and second metal) annotated fig. 22 above [0027], and the interface (see above) comprises a corner interface between the second metal layer (upper 114 = “second metal”) annotated fig. 22 above [0028, 0094] and the first dielectric layer (112 between first and second metal) (refer to annotated fig. 22 above).
Regarding claim 20, Chang teaches the capacitor (2200) fig. 22 [0092-0094] of claim 17. Chang also teaches wherein:
the second metal layer (upper 114 = “second metal”) annotated fig. 22 below [0028, 0094] comprises a sidewall surface, and the interface comprises a sidewall interface defined by the sidewall surface (interface of second metal 114 and spacer includes sidewall of second metal 114) (refer to annotated fig. 22 above).
Regarding claim 32, Chang teaches the capacitor (2200) fig. 22 [0092-0094] of claim 17. Chang also teaches:
a third dielectric layer (upper 112 atop upper 114) annotated fig. 22 above [0028, 0094] directly physically contacting a top surface of the second metal layer (upper 114 = “second metal”) annotated fig. 22 above [0028, 0094]; and
wherein a sidewall surface of the spacer (1010-spacer-portion, as defined in annotated fig. 22 above) directly physically contacts a sidewall surface of the second metal layer (upper 114 = “second metal”) and a sidewall surface of the third dielectric layer (upper 112).
However, the embodiment of fig. 22 of Chang does not explicitly disclose and a fourth dielectric layer directly physically contacting a top surface of the third dielectric layer (upper 112),
wherein a sidewall surface of the spacer (1010 portion in fig. 22) directly physically contacts a sidewall surface of the third dielectric layer (upper 112) and a sidewall of the fourth dielectric layer.
The embodiment of fig. 2C of Chang [0035] teaches a capacitor (200C) fig. 2C [0035] comprising a fourth dielectric layer (upper 112hk) [0035-0037] directly physically contacting a top surface of the third dielectric layer (upper 112bs) [0035-0037],
wherein a sidewall surface of the spacer (1010 portion in fig. 22) directly physically contacts a sidewall surface of the third dielectric layer (upper 112, 112bs portion) and a sidewall of the fourth dielectric layer (upper 112, 112hk portion) (when upper 112 in fig. 22 replaced by 112hk, 112bs dual-layer of fig. 2C of Chang).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have annotated the capacitor structure of the embodiment of fig. 22 of Chang such that the dielectric layers of the capacitor adopt a dual-layer structure with a second, high-k dielectric layer atop the first, base dielectric layer [0035-0037] in order to enhance electrical insulation [0036] and reduce leakage current of the capacitor structure [0036], as taught by Chang.
Claim 29 is rejected under 35 U.S.C. 103 as being unpatentable over Chang (U.S. PG Pub No US2020/0176552 A1) (of record), as applied in claim 21 above, in view of Kim (U.S. PG Pub No US2019/0131367A1) (of record).
Regarding claim 29, Chang teaches the semiconductor arrangement (2200) fig. 22 [0092-0094] (capacitor) of claim 21. Chang also teaches wherein the first conductive layer (lower 114 = “first conductive layer”) annotated fig. 22 below [0028, 0094] comprises titanium nitride (114 may be comprise TiN [0028]).
However, Chang does not explicitly disclose and the first spacer (composed of 1010a material) fig. 22 [0065] comprises titanium fluoride (may be composed of SiN instead [0065]).
Kim teaches a semiconductor arrangement (comprising a capacitor) [0045-0046, 0109] wherein the first conductive layer (M1) fig. 1 [0054] comprises titanium nitride [0064-0065] and the first spacer (comprising I-INS, O-INS, and BR) fig. 1 [0062] comprises titanium fluoride [0065].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have annotated the spacer material in the semiconductor structure comprising a capacitor of Chang to include a titanium-fluoride comprising barrier layer interfacing the metal layer and insulating material [0062-0065] in order to provide etch protection to the spacer layer [0069] as well as protect metal material in the semiconductor structure from corrosion and diffusion [0066-0068], as taught by Kim. The presence of titanium and nitrogen in the conductive layer enables the formation of barrier material on the spacer layer endowing these favorable characteristics [0065-0066].
Response to Arguments
Applicant’s arguments with respect to claim(s) 11 and 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant’s argument(s) with respect to claim 21 have been considered but they are not persuasive because Applicant has not specifically addressed why, if the spacer is defined as a portion of layer (1010a) annotated fig. 22 above [0065 Chang] and the second dielectric layer is defined as (1010b) fig. 22 [0093-0094 Chang], and [0091 Chang] discloses that ‘the first etch stop layer 1010 a may be USG oxide while 1010 b may be silicon nitride’, that these two distinct materials would have ‘different compositions’ from each other.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Newly-added Kuo (U.S. PG Pub No US2020/0098855A1) teaches another example of a deep trench capacitor with additional dielectric layers in direct contact with the claimed first dielectric layer.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SEAN AYERS WINTERS/Examiner, Art Unit 2892 05/19/2026
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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