DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/2/2025 has been entered.
Response to Arguments
Applicant's arguments filed 12/22/2025 have been fully considered but they are moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1 and 2 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The newly amended portion of the claim recites that “the first electrode is disposed on the second interlayer insulating layer, is buried in a first contact hole penetrating through the first interlayer insulating layer and the second interlayer insulating layer” which limits first electrode to element 215. The specification as filed fails to support the limitation “planarization layer disposed between the first electrode and the second electrode” recited at line 15 since the planarization layer 118 is not provided between second electrode 225d/225s and 215 since 215 is not at the level of the planarization layer 118. Further the specification as filed fails to support the limitation “the uppermost portion of the first electrode is disposed in a same layer as the planarization layer” as recited at line 19 since first electrode 215 is disposed below planarization layer 118.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US PGPub 2010/0182223; hereinafter “Choi”) in view of Oh et al. (US PGPub 2016/0064465; hereinafter “Oh”).
Re claim 1: Choi teaches (e.g. fig. 4) a display apparatus comprising: a substrate (10) comprising a display area (display area as shown in fig. 3; hereinafter “DA”); a first thin-film transistor (transistor M2; e.g. paragraph 38) disposed in the display area (DA) on the substrate (10), wherein the first thin-film transistor (M2) comprises a first active layer (30) comprising polycrystalline silicon (polysilicon active layer 30; e.g. paragraph 36-38), a first gate electrode (13) insulated from the first active layer (30), and a first electrode (20d) connected to the first active layer (30); a second thin-film transistor (transistor M1; e.g. paragraph 37) disposed in the display area (DA) on the substrate (10), wherein the second thin-film transistor (M1) comprises a second active layer (18) comprising an oxide semiconductor (oxide semiconductor 18; e.g. paragraph 37), a second gate electrode (14) disposed near the second active layer (18) and insulated from the second active layer (18), and a second electrode (20b,317) connected to the second active layer (18); a first interlayer insulating layer (16) disposed between the first gate electrode (15) and the second active layer (18); a second interlayer insulating layer (22) disposed between the second gate electrode (14) and the first electrode (20d); and a planarization layer (316) disposed between the first electrode (20d) and the second electrode (20b,317), wherein an uppermost portion of the second electrode (20b,317) is spaced farther away than an uppermost portion of the first electrode (20d) relative to the substrate (10) such that the uppermost portion of the second electrode (20b,317) is above an upper surface of the planarization layer (316) and the uppermost portion of the first electrode (20d) is disposed in a same layer as the planarization layer (316), wherein the first electrode (20d) is disposed on the second interlayer insulating layer (22), is buried in a first contact hole (hole for 20d) penetrating through the first interlayer insulating layer (16) and the second interlayer insulating layer (22), and contacts an upper surface of the first active layer (30), and wherein the second electrode (20b,317) is disposed on the planarization layer (316), is buried in a second contact hole (contact hole for 20b,317) penetrating through the second interlayer insulating layer (22) and the planarization layer (316), and contacts an upper surface of the second active layer (18).
Choi is silent as to explicitly teaching second gate electrode (14) disposed above the second active layer; the uppermost portion of the second electrode is spaced farther away than an uppermost portion of the first electrode relative to the substrate such that the upper most portion of the second electrode is above an upper surface of the planarization layer.
Oh teaches (e.g. fig. 3) the second gate electrode (G2) disposed above the second active layer (A2); the uppermost portion of the second electrode (S2, D2) is spaced farther away than an uppermost portion of the first electrode (SA1’, DA1’) relative to the substrate (SUB) such that the upper most portion of the second electrode (S2, D2) is above an upper surface of the planarization layer (ILD2).
It would have been obvious to one of ordinary skill in the art, at the time of effective filing, absent unexpected results, to use the top gate structure for the second thin film transistors and planarization layer as taught by Oh in the device of Lee in order to have the predictable result of using an alternative structure for the second TFT such that there would be better electrical isolation between the two TFTs.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Oh, as applied to claim 1 above, and further in view of Kim (US PGPub 2018/0033821).
Re claim 2: Choi in view of Oh teaches substantially the entire display as claimed in claim 1 except explicitly teaching the display apparatus, wherein the substrate further comprises a bending area, wherein the display apparatus further comprises: a first conductive layer disposed in the bending area at a level which is the same as a level of the first electrode; and a second conductive layer disposed in the bending area at a level which is the same as a level of the second electrode.
Kim teaches (e.g. figs. 4A, 4B) the display apparatus, wherein the substrate (110) further comprises a bending area (BA), wherein the display apparatus further comprises: a first conductive layer (472) disposed in the bending area (BA) at a level which is the same as a level of the first electrode (439); and a second conductive layer (471) disposed in the bending area (BA) at a level which is the same as a level of the second electrode (108 of Lee/122 of Kim).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the bending area wiring connections as taught by Kim in the device of Choi in view of Oh in order to have the predictable result of using a wiring at the bending area at two different levels in order to reduce the area occupied by the wiring (see paragraph 85 of Kim).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSE Y MIYOSHI whose telephone number is (571)270-1629. The examiner can normally be reached M-F, 8:30AM-5:00PM.
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/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898
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