Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed January 1st, 2026, have been fully considered but they are not persuasive.
Applicant argues (pgs. 10-11, “Remarks”) that Jeon and Choi fail to teach the limitations presented in amended Claims 1 and 8.
However, as seen in more detail below, Claim 1 is now rejected by the combination of Jeon, Choi, Sharma, and Leobandung. Similarly, Claim 8 is now rejected by the combination of Choi, Sharma, and Leobandung.
Therefore, applicant’s arguments are not persuasive and are moot in view of the new grounds of rejection.
Applicant argues (pg. 11, “Remarks”) that Choi is designed to preserve the high-quality single-crystal silicon nanosheets (NS1) derived from the substrate. Sharma describes a thin film transistor (TFT) process where the channel is fully replaced. One of ordinary skill in the art would not be motivated to modify Choi with the teachings of Sharma, because doing so would require removing the very silicon nanosheets that Choi relies upon for device performance.
Examiner disagrees with the applicant’s statement that Choi is designed to preserve the high-quality single crystal silicon nanosheets. Applicant has not provided a citation or excerpt from Choi that would support such a statement. Choi merely requires that the nanosheets (NS1) may include silicon or germanium among other materials ([0121]). As a result, it is clear that the benefit of Sharma may be imparted on the device of Choi without destroying the device.
Therefore, applicant’s arguments are not persuasive.
Applicant argues (pg. 12, “Remarks”) that Kanzawa discloses a resistive RAM element and Heo discloses a ferroelectric FET. Kanzawa’s memory cell architecture is fundamentally different from the claimed FeFET architecture wherein the transistor itself is the memory element. In Kanzawa, the “gate structures” are merely access switches for the separate resistive element. The examiner has not demonstrated that it would be obvious to replace the discrete resistor memory element of Kanzawa with the fully integrated gate-all-around FeFET of Heo while retaining the specific wiring connections recited in Claim 15.
Heo teaches that the gate-all-around transistors with ferroelectric channels ([0065], D50, see figs. 10A and 10B, further explained in the rejection below) may be utilized as transistors in a memory device that utilizes a separate memory element ([0071]-[0072], transistor D61 may be the gate-all-around transistor as shown in figs. 10A and 10B, also see fig. 12A). As a result, the transistor of Heo can replace the transistor of Kanzawa and does not require replacing or removing the resistor memory element.
Additionally, in response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., the transistor itself is the memory element) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Applicant states that the claimed invention utilizes the transistor itself is the memory element, however Claim 15 does not explicitly state or preclude other elements or other memory elements from being included in the formation of the memory device.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 5 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites the limitation "the second conductive fill" in lines 2-3. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the limitation will be interpreted as “the second semiconductor material”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate that the corresponding limitations are addressed with a secondary reference/embodiment in an obviousness analysis.
Claims 1-3, 5, 7, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon (2005/0135143 A1; hereinafter Jeon) in view of Choi et al. (KR 20220132791 A1; hereinafter Choi), Sharma et al. (2020/0411669 A1; hereinafter Sharma), and Leobandung (2017/0222045 A1; hereinafter Leobandung).
Regarding Claim 1, Jeon (annotated fig. 8) teaches a method of fabricating a semiconductor device ([0054], memory cell array), the method comprising:
forming a transistor device ([0057], transistor device, see annotated fig. 8) in a first device region (region where transistor device is formed) on the semiconductor device wherein
forming the transistor device comprises: forming a first stacked structure in the first device region, the first stacked structure comprising alternating first and second semiconductor strips;
removing the first semiconductor strips of the first stacked structure to form first voids between the second semiconductor strips in the first device region;
depositing a first dielectric structure layer in the first voids to surround the second semiconductor strips in the first device region; and
depositing a first conductive fill material in the first voids over the first dielectric structure laver to surround the second semiconductor strips in the first device region; and
forming a memory device ([0055], 300) in a second device region (region where 300 is formed) on the semiconductor device, the memory device (300) connected (connected through WLi, see annotated fig. 8) to the transistor device (transistor device); wherein forming the memory device (300) comprises:
forming a second stacked structure in the second device region comprising alternating first and second semiconductor strips;
removing the first semiconductor strips of the second stacked structure to form first voids;
depositing a second dielectric structure laver and the first conductive fill material in the first voids to surround the second semiconductor strips in the second device region;
removing the second semiconductor strips to form second voids in the second device region;
depositing a second semiconductor material in the second voids;
forming a first bit line ([0056], BLi);
forming a first word line ([0056], WLi) connected to the first bit line (BLi);
forming a plate line ([0060], PL) connected to the first word line (WLi) and the first bit line (BLi);
forming a second bit line ([0056], BLi+1) connected to the plate line (PL); and
forming a second word line (([0056], WLi+1) connected to the second bit line (BLi+1) and the plate line (PL).
Jeon doesn’t teach wherein forming the transistor device comprises: forming a first stacked structure in the first device region, the first stacked structure comprising alternating first and second semiconductor strips; removing the first semiconductor strips of the first stacked structure to form first voids between the second semiconductor strips in the first device region; depositing a first dielectric structure layer in the first voids to surround the second semiconductor strips in the first device region; and depositing a first conductive fill material in the first voids over the first dielectric structure laver to surround the second semiconductor strips in the first device region and forming a second stacked structure in the second device region comprising alternating first and second semiconductor strips; removing the first semiconductor strips of the second stacked structure to form first voids; depositing a second dielectric structure laver and the first conductive fill material in the first voids to surround the second semiconductor strips in the second device region.
However, Choi (figs. 1-2 and 20-28) teaches forming the transistor device ([0028], [0033], device formed in region 100b, formed in the right half of figs 20-28) comprises: forming a first stacked structure ([0122], U_AP2, see fig. 22) in the first device region (100b), the first stacked structure (U_AP2) comprising alternating first ([0123]-[0124], SC_L, see fig. 22) and second semiconductor strips ([0123]-[0124], ACT_L, see fig. 22); removing the first semiconductor strips (SC_L) of the first stacked structure (U_AP2) to form first voids ([0129], 170T’, see fig. 26) between the second semiconductor strips (ACT_L) in the first device region (100b); depositing a first dielectric structure layer ([0131], 105 formed in 170T’, see fig. 27) in the first voids (170T’) to surround the second semiconductor strips (ACT_L, referred to as NS1 in fig. 27) in the first device region (100b); and depositing a first conductive fill material ([0132], M1’, see fig. 28) in the first voids (170T’) over the first dielectric structure layer (105 formed in 170T’) to surround the second semiconductor strips (ACT_L, referred to as NS1 in fig. 28) in the first device region (100b) and forming a second stacked structure ([0122], U_AP1, see fig. 22) in the second device region ([0028], [0033], region 100a, formed in the left half of figs. 20-28) comprising alternating first (SC_L) and second semiconductor strips (ACT_L); removing the first semiconductor strips (SC_L) of the second stacked structure (U_AP1) to form first voids ([0129], 130T’, see fig. 26); depositing a second dielectric structure laver ([0131], 105 formed in 130T’, see fig. 27) and the first conductive fill material ([0132], M1’, see fig. 28) in the first voids (130T’)to surround the second semiconductor strips (ACT_L, referred to as NS1 in fig. 28) in the second device region (100a). The gate all around transistor of Choi provides increases device density and an increased number of channels.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Jeon to include the method for forming a transistor of Choi to provide increased device density.
Jeon and Choi don’t teach removing the second semiconductor strips to form second voids in the second device region; depositing a second semiconductor material in the second voids.
However, Sharma (figs. 5a-e) teaches removing the second semiconductor strips ([0052], 531) to form second voids ([0056], 535) in the second device region; depositing a second semiconductor material ([0057], 506, 511, 513) in the second voids (535). Sharma also teaches that the channel formed in this process does not need to withstand the high temperature used in forming the gate electrode ([0014]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Jeon and Choi to include the process for forming the channel of Sharma to avoid channels having to withstand high temperatures.
Sharma doesn’t explicitly teach removing the second semiconductor strips in the second device region.
However, Leobandung teaches that modern transistors may be manufactured using gate-firms process flows ([0003]) like the one described by Sharma. Leobandung continues to teach that this process may be selectively applied to NMOS transistors resulting in a hybrid approach ([0003]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Sharma to include selective gate-first processing of Leobandung to form a hybrid structure.
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Annotated Figure 8
Regarding Claim 2, Jeon (annotated fig. 8) teaches the method of claim 1, wherein the memory device (300) comprises a ferroelectric material ([0057], ferroelectric capacitors).
Regarding Claim 3, Jeon (annotated fig. 8) teaches the method of claim 1, wherein the transistor device (transistor device) is formed side by side with the memory device (300).
Regarding Claim 5, the combination of Choi and Sharma (figs. 5a-e) teaches the method of claim 1, wherein the first conductive fill material (Sharma, [0053], 505) forms a first electrode (Sharma, [0053], 505 is a gate electrode) of the memory device (Choi, left half of figs. 20-28) and the second conductive fill material (Sharma, 506, 511, 513) forms a channel (Sharma, [0057], 506, 511, 513 are formed integrally into a channel structure) of the memory device (Choi, left half of figs. 20-28) in the second device region (Choi, 100a).
Regarding Claim 7, Choi (figs. 20-28) teaches the method of claim 1, wherein depositing the second dielectric structure layer (105 formed in 170T’) to surround the second semiconductor strips (NS1) further comprises: depositing a first ferroelectric material layer ([0092], [0116], 105 is formed into 172’’, see fig. 21) to surround the second semiconductor strips (NS1).
Regarding Claim 21, Sharma (figs. 5a-e) teaches the method of claim 1, wherein the second semiconductor material (506, 511, 513) comprises indium gallium zinc oxide (IGZO) ([0039], channel material may be IGZO).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon, Choi, Sharma, and Leobandung as applied to Claim 1 above, and further in view of Zhang et al. (2021/0202749 A1; hereinafter Zhang).
Regarding Claim 6, Choi doesn’t teach the method of claim 1, wherein removing the first semiconductor strips to form the first voids further comprises: removing portions of the first semiconductor strips to form recessed regions; depositing a dielectric material in the recessed regions; and removing the first semiconductor strips, using the dielectric material in the recessed regions as a mask, to form the first voids between the second semiconductor strips in the second stacked structure.
However, Zhang (figs. 6-8) teaches removing the first semiconductor strips ([0045], 16) to form the first voids ([0057], see fig. 8) further comprises: removing portions of the first semiconductor strips (16) to form recessed regions ([0045], not shown); depositing a dielectric material ([0045], 24) in the recessed regions; and removing the first semiconductor strips (16), using the dielectric material (24) in the recessed regions as a mask ([0057], 24 is not etched during the removal of 16 and protects 26 behind it), to form the first voids between the second semiconductor strips ([0028], 18) in the second stacked structure (stack of 16 and 18). Zhang teaches that the dielectric material is not etched during subsequent etchings and protects the materials behind it ([0057]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Jeon, Choi, and Sharma to include the formation of dielectric layers in recesses of Zhang to protect materials positioned behind it during subsequent etchings.
Claims 8-10, 12, 14, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Sharma and Leobandung.
Regarding Claim 8, Choi (figs. 1-2 and 20-28) teaches a method of fabricating a semiconductor device ([0027], 100), the method comprising:
forming a first memory device ([0028], [0033], device formed in region 100a, formed in the left half of figs. 20-28), wherein forming the first memory device (left half of figs. 20-28) comprises:
forming a first stacked structure ([0122], U_AP1, see fig. 22) in a first device region (100a) of a semiconductor substrate ([0031], 101a, 101b), the first stacked structure (U_AP1) comprising alternating first ([0123]-[0124], SC_L, see fig. 22) and second semiconductor strips ([0123]-[0124], ACT_L, see fig. 22);
removing the first semiconductor strips (SC_L) to form first voids ([0129], 130T’, see fig. 26) between the second semiconductor strips (ACT_L) in the first device region (100a);
depositing a first dielectric structure layer ([0131], 105 formed in 130T’, see fig. 27) in the first voids (130T’) to surround the second semiconductor strips (ACT_L, referred to as NS1 in fig. 27) in the first device region (100a);
depositing a first conductive fill material ([0132], M1’, see fig. 28) in the first voids (130T’) over the first dielectric structure layer (105 formed in 130T’) to surround the second semiconductor strips (ACT_L, referred to as NS1 in fig. 28) in the first device region (100a);
removing the second semiconductor strips between portions of the first dielectric structure laver to form second voids in the first device region;
depositing a second semiconductor material in the second voids between portions of the first dielectric structure laver in the first device region to
form a first plurality of ferroelectric channel regions ([0104], NS1, BP1, [0092], [0116], 105 is formed into 132’’, see fig. 21) on the semiconductor substrate (101a, 101b);
forming a plurality of gate structures ([0132], M1’ between NS1, see fig. 28), each surrounding one of the ferroelectric channel regions (NS1, 132’’);
electrically connecting the gate structures to a gate electrode (M1’ above the stack, see fig. 28);
electrically connecting the first plurality of ferroelectric channel regions (NS1, BP1, 132’’) to a source electrode ([0117], left 135, see fig. 28); and
electrically connecting the first plurality of ferroelectric channel regions (NS1, BP1, 132’’) to a drain electrode ([0117], right 135, see fig. 28).
Choi doesn’t teach removing the second semiconductor strips between portions of the first dielectric structure laver to form second voids in the first device region; depositing a second semiconductor material in the second voids between portions of the first dielectric structure laver in the first device region.
However, Sharma (figs. 5a-e) teaches removing the second semiconductor strips ([0052], 531) between portions of the first dielectric structure laver ([0053], gate dielectric, labeled as 511 in fig. 5a) to form second voids ([0056], 535) in the first device region; depositing a second semiconductor material ([0057], 506) in the second voids (535) between portions of the first dielectric structure laver (511) in the first device region. Sharma also teaches that the channel formed in this process does not need to withstand the high temperature used in forming the gate electrode ([0014]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Choi to include the process for forming the channel of Sharma to avoid channels having to withstand high temperatures.
Sharma doesn’t explicitly teach removing the second semiconductor strips in the first device region.
However, Leobandung teaches that modern transistors may be manufactured using gate-firms process flows ([0003]) like the one described by Sharma. Leobandung continues to teach that this process may be selectively applied to NMOS transistors resulting in a hybrid approach ([0003]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Sharma to include selective gate-first processing of Leobandung to form a hybrid structure.
Regarding Claim 9, Choi (figs. 1-2 and 20-28) teaches the method of claim 8, further comprising: a second device ([0028], device formed in region 100b, formed in the right half of figs 20-28) in a second device region (100b) of the semiconductor substrate (101a, 101b).
Regarding Claim 10, Choi (figs. 1-2 and 20-28) teaches the method of claim 9, wherein the second device (right half of figs. 20-28) is a transistor ([0033]) formed side by side with the first memory device (left half of figs. 20-28).
Regarding Claim 12, Choi (figs. 1-2 and 20-28) teaches the method of claim 9, wherein the first conductive fill material (M1’) forms a plurality of electrodes ([0120], M1’ is formed into 173’’, see fig. 21) of the first memory device (left half of figs. 20-28) in the first device region and a plurality of electrodes ([0116], M1’ is formed into 133’’, see fig. 21) of the second device (right half of figs. 20-28) in the second device region.
Regarding Claim 14, Choi (figs. 20-28) teaches the method of claim 8, wherein depositing the first dielectric structure layer (105 formed in 130T’) to surround the second semiconductor strips (NS1) further comprises: depositing a first ferroelectric material layer ([0092], [0116], 105 is formed into 132’’, see fig. 21) to surround the second semiconductor strips (NS1).
Regarding Claim 22, Sharma (figs. 5a-e) teaches the method of claim 8, wherein the second semiconductor material (506) comprises indium gallium zinc oxide (IGZO) ([0039], channel material may be IGZO).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Choi, Sharma, and, as applied to Claim 8 above, and further in view of Zhang.
Regarding Claim 13, Choi doesn’t teach the method of claim 8, wherein removing the first semiconductor strips to form the first voids further comprises: removing portions of the first semiconductor strips to form recessed regions; depositing a dielectric material in the recessed regions; and removing the first semiconductor strips, using the dielectric material in the recessed regions as a mask, to form the first voids between the second semiconductor strips in the first stacked structure.
However, Zhang (figs. 6-8) teaches removing the first semiconductor strips ([0045], 16) to form the first voids ([0057], see fig. 8) further comprises: removing portions of the first semiconductor strips (16) to form recessed regions ([0045], not shown); depositing a dielectric material ([0045], 24) in the recessed regions; and removing the first semiconductor strips (16), using the dielectric material (24) in the recessed regions as a mask ([0057], 24 is not etched during the removal of 16 and protects 26 behind it), to form the first voids between the second semiconductor strips ([0028], 18) in the first stacked structure (stack of 16 and 18). Zhang teaches that the dielectric material is not etched during subsequent etchings and protects the materials behind it ([0057]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Choi and Sharma to include the formation of dielectric layers in recesses of Zhang to protect materials positioned behind it during subsequent etchings.
Claims 15-19 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Kanzawa et al. (2009/0283736 A1; hereinafter Kanzawa) in view of Heo et al. (2021/0359101 A1; hereinafter Heo) and Jeon (2005/0135143 A1; hereinafter Jeon).
Regarding Claim 15, Kanzawa (annotated fig. 25 and fig. 26) teaches a method of fabricating a semiconductor device ([0111], 300), the method comprising:
forming a first memory device ([0301], T11, M211), wherein forming the first memory device (T11, M211) comprises:
forming a plurality of first ferroelectric channel regions (channel portion of transistor T11) on a semiconductor substrate ([0300]-[0301], layer where source/drain regions 319 are formed, see fig. 26), the first ferroelectric channel regions connecting a first drain region ([0305], first drain region, see annotated fig. 25) to a source region ([0305], source region, see annotated fig. 25);
forming a plurality of first gate structures ([0307], gate of T11), each surrounding one of the first ferroelectric channel regions;
forming a second memory device ([0301], T21, M221), wherein forming the second memory device (T21, M221) comprises:
forming a plurality of second ferroelectric channel regions (channel portion of transistor T21) on the semiconductor substrate, the second ferroelectric channel regions connecting a second drain region (second drain region, see annotated fig. 25) to the source region (source region);
forming a plurality of second gate structures (gate of T21), each surrounding one of the second ferroelectric channel regions;
electrically connecting the first drain region (first drain region) to a first electrode ([0301], BL0);
electrically connecting the first gate structures (gate of T11) to a second electrode ([0307], WL0);
electrically connecting the source region (source region) to a third electrode ([0302], PL0);
electrically connecting the second gate structures to a fourth electrode, and
electrically connecting the second drain region (second drain region) to a fifth electrode ([0301], BL1); wherein
the first and second memory devices each have a gate all around transistor structure having a ferroelectric channel.
Kanzawa doesn’t teach that the first and second channel regions are ferroelectric.
However, Heo (fig. 10B) teaches that the memory device ([0065], D50) comprises ferroelectric channel regions ([0065], 220). Heo also teaches that when ferroelectrics are applied to the gate stack of a transistor, it may lower the transistor’s subthreshold swing value ([0053]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the memory device of Kanzawa to include the use of a ferroelectric material in a transistor of Heo to lower the transistor’s subthreshold swing value.
Additionally, Kanzawa doesn’t teach that the plurality of first and second gate structures each surround one of the first and second ferroelectric channel regions, respectively.
However, Heo (fig. 10A) teaches that the plurality of gate structures ([0065], 300) each surround one of the ferroelectric channel regions ([0065], 111). Heo also teaches that this transistor structure increases the number of gates on channel ([0063]) while still maintaining the function of a transistor for a memory device. One of ordinary skill in the art could have substituted the transistor of Heo for the transistor of Kanzawa and yielded the predictable results of a functioning transistor in a memory device.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the transistor of Heo for the transistor of Kanzawa, since simple substitution of transistors for another is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Lastly, Kanzawa doesn’t teach electrically connecting the second gate structures to a fourth electrode.
However, Jeon (annotated fig. 8) teaches electrically connecting the second gate structures ([0059], gate of N302) to a fourth electrode ([0059], WLi+1). Jeon teaches that this modification forms a two memory cell array having a folded structure ([0054]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the memory device of Kanzawa to include the additional word line of Jeon to facilitate the formation of a two memory cell array having a folded structure.
Furthermore, the combination of Kanzawa and Heo teaches the first (Kanzawa, T11, M211) and second memory devices (Kanzawa, T21, M221) each have a gate all around transistor structure (Heo, fig. 10A) having a ferroelectric channel (Heo, [0065], D50).
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Annotated Figure 25
Regarding Claim 16, Kanzawa (annotated fig. 25 and fig. 26) teaches the method of claim 15, wherein the first electrode is a first bit line (BL0).
Regarding Claim 17, Kanzawa (annotated fig. 25 and fig. 26) teaches the method of claim 15, wherein the second electrode is a first word line (WL0).
Regarding Claim 18, Kanzawa (annotated fig. 25 and fig. 26) teaches the method of claim 15, wherein the third electrode is a plate line (PL0).
Regarding Claim 19, Jeon (annotated fig. 8) teaches the method of claim 15, wherein the fourth electrode is a second word line (WLi+1).
Regarding Claim 23, Kanzawa (annotated fig. 25 and fig. 26) teaches the method of claim 15, wherein the first memory device (T11, M211) and the second memory device (T21, M221) share the third electrode as a common plate line (PL0, see annotated fig. 25).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/A.H./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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