DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after 16 March 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant’s reply filed on 18 April 2025.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 71 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 71 recites “the plurality of conductive contacts are laterally closer to the active area than the via rail.” However, claim 66, which claim 71 depends from, recites “the plurality of conductive contacts laterally straddle the outermost sidewall of the via rail in a plan-view.” It is unclear and indefinite as to how the plurality of conductive contacts can straddle the via rail and be closer to the active area than the via rail. For compact prosecution, it will be interpreted as a second plurality of conductive contacts are laterally closer to the active area than the via rail.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 50, 51, 53, 55, 57, 58 and 65 is/are rejected under 35 U.S.C. 103 as being unpatentable over Seo et al. (U.S. Pub. 2015/0014775) in view of Shimbo et al. (U.S. Pub. 2008/0169487) in view of Warnock (U.S. Pub. 2014/0141607).
Claim 50: Seo et al. discloses an integrated chip, in Figs. 1, 3 and 6 and in paragraphs 50-67 and 84, comprising:
a plurality of gate structures (22) arranged over a substrate (semiconductor substrate) and separated along a first direction (X direction), wherein respective ones of the plurality of gate structures (22) are arranged between adjacent ones of a plurality of source/drain regions (17 and 18) within an active area (12);
a plurality of MEOL structures (24a and 26a) interleaved between neighboring ones of the plurality of gate structures (22), wherein the plurality of MEOL structures (24a and 26a) include a first plurality of MEOL structures (26a) interleaved between a second plurality of MEOL structures (24a), the second plurality of MEOL structures (24a) being closest neighboring MEOL structures on opposing sides of respective ones of the first plurality of MEOL structures (26a), the first plurality of MEOL structures (26a) having a smaller length than the second plurality of MEOL structures (24a);
a third interconnect wire (96) continuously extending directly over the first plurality of MEOL structures (26a); and
a via rail (44) arranged over the second plurality of MEOL structures (24a), wherein the via rail (44) continuously extends in the first direction (X direction) directly over the plurality of gate structures (22), the first plurality of MEOL structure (26a), and the second plurality of MEOL structures (24a),
wherein the second plurality of MEOL structures (24a) extend to directly below the via rail (44) and the third interconnect wire (96) extends directly over a central one (middle 24a) of the second plurality of MEOL structures (24a).
Seo et al. appears not to explicitly disclose wherein the plurality of MEOL structures consist of 5 MEOL structures over the active area, the via rail continuously extending past the 5 MEOL structures and continuously extending to directly over parts of exactly 3 MEOL structures of the 5 MEOL structures.
Seo et al., however, in Fig. 1 and in paragraph 66, discloses there are eight PMOS transistors, however, the number of transistors can vary according to the performance of the inverter.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Seo et al. to have made the device have four transistors in order to have the desired performance of the inverter (paragraph 66 of Set et al.).
If there are only four PMOS transistors, Seo et al. would disclose the plurality of MEOL structures (24a and 26a) consist of 5 MEOL structures (24a and 26a) over the active area (12), the via rail (44) continuously extending past the 5 MEOL structures and continuously extending to directly over parts of exactly 3 MEOL structures (24a) of the 5 MEOL structures.
Seo et al. also appears not to explicitly disclose wherein an entirety of the third interconnect wire is laterally confined between interior sidewalls of outermost ones of the second plurality of MEOL structures that face the first plurality of MEOL structures.
Shimbo et al., however, in Fig. 8 and in paragraphs 27-31, discloses an entirety of the third interconnect wire (15) is laterally confined between interior sidewalls (interior sidewalls of rightmost 24a and leftmost 24a) of outermost ones of the second plurality of MEOL structures that face the first plurality of MEOL structures (13 and 14).
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It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify Seo et al. with the disclosure of Shimbo et al. to have made an entirety of the third interconnect wire is laterally confined between interior sidewalls of outermost ones of the second plurality of MEOL structures that face the first plurality of MEOL structures in order to have used less material to form the third interconnect wire to save on manufacturing costs.
Seo et al. appears not to explicitly disclose a first interconnect wire arranged over the second plurality of MEOL structures;
a second interconnect wire arranged over the first interconnect wire;
the via rail contacting the first interconnect wire and the second interconnect wire along interfaces.
Warnock, however, in Figs. 2 and 3 and in paragraph 18, discloses a first interconnect wire (130);
a second interconnect wire (120) arranged over the first interconnect wire (130); and
the via rail (110) contacting the first interconnect wire (130) and the second interconnect wire (120) along interfaces (interface between 110 and 130 and interface between 110 and 120) in order to have a narrower current carrying structure.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify Seo et al. with the disclosure of Warnock to have made a first interconnect wire;
a second interconnect wire arranged over the first interconnect wire; and
the via rail contacting the first interconnect wire and the second interconnect wire along interfaces in order to have a narrower current carrying structure (paragraph 18 of Warnock).
Seo et al. in view of Warnock would therefore disclose a first interconnect wire arranged over the plurality of conductive contacts;
a second interconnect wire arranged over the first interconnect wire; and
the via rail contacting the first interconnect wire and the second interconnect wire along interfaces.
Claim 51: Seo et al. in view of Shimbo et al. in view of Warnock discloses the integrated chip of claim 50.
Seo et al. in view of Shimbo et al. in view of Warnock, as applied to claim 50, appears not to explicitly disclose wherein the third interconnect wire is laterally centered on the vial rail along the first direction.
Set et al., however, in Fig. 1, further discloses wherein the third interconnect wire (64) is laterally centered on the vial rail (44) along the first direction (X direction) is a suitable configuration for the third interconnect wire to distribute an electrical connection to the drain electrodes.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Seo et al. in view of Shimbo et al. in view of Warnock, as applied to claim 50, with the further disclosure of Seo et al., to have made the third interconnect wire is laterally centered on the vial rail along the first direction because the selection of a known configuration based on its suitability for its intended purpose is obvious (see, for example, M.P.E.P. § 2144.07, and precedents cited therein).
Claim 53: Seo et al. in view of Shimbo et al. in view of Warnock discloses the integrated chip of claim 50, and Seo et al., in Figs. 1 and 6, further discloses wherein the third interconnect wire (96) has ‘U’ shape, the via rail (44) extending past opposing sides (left and right sides) of the ‘U’ shape.
Claim 55: Seo et al. in view of Shimbo et al. in view of Warnock discloses the integrated chip of claim 50, and Seo et al.in Figs. 1 and 6, further discloses wherein the third interconnect wire (96) has an outer edge (lower edge that extends in the X direction) that is parallel to the via rail (44) and that is outside of the active area (12).
Claim 57: Seo et al. in view of Shimbo et al. in view of Warnock discloses the integrated chip of claim 50, and Seo et al., in Figs. 1 and 3 and in paragraphs 66-68, discloses further comprising:
a second plurality of source/drain regions (17 and 18 that are in 14); and
a second via rail (46) extending past the plurality of gate structures (22), wherein the via rail (44) is separated from the second via (46) rail by a cell height (height in Y direction between lower surfaces of 44 and upper surface of 46) that is smaller than a length of the via rail (44), wherein the second via rail (46) is separated from the plurality of source/drain regions (17 and 18) by the second plurality of source/drain regions (17 and 18 that are in 14), wherein the plurality of gate structures (22) continuously extend from directly below the via rail (44) to directly below the second via rail (46).
Seo et al. in view of Shimbo et al. in view of Warnock, as applied to claim 50, appears not to explicitly disclose a fourth interconnect wire separated from the plurality of source/drain regions by the second plurality of source/drain regions, wherein the plurality of gate structures continuously extend from directly below the first interconnect wire to directly below the fourth interconnect wire;
a fifth interconnect wire over the fourth interconnect wire; and
the second via rail arranged between the fourth interconnect wire and the fifth interconnect wire.
Warnock, however, in Figs. 2 and 3 and in paragraph 18, further discloses
a fourth interconnect wire (130);
a fifth interconnect wire (120) over the fourth interconnect wire (130); and
the second via rail (110) arranged between the fourth interconnect wire (130) and the fifth interconnect wire (120) in order to have a narrower current carrying structure.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify Seo et al. in view of Shimbo et al. in view of Warnock, as applied to claim 50, with the further disclosure of Warnock to have made a fourth interconnect wire;
a fifth interconnect wire over the fourth interconnect wire; and
the second via rail arranged between the fourth interconnect wire and the fifth interconnect wire in order to have a narrower current carrying structure (paragraph 18 of Warnock).
Seo et al. in view of Shimbo et al. in view of Warnock would therefore disclose a fourth interconnect wire separated from the plurality of source/drain regions by the second plurality of source/drain regions, wherein the plurality of gate structures continuously extend from directly below the first interconnect wire to directly below the fourth interconnect wire;
a fifth interconnect wire over the fourth interconnect wire; and
the second via rail arranged between the fourth interconnect wire and the fifth interconnect wire.
Claim 58: Seo et al. in view of Shimbo et al. in view of Warnock discloses the integrated chip of claim 50, and Seo et al., in Fig. 1, further discloses wherein the outermost (outermost 24a) ones of the second plurality of MEOL structures (24a) are closest MEOL structures (24a and 26a) to opposing outermost edges (outermost edges of 12) of the active area (12).
Claim 65: Seo et al. in view of Shimbo et al. in view of Warnock discloses the integrated chip of claim 50, and Seo et al., in Fig. 1 and in paragraph 67, discloses further comprising:
a plurality of conductive contacts (34) between the second plurality of MEOL structures (24a) and the via rail (44),
Since Warnock, in Fig. 2, discloses the first interconnect wire (130) is below the via rail (110), Seo et al. in view of Warnock would disclose a plurality of conductive contacts between the second plurality of MEOL structures and the first interconnect wire.
Seo et al. in view of Shimbo et al. in view of Warnock, as applied to claim 50, appears not to explicitly disclose the plurality of conductive contacts are respectively off-centered from the via rail along a second direction that is perpendicular to the first direction.
Shimbo et al., however, in Fig. 8 and in paragraphs 27-30, the plurality of conductive contacts are respectively off-centered from the via rail (11) along a second direction that is perpendicular to the first direction.
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It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify Seo et al. in view of Shimbo et al. in view of Warnock, as applied to claim 50, with the further disclosure of Shimbo et al. to have made a plurality of conductive contacts between the second plurality of MEOL structures and the first interconnect wire in order to reduce manufacturing cost by using less material from reducing the length of the second MEOL structures.
Claim(s) 52 is/are rejected under 35 U.S.C. 103 as being unpatentable over Seo et al in view of Shimbo et al. in view of Warnock as applied to claim 50 above, and further in view of Kim et al. (U.S. Pub. 2016/0117431).
Claim 52: Seo et al. in view of Shimbo et al. in view of Warnock discloses the integrated chip of claim 50.
Seo et al. in view of Shimbo et al. in view of Warnock appears not to explicitly disclose wherein the first plurality of MEOL structures comprise a first MEOL structure having a first length and a second MEOL structure having a second length that is larger than the first length.
Kim et al., however, in Fig. 5 and in paragraphs 131 and 132, discloses the first plurality of MEOL structures (CA1a and CA1c) comprise a first MEOL structure (CA1c) having a first length (length of CA1c in the Y direction) and a second MEOL structure (CA1a) having a second length (length of CA1a in the Y direction) that is larger than the first length is a suitable configuration for routing potential within the device.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify Seo et al. in view of Shimbo et al. in view of Warnock with the disclosure Kim et al. to have made the first plurality of MEOL structures comprise a first MEOL structure having a first length and a second MEOL structure having a second length that is larger than the first length because the selection of a known configuration based on its suitability for its intended purpose is obvious (see, for example, M.P.E.P. § 2144.07, and precedents cited therein).
Claim(s) 66-68, 70 and 71 is/are rejected under 35 U.S.C. 103 as being unpatentable over Seo et al. (U.S. Pub. 2015/0014775) in view of Warnock (U.S. Pub. 2014/0141607) in view of Lin et al. (U.S. Pub. 2016/0329276).
Claim 66: Seo et al. discloses an integrated chip, in Figs. 1, 3 and 6 and in paragraphs 50-67, 70 and 84, comprising:
a plurality of gate structures (22) arranged over a substrate (semiconductor substrate), wherein respective ones of the plurality of gate structures (22) are arranged between adjacent ones of a plurality of source/drain regions (17 and 18) in an active area (12) within the substrate;
a plurality of MEOL structures (24a and 26a) interleaved between neighboring ones of the plurality of gate structures (22);
a plurality of conductive contacts (34) electrically coupled to the plurality of MEOL structures (24a and 26a); and
a via rail (44) over the plurality of conductive contacts (34), wherein the via rail (44) has an outermost sidewall (lower sidewall of 44) that faces an outermost edge (uppermost edge of 17 and 18) of the plurality of source/drain regions (17 and 18), that is laterally separated from the outermost edge (uppermost edge of 17 and 18) of the plurality of source/drain regions (17 and 18) by a non-zero distance, and that continuously extends past the plurality of MEOL structures (24a and 26a).
Seo et al. appears not to explicitly disclose a first interconnect wire arranged over the plurality of conductive contacts;
a second interconnect wire arranged over the first interconnect wire; and
the via rail between the first interconnect wire and the second interconnect wire.
Warnock, however, in Figs. 2 and 3 and in paragraph 18, discloses a first interconnect wire (130);
a second interconnect wire (120) arranged over the first interconnect wire (130); and
the via rail (110) between the first interconnect wire (130) and the second interconnect wire (120) in order to have a narrower current carrying structure.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify Seo et al. with the disclosure of Warnock to have made a first interconnect wire;
a second interconnect wire arranged over the first interconnect wire; and
the via rail between the first interconnect wire and the second interconnect wire in order to have a narrower current carrying structure (paragraph 18 of Warnock).
Seo et al. also appears not to explicitly disclose wherein the plurality of conductive contacts laterally straddle the outermost sidewall of the via rail in a plan-view.
Lin et al., however, in Fig. 7 and in paragraph 40, discloses the plurality of conductive contacts (340) laterally straddle the outermost sidewall (lower sidewall of 354) of the via rail (354) in a plan-view.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify Seo et al. with the disclosure of Lin et al. to have made the plurality of conductive contacts laterally straddle the outermost sidewall of the via rail in a plan-view in order to reduce manufacturing cost by using less material from reducing the length of the second MEOL structures.
Claim 67: Seo et al. in view of Warnock in view of Lin et al. discloses the integrated chip of claim 66.
Seo et al. in view of Warnock in view of Lin et al., as applied to claim 66, appears not to explicitly disclose wherein the via rail extends directly over no more and no less than three of the plurality of MEOL structures.
Seo et al., however, in Fig. 1 and in paragraph 66, further discloses there are eight PMOS transistors, however, the number of transistors can vary according to the performance of the inverter.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Seo et al. to have made the device have four transistors in order to have the desired performance of the inverter (paragraph 66 of Set et al.).
If there are only four PMOS transistors, Seo et al. would disclose the via rail (44) extends directly over only three MEOL structures (24a). Seo et al. would therefore disclose wherein the via rail extends directly over no more and no less than three of the plurality of MEOL structures.
Claim 68: Seo et al. in view of Warnock in view of Lin et al. discloses the integrated chip of claim 66.
Since Seo et al., in Fig. 1, discloses the via rail (44) has an outermost sidewall (lower sidewall of 44) that faces an outermost edge (uppermost edge of 17 and 18) of the plurality of source/drain regions (17 and 18) and that is laterally separated from the outermost edge (uppermost edge of 17 and 18) of the plurality of source/drain regions (17 and 18) by a non-zero distance, and Warnock, in Fig. 1, discloses the first interconnect wire (130) and the second interconnect wire (120) have outer sidewalls facing the same direction as the via rail (110), Seo et al. in view of Warnock would therefore disclose wherein the first interconnect wire comprises a first additional outer sidewall that faces the outermost edge of the plurality of source/drain regions and that is laterally separated from the outermost edge of the plurality of source/drain regions by a second non-zero distance; and
wherein the second interconnect wire comprises a second additional outer sidewall that faces the outermost edge of the plurality of source/drain regions and that is laterally separated from the outermost edge of the plurality of source/drain regions by a third non-zero distance.
Claim 70: Seo et al. in view of Warnock in view of Lin et al. discloses the integrated chip of claim 66 and Seo et al., in Fig. 1, further disclose the plurality of MEOL structures (24a and 26a) comprise a first MEOL structure (26a).
Seo et al. in view of Warnock in view of Lin et al., as applied to claim 66, appears not to explicitly disclose wherein the first MEOL structure that straddles the active area and that has opposing outermost edges that are laterally outside of the active area.
Lin et al., however, in Fig. 4, further discloses the first MEOL structure (upper middle 232) that straddles the active area (200n) and that has opposing outermost edges (upper and lower outermost edges) that are laterally outside of the active area (200n).
Accordingly, it would have been obvious to one of ordinary skill in the art to substitute the further disclosure of Lin et al. that is in the same field of endeavor with Seo et al. in view of Warnock in view of Lin et al., as applied to claim 66, before the effective filing date of the claimed invention in order to substitute the first MEOL structure that straddles the active area and that has opposing outermost edges that are laterally outside of the active area as disclosed by Lin et al. for the configuration of the first MEOL structure and in the active area disclosed by Seo et al. in view of Warnock in view of Lin et al., as applied to claim 66. The substituted components were known in the art, one of ordinary skill could have substituted the elements, and the simple substitution of the first MEOL structure that straddles the active area and that has opposing outermost edges that are laterally outside of the active area disclosed by Lin et al. for the configuration of the first MEOL structure and in the active area disclosed by Seo et al. in view of Warnock in view of Lin et al., as applied to claim 66, would have yielded predictable results, namely providing a suitable electrical connection between the adjacent layers. (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Claim 71: Seo et al. in view of Warnock in view of Lin et al. discloses the integrated chip of claim 66, and Seo et al. further discloses wherein a second plurality of conductive contacts (36) are laterally closer to the active area (12) than the via rail (44).
Claim(s) 69 is/are rejected under 35 U.S.C. 103 as being unpatentable over Seo et al. in view of Warnock in view of Lin et al. as applied to claim 66 above, and further in view of Kim et al. (U.S. Pub. 2016/0117431).
Claim 69: Seo et al. in view of Warnock in view of Lin et al. discloses the integrated chip of claim 66, and Seo et al., in Fig. 1, further discloses wherein the plurality of gate structures (22) respectively have a length extending in a first direction (Y-direction) and a width extending in a second direction (X-direction), the width less than the length.
Seo et al. in view of Warnock in view of Lin et al. appears not to explicitly disclose wherein the plurality of gate structures protrude outward from below the via rail in the first direction.
Kim et al., however, in Fig. 13 and in paragraphs 162 and 163, discloses the plurality of gate structure (130) protrudes outward from below the via rail (120) in the first direction (Y-direction).
Accordingly, it would have been obvious to one of ordinary skill in the art to substitute the disclosure of Kim et al. that is in the same field of endeavor with Seo et al. in view of Warnock in view of Lin et al. before the effective filing date of the claimed invention in order to substitute the plurality of gate structures protrude outward from below the via rail in the first direction as disclosed by Kim et al. for the configuration of the plurality of gate structures and the via rail disclosed by Seo et al. in view of Warnock in view of Lin et al. The substituted components were known in the art, one of ordinary skill could have substituted the elements, and the simple substitution of the plurality of gate structures protrude outward from below the via rail in the first direction disclosed by Kim et al. for the configuration of the plurality of gate structures and the via rail disclosed by Seo et al. in view of Warnock in view of Lin et al. would have yielded predictable results, namely controlling the flow of current in the transistor. (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Claim(s) 72 and 74-77 is/are rejected under 35 U.S.C. 103 as being unpatentable over Seo et al. (U.S. Pub. 2015/0014775) in view of Warnock (U.S. Pub. 2014/0141607) in view of Shimbo et al. (U.S. Pub. 2008/0169487).
Claim 72: Seo et al. discloses an integrated chip, in Figs. 1, 3 and 6 and in paragraphs 50-67 and 84, comprising:
a plurality of gate structures (22) arranged over a substrate (semiconductor substrate) and separated along a first direction (X direction), wherein respective ones of the plurality of gate structures (22) are arranged between adjacent ones of a plurality of source/drain regions (17 and 18) within an active area (12);
a via rail (44) arranged over the plurality of gate structures (22), wherein the via rail (44) continuously extends in the first direction (X direction) directly over the plurality of gate structures (22);
a plurality of MEOL structures (24a and 26a) interleaved between neighboring ones of the plurality of gate structures (22), wherein the plurality of MEOL structures (24a and 26a) include a first plurality of MEOL structures (26a) interleaved between a second plurality of MEOL structures (24a), the second plurality of MEOL structures (24a) extending to directly below the via rail (44); and
a third interconnect wire (96) continuously extending directly over the first plurality of MEOL structures (26a), wherein the third interconnect wire (96) extends directly over a central one (middle 24a) of the second plurality of MEOL structures (24a).
Seo et al. appears not to explicitly disclose
a first interconnect wire arranged over the plurality of gate structures;
a second interconnect wire arranged over the first interconnect wire;
a via rail between the first interconnect wire and the second interconnect wire
Warnock, however, in Figs. 2 and 3 and in paragraph 18, discloses a first interconnect wire (130);
a second interconnect wire (120) arranged over the first interconnect wire (130); and
the via rail (110) between the first interconnect wire (130) and the second interconnect wire (120) in order to have a narrower current carrying structure.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify Seo et al. with the disclosure of Warnock to have made a first interconnect wire;
a second interconnect wire arranged over the first interconnect wire; and
the via rail between the first interconnect wire and the second interconnect wire in order to have a narrower current carrying structure (paragraph 18 of Warnock).
Seo et al. also appears not to explicitly disclose wherein an entirety of the third interconnect wire is laterally confined between interior sidewalls of outermost ones of the second plurality of MEOL structures that face the first plurality of MEOL structures.
Shimbo et al., however, in Fig. 8 and in paragraphs 27-31, discloses an entirety of the third interconnect wire (15) is laterally confined between interior sidewalls (interior sidewalls of rightmost 24a and leftmost 24a) of outermost ones of the second plurality of MEOL structures that face the first plurality of MEOL structures (13 and 14).
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It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify Seo et al. with the disclosure of Shimbo et al. to have made an entirety of the third interconnect wire is laterally confined between interior sidewalls of outermost ones of the second plurality of MEOL structures that face the first plurality of MEOL structures in order to have used less material to form the third interconnect wire to save on manufacturing costs.
Claim 74: Seo et al. in view of Warnock in view of Shimbo et al. discloses the integrated chip of claim 72,
Seo et al. in view of Warnock in view of Shimbo et al., as applied to claim 72, appears not to explicitly disclose wherein the first interconnect wire and the second interconnect wire extend along the first direction past a first pair of opposing sides of the via rail and along a second direction past a second pair of opposing sides of the via rail, the first direction being perpendicular to the second direction.
Warnock, however, in Figs. 3 and 4 and in paragraphs 18-20, further discloses the first interconnect wire (130) and the second interconnect wire (120) extend along the first direction (horizontal direction in Fig. 3) past a first pair of opposing sides (left and right sides of 110) of the via rail (110) and the first interconnect wire (430) and the second interconnect wire (420) extend along a second direction (horizonal direction in Fig. 4) past a second pair of opposing sides (left and right sides of 110) of the via rail (110), the first direction being perpendicular to the second direction.
Accordingly, it would have been obvious to one of ordinary skill in the art to substitute the further disclosure of Warnock that is in the same field of endeavor with Seo et al. in view of Warnock in view of Shimbo et al., as applied to claim 72, before the effective filing date of the claimed invention in order to substitute the first interconnect wire and the second interconnect wire extend along the first direction past a first pair of opposing sides of the via rail and the first interconnect wire and the second interconnect wire extend along a second direction past a second pair of opposing sides of the via rail, the first direction being perpendicular to the second direction as further disclosed by Warnock. for the configuration of the first interconnect wire, the second interconnect wire and the via rail disclosed by Seo et al. in view of Warnock in view of Lin et al., as applied to claim 72. The substituted components were known in the art, one of ordinary skill could have substituted the elements, and the simple substitution of the first interconnect wire and the second interconnect wire extend along the first direction past a first pair of opposing sides of the via rail and the first interconnect wire and the second interconnect wire extend along a second direction past a second pair of opposing sides of the via rail, the first direction being perpendicular to the second direction disclosed by Warnock for the configuration of the first interconnect wire, the second interconnect wire and the via rail disclosed by Seo et al. in view of Warnock in view of Shimbo et al., as applied to claim 72, would have yielded predictable results, namely providing a suitable electrical connection between the adjacent layers. (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Claim 75: Seo et al. in view of Warnock in view of Shimbo et al. discloses the integrated chip of claim 72, and Seo et al., in Fig. 1, further discloses wherein the via rail (44) extends past opposing edges (left and right edges of 12) of the active area (12).
Seo et al. in view of Warnock in view of Shimbo et al., as applied to claim 72, appears not to explicitly disclose wherein the via rail continuously extends to directly over no more and no less than 3 MEOL structures consisting of the second plurality of MEOL structures.
Seo et al., however, in paragraph 66, further discloses there are eight PMOS transistors in Fig. 1, however, the number of transistors can vary according to the performance of the inverter.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Seo et al. to have made the device have four transistors in order to have the desired performance of the inverter (paragraph 66 of Set et al.).
If there are only four PMOS transistors, Seo et al. would disclose the via rail (44) extends directly over only three MEOL structures (24a). Seo et al. would therefore disclose wherein the via rail continuously extends directly over no more and no less than 3 MEOL structures consisting of the second plurality of MEOL structures.
Claim 76: Seo et al. in view of Warnock in view of Shimbo et al. discloses the integrated chip of claim 72, and Seo et al., in Figs. 1 and 6, further discloses wherein the third interconnect wire (96) has ‘U’ shape that wraps around an opening (the opening on the left side of 96), the opening being within a side of the third interconnect wire (96) that faces away from the via rail (44) and the active area (12).
Claim 77: Seo et al. in view of Warnock in view of Shimbo et al. discloses the integrated chip of claim 72.
Seo et al. in view of Warnock in view of Shimbo et al., as applied to claim 72, appears not to explicitly disclose wherein the third interconnect wire is separated from the outermost ones of the second plurality of MEOL structures by equal distances along the first direction.
Shimbo et al., however, further discloses wherein the third interconnect wire (412) is separated from the outermost ones (outermost 422) of the second plurality of MEOL structures (422) by equal distances along the first direction (X direction).
Accordingly, it would have been obvious to one of ordinary skill in the art to substitute the further disclosure of Shimbo et al. that is in the same field of endeavor with Seo et al. in view of Warnock in view of Shimbo et al., as applied to claim 72, before the effective filing date of the claimed invention in order to substitute the third interconnect wire is separated from the outermost ones of the second plurality of MEOL structures by equal distances along the first direction as disclosed by Shimbo et al. for the configuration of the third interconnect wire and the second plurality of MEOL structures disclosed by Seo et al. in view of Warnock in view of Lin et al., as applied to claim 72. The substituted components were known in the art, one of ordinary skill could have substituted the elements, and the simple substitution of the third interconnect wire is separated from the outermost ones of the second plurality of MEOL structures by equal distances along the first direction disclosed by Shimo et al. for the configuration of the third interconnect wire and the second plurality of MEOL structures disclosed by Seo et al. in view of Warnock in view of Shimbo et al., as applied to claim 72, would have yielded predictable results, namely providing a suitable electrical connection between the adjacent layers. (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Claim(s) 73 is/are rejected under 35 U.S.C. 103 as being unpatentable over Seo et al. in view of Warnock in view of Simbo et al. as applied to claim 72 above, and further in view of Kim et al. (U.S. Pub. 2016/0117431).
Claim 73: Seo et al. in view of Warnock in view of Shimbo et al. discloses the integrated chip of claim 72.
Seo et al. in view of Warnock in view of Shimbo et al. appears not to explicitly disclose wherein the plurality of gate structures comprise ends that are completely confined directly below the via rail.
Kim et al., however, in Fig. 13 and in paragraphs 162 and 163, discloses the plurality of gate structure (130) comprise ends (upper ends of 130) that are completely confined directly below the via rail (120).
Accordingly, it would have been obvious to one of ordinary skill in the art to substitute the further disclosure of Kim et al. that is in the same field of endeavor with Seo et al. in view of Warnock in view of Lin et al. before the effective filing date of the claimed invention in order to substitute the plurality of gate structures comprise ends that are completely confined directly below the via rail as disclosed by Kim et al. for the configuration of the plurality of gate structures and the via rail disclosed by Seo et al. in view of Warnock in view of Lin et al. The substituted components were known in the art, one of ordinary skill could have substituted the elements, and the simple substitution of the plurality of gate structures comprise ends that are completely confined directly below the via rail disclosed by Kim et al. for the configuration of the plurality of gate structures and the via rail disclosed by Seo et al. in view of Warnock in view of Lin et al. would have yielded predictable results, namely controlling the flow of current in the transistor. (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Response to Arguments
Applicant's arguments filed 09 September 2025 have been fully considered but they are not persuasive.
Applicant contends the cited prior art fails to teach over a third interconnect that extends to directly over a central one of a second plurality of MEOL structures that extends directly below a via rail, as recited in claim 50.
Examiner notes Seo et al., in Figs. 1 and 6, discloses the third interconnect wire (96) extends directly over a central one (middle 24a) of the second plurality of MEOL structures (24a) that extends directly below a via rail (44).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JAY C KIM/Primary Examiner, Art Unit 2815
/J.L/ Examiner, Art Unit 2815
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