Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status of the Claims
Applicant’s remarks/amendments of claims 1-12, 14-15 and 18-23, in the reply filed on January 30th, 2026, are acknowledged. Claims 1, 6, 14 and 19 have been amend. Claims 13, 16 and 17 have been cancelled. Claims 1-12, 14-15 and 18-23 are pending.
Action on merits of claims 1-12, 14-15 and 18-23 as follows.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1, 6-9 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Ando (US 2018/0337098, hereinafter as Ando ‘098) in view of Yeo (US 2016/0380056, hereinafter as Yeo ‘056), in view of Kuang (US 2016/0013316, hereinafter as Kuan ‘316) and further in view of Loubet (US 2014/0353760, hereinafter as Loub ‘760).
Regarding Claim 1, Ando ‘098 teaches a device comprising:
a first semiconductor region extending from a substrate, the first semiconductor region comprising silicon (Fig. 8, (210; [0028]);
a second semiconductor region on the first semiconductor region, the second semiconductor region comprising silicon germanium (502/504; [0040]), a surface (502) of the second semiconductor region having a first germanium concentration, a subsurface of the second semiconductor region (504) having a second germanium concentration, the first germanium concentration being greater than the second germanium concentration (see para. [0040]); and an isolation region (300; [0036]) around the first semiconductor region (210).
Thus, Ando ‘098 is shown to teach all the features of the claim with the exception of explicitly the limitations: “a protective cap on the second semiconductor region, the protective cap comprising silicon; a gate stack comprising a gate dielectric and a gate electrode, the gate dielectric extending through the protective cap to contact the surface of the second semiconductor region; and a source/drain region in the second semiconductor region, the source/drain region being adjacent the metal gate stack”.
Yeo ‘056 teaches a protective cap (Fig. 3A, (28); [0026]) on the second semiconductor region (22; [0024]), the protective cap comprising silicon (see para. [0026]); a gate stack comprising a gate dielectric (60; [0043]) and a gate electrode (74; [0054]); and a source/drain region (Fig. 17C, (42; [0029]) in the second semiconductor region, the source/drain region being adjacent the metal gate stack (see Fig. 8).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Ando ‘098 by having a protective cap on the second semiconductor region, the protective cap comprising silicon; a gate stack comprising a gate dielectric and a gate electrode; and a source/drain region in the second semiconductor region, the source/drain region being adjacent the metal gate stack for the purpose of protecting the SiGe fin from the damage in subsequent processing (see para. [0024]) as suggested by Yeo ‘056.
Thus, Ando ‘098 and Yeo ‘056 are shown to teach all the features of the claim with the exception of explicitly the limitations: “the gate dielectric extending through the protective cap to contact the surface of the second semiconductor region”.
Kuan ‘316 teaches the gate dielectric (not shown; [0026]) extending through the protective cap (silicon cap, Fig. 9, (230); [0036]) to contact the surface of the second semiconductor region (200; [0018]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Ando ‘098 and Yeo ‘056 by having the gate dielectric extending through the protective cap to contact the surface of the second semiconductor region in order to provide excellent contact characteristics for a contact to be formed to a source and drain regions (see para. [0023]) as suggested by Kuan ‘316.
Thus, Ando ‘098 Yeo ‘056 and Kuan ‘316 are shown to teach all the features of the claim with the exception of explicitly the limitations: “the first semiconductor region having a first width measured between sidewalls of the first semiconductor region; the second semiconductor region having a second width measured between sidewalls of the second semiconductor region, wherein the sidewalls of the second semiconductor region extend continuously from a top of the second semiconductor region to a bottom of the second semiconductor region, wherein the first width of the first semiconductor region is the same as the second width of the second semiconductor region”.
Loub ‘760 teaches the first semiconductor region (Fig. 2K, (A; Annotated)) having a first width measured between sidewalls of the first semiconductor region; the second semiconductor region (Fig. 2K, (224); [0023]) having a second width measured between sidewalls of the second semiconductor region, wherein the sidewalls of the second semiconductor region extend continuously from a top of the second semiconductor region to a bottom of the second semiconductor region, wherein the first width of the first semiconductor region is the same as the second width of the second semiconductor region (see Fig. 2K; [0031]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Ando ‘098, Yeo ‘056 and Kuan ‘316 by having the first semiconductor region having a first width measured between sidewalls of the first semiconductor region; the second semiconductor region having a second width measured between sidewalls of the second semiconductor region, wherein the sidewalls of the second semiconductor region extend continuously from a top of the second semiconductor region to a bottom of the second semiconductor region, wherein the first width of the first semiconductor region is the same as the second width of the second semiconductor region for making co-integrated SiGe and Si finFETs on a bulk substrate (see para. [0007]) as suggested by Loub ‘760.
Thus, Ando ‘098, Yeo ‘056, Kuan ‘316 and Loub ‘760 are shown to teach all the features of the claim with the exception of explicitly the limitations: “the surface of the second semiconductor region and the subsurface of the second semiconductor region are each disposed above a top surface of the isolation region”.
However, it has been held to be within the general skill of a worker in the art to select the first germanium concentration being greater than the second germanium concentration; and the surface of the second semiconductor region and the subsurface of the second semiconductor region are each disposed above a top surface of the isolation region on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. (see Fig. 3C, para. [0038] of Brunco (US 2014/0170839); “a thin region (122C) of the silicon-germanium fins (22) that has an increased or higher concentration of germanium relative to the concentration of germanium in the other portions of the silicon/germanium fins (22); and the surface of the second semiconductor region (122c) and the subsurface of the second semiconductor region (22) are each disposed above a top surface of the isolation region (18)”) as evidence. A person of ordinary skills in the art is motivated to select the first germanium concentration being greater than the second germanium concentration and the surface of the second semiconductor region and the subsurface of the second semiconductor region are each disposed above a top surface of the isolation region in order to improve the performance (e.g. increasing the drive currents…) of the MOSFET transistor device.
Regarding Claim 6, Ando ‘098 teaches a device comprising:
a fin extending from a substrate, the fin comprising a silicon portion (Fig. 8, (210; [0028]) and a silicon germanium portion (502/504; [0040]) on the silicon portion, the silicon germanium portion having a center region and an edge region (502; [0046]); an isolation region (300) around the silicon portion of the fin (210), the center region of the silicon germanium portion of the fin protruding above the isolation region (see para. [0040]); the edge region of the silicon germanium portion of the fin protruding above the isolation region (see para. [0040]);
a gate stack (800; [0045]) on the isolation region (300) and the edge region (500); a gate stack comprising a gate dielectric (804; [0045]) and a gate electrode (800; [0045]).
Thus, Ando ‘098 is shown to teach all the features of the claim with the exception of explicitly the limitations: “a semiconductor cap on the fin, the gate dielectric extending through the semiconductor cap, the gate electrode extending through the semiconductor cap”.
Yeo ‘056 teaches a semiconductor cap (Fig. 3A, (28); [0026]) on the fin (22; [0016]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Ando ‘098 by having a semiconductor cap on the fin for the purpose of improving the drive currents and the speed of the n-channel FinFETs (see para. [0020]) as suggested by Yeo ‘056.
Thus, Ando ‘098 and Yeo ‘056 are shown to teach all the features of the claim with the exception of explicitly the limitations: “the gate dielectric extending through the semiconductor cap, the gate electrode extending through the semiconductor cap”.
Kuan ‘316 teaches the gate dielectric (not shown; see para. [0026]) extending through the semiconductor cap (silicon cap, Fig. 9, (230); [0036]), the gate electrode (not shown; [0026]) extending through the semiconductor cap (230).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Ando ‘098 and Yeo ‘056 by having the gate dielectric extending through the semiconductor cap, the gate electrode extending through the semiconductor cap in order to provide excellent contact characteristics for a contact to be formed to a source and drain regions (see para. [0023]) as suggested by Kuan ‘316.
Thus, Ando ‘098 Yeo ‘056 and Kuan ‘316 are shown to teach all the features of the claim with the exception of explicitly the limitations: “a top of the silicon portion having the same width as a top of the silicon germanium portion”.
Loub ‘760 teaches a top of the silicon portion (Fig. 2K, (A; Annotated)) having the same width (see para. [0031]) as a top of the silicon germanium portion (Fig. 2K, (224); [0023]).
the first semiconductor region (Fig. 2K, (A; Annotated)) having a first width measured between sidewalls of the first semiconductor region; the second semiconductor region (Fig. 2K, (224); [0023]) having a second width measured between sidewalls of the second semiconductor region, wherein the sidewalls of the second semiconductor region extend continuously from a top of the second semiconductor region to a bottom of the second semiconductor region, wherein the first width of the first semiconductor region is the same as the second width of the second semiconductor region (see Fig. 2K; [0031]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Ando ‘098, Yeo ‘056 and Kuan ‘316 by having a top of the silicon portion having the same width as a top of the silicon germanium portion for making co-integrated SiGe and Si finFETs on a bulk substrate (see para. [0007]) as suggested by Loub ‘760.
Thus, Ando ‘098, Yeo ‘056, Kuan ‘316 and Loub ‘760 are shown to teach all the features of the claim with the exception of explicitly the limitations: “the edge region having a greater germanium concentration than the center region”.
However, it has been held to be within the general skill of a worker in the art to select the channel region having a greater germanium concentration than the center region on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. (see Fig. 3C, para. [0038] of Brunco (US 2014/0170839); “a thin region (122C) of the silicon-germanium fins (22) that has an increased or higher concentration of germanium relative to the concentration of germanium in the other portions of the silicon/germanium fins (22)”) as evidence. A person of ordinary skills in the art is motivated to select the channel region having a greater germanium concentration than the center region in order to improve the performance (e.g. increasing the drive currents…) of the MOSFET transistor device.
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Fig. 2K (Loub ‘760_Annotated)
Regarding Claim 7, Yeo ‘056 teaches a top surface of the isolation region (24; [0021]) is level with a top surface of the silicon portion of the fin (see Fig. 8).
Regarding Claim 8, Ando ‘098 teaches a top surface of the isolation region (300) is disposed above a top surface of the silicon portion (210) of the fin (see Fig. 8).
Regarding Claim 9, Ando ‘098 teaches a top surface of the isolation region (300) is disposed above a top surface of the silicon portion (210) of the fin (see Fig. 8).
Ando ‘098, Yeo ‘056, Kuan ‘316 and Loub ‘760 are shown to teach all the features of the claim with the exception of explicitly the limitations: “a top surface of the isolation region is disposed below a top surface of the silicon portion of the fin”.
However, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the top surface of the isolation region that can be arranged in any order, thus a top surface of the isolation region is disposed below a top surface of the silicon portion of the fin involves only routine skill in the art. (see Fig. 5C of Brunco (US 2014/0170839) as a evidence. In re Einstein, 8 USPQ 167. A person of ordinary skills in the art is motivated to perform the arrangement when this improving the performance of the semiconductor transistor device.
Regarding Claim 23, Kuan ‘316 teaches a gate spacer (203; [0027]) on the semiconductor cap (230),
Yeo ‘056 teaches the semiconductor cap (70) disposed between the gate spacer (45) and the fin (22) (see Fig. 9).
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the semiconductor cap that can be arranged in any order, the semiconductor cap disposed between the gate spacer and the fin involves only routine skill in the art. In re Einstein, 8 USPQ 167. A person of ordinary skills in the art is motivated to have the semiconductor cap disposed between the gate spacer and the fin when this improves the performance of MOS devices.
Claims 2-5 and 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Ando ‘098, Yeo ‘056, Kuan ‘316 and Loub ‘760 as applied to claim 1 above, and further in view of Noda (US 2007/0063275, hereinafter as Noda ‘275).
Regarding Claim 2, Ando ‘098, Yeo ‘056, Kuan ‘316 and Loub ‘760 are shown to teach all the features of the claim with the exception of explicitly the limitations: “a lightly doped source/drain (LDD) region in the second semiconductor region, upper portions of the LDD region having a higher germanium concentration than lower portions of the LDD region”.
Noda ‘275 teaches a lightly doped source/drain (LDD) region (Fig. 1, (106); [0058]) and [0060]) in the second semiconductor region, upper portions of the LDD region having a higher germanium concentration than lower portions of the LDD region (see para. [0058]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Ando ‘098, Yeo ‘056, Kuan ‘316 and Loub ‘760 by having a lightly doped source/drain (LDD) region in the second semiconductor region, upper portions of the LDD region having a higher germanium concentration than lower portions of the LDD region in order to void the appearance of short channel effect and suppress an increase in leakage current flow resulting from a low threshold voltage and a highly doped channel of the device (see para. [0016]) as suggested by Noda ‘275.
Regarding Claims 3 and 11, Noda ‘275 teaches a lightly doped source/drain (LDD) region (Fig. 14B, (206); [0010]) in the second semiconductor region, upper portions of the LDD region and lower portions of the LDD region having a uniform germanium concentration.
Regarding Claim 4, Yeo ‘056 teaches gate spacers (45; [0033]) extending along the protective cap, the gate stack (74; [0051]) being disposed between the gate spacers.
Regarding Claim 5, Yeo ‘056 teaches a gate spacer (45) between the metal gate stack (74) and the source/drain region (42), the gate spacer disposed on the protective cap (59/70).
Regarding Claim 10, Noda ‘275 teaches a lightly doped source/drain (LDD) region (Fig. 1, (106); [0058]) in the silicon germanium portion of the fin, the LDD region having a lower region and an upper region, the upper region having a greater germanium concentration than the lower region (see para. [0058]).
Regarding Claim 12, Yeo ‘056 teaches a source/drain region (42; [0032]) adjacent the edge region (22), the source/drain region (42) extending through the semiconductor cap (70) (see Fig. 17C); and a gate spacer (45) on the semiconductor cap, the gate spacer (45) disposed between the gate stack and the source/drain region (42) (see Fig. 8).
Claims 14-15, 18-21 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Ando ‘098 in view of Chang (US 2011/0193178, hereinafter as Chang ‘178), in view of Yeo ‘056; in view Kwok (US 2016/0254364, hereinafter as Kwok ‘364) and further in view Loub ‘760.
Regarding Claim 14, Ando ‘098 teaches a device comprising:
an isolation region (300; [0036]) over a substrate (102; [0036]);
a fin extending from a substrate, the fin comprising a silicon portion (Fig. 8, (210; [0028]) and a silicon germanium portion (502/504; [0040]) on the silicon portion, the silicon germanium portion having a first lower region (504) and a first upper region (502), the first upper region having a greater germanium concentration than the first lower region;
Thus, Ando ‘098 is shown to teach all the features of the claim with the exception of explicitly the limitations: “a lightly doped source/drain (LDD) region in the silicon germanium portion of the fin, the LDD region having a second lower region and a second upper region, the second upper region having a greater germanium concentration than the second lower region”.
Chang ‘178 teaches a lightly doped source/drain (LDD) region in the silicon germanium portion of the fin, the LDD region having a second lower region (62; [0062]) and a second upper region (54; [0021]), the second upper region having a greater germanium concentration than the second lower region (see para. [0021]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Ando ‘098 by having a lightly doped source/drain (LDD) region in the silicon germanium portion of the fin, the LDD region having a second lower region and a second upper region, the second upper region having a greater germanium concentration than the second lower region; and a gate stack on the silicon germanium portion of the fin for the purpose of increasing the drive currents of the FinFETs without incurring the penalty of increased leakage currents (see para. [0030]) as suggested by Chang ‘178.
Thus, Ando ‘098 and Chang ‘178 are shown to teach all the features of the claim with the exception of explicitly the limitations: “the protective cap physically contacting the fin”.
Yeo ‘056 teaches the protective cap (70) physically contacting the fin (22) (see Fig. 17A).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Ando ‘098 and Chang ‘178 by having the protective cap physically contacting the fin for the purpose of improving the drive currents and the speed of the n-channel FinFETs (see para. [0020]) as suggested by Yeo ‘056.
Thus, Ando ‘098, Chang ‘178 and Yeo ‘056 are shown to teach all the features of the claim with the exception of explicitly the limitations: “a protective cap on the LDD region; and a gate spacer on the protective cap, the protective cap disposed between the gate spacer and the LDD region”.
Kwok ‘364 teaches a protective cap (Fig. 8, (44); [0027]) on the LDD region (30; [0013]); and a gate spacer (34; [0014]) on the protective cap (44).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Ando ‘098, Chang ‘178 and Yeo ‘056 by having a protective cap on the LDD region; and a gate spacer on the protective cap in order to enhance the performance of MOS devices (see para. [0008]) as suggested by Kwok ‘364.
Thus, Ando ‘098, Chang ‘178, Yeo ‘056 and Kwok ‘364 are shown to teach all the features of the claim with the exception of explicitly the limitations: “the first semiconductor region having a first width measured between sidewalls of the first semiconductor region; the second semiconductor region having a second width measured between sidewalls of the second semiconductor region, wherein the sidewalls of the second semiconductor region extend continuously from a top of the second semiconductor region to a bottom of the second semiconductor region, wherein the first width of the first semiconductor region is the same as the second width of the second semiconductor region”.
Loub ‘760 teaches the first semiconductor region (Fig. 2K, (A; Annotated)) having a first width measured between sidewalls of the first semiconductor region; the second semiconductor region (Fig. 2K, (224); [0023]) having a second width measured between sidewalls of the second semiconductor region, wherein the sidewalls of the second semiconductor region extend continuously from a top of the second semiconductor region to a bottom of the second semiconductor region, wherein the first width of the first semiconductor region is the same as the second width of the second semiconductor region (see Fig. 2K; [0031]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Ando ‘098, Chang ‘178, Yeo ‘056 and Kwok ‘364 by having the first semiconductor region having a first width measured between sidewalls of the first semiconductor region; the second semiconductor region having a second width measured between sidewalls of the second semiconductor region, wherein the sidewalls of the second semiconductor region extend continuously from a top of the second semiconductor region to a bottom of the second semiconductor region, wherein the first width of the first semiconductor region is the same as the second width of the second semiconductor region for making co-integrated SiGe and Si finFETs on a bulk substrate (see para. [0007]) as suggested by Loub ‘760.
Thus, Ando ‘098, Chang ‘178, Yeo ‘056, Kwok ‘364 and Loub ‘760 are shown to teach all the features of the claim with the exception of explicitly the limitations: “the protective cap disposed between the gate spacer and the LDD region; the fin protruding above the isolation region; the first lower region and the first upper region of the silicon germanium portion each being disposed above a top surface of the isolation region”.
However, it has been held to be within the general skill of a worker in the art to select the protective cap disposed between the gate spacer and the LDD region; the fin protruding above the isolation region; the first lower region and the first upper region of the silicon germanium portion each being disposed above a top surface of the isolation region on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. (see Fig. 3C, para. [0038] of Brunco (US 2014/0170839); as evidence). A person of ordinary skills in the art is motivated to select the protective cap disposed between the gate spacer and the LDD region; the fin protruding above the isolation region; the first lower region and the first upper region of the silicon germanium portion each being disposed above a top surface of the isolation region in order to improve the performance (e.g. increasing the drive currents…) of the MOSFET transistor device.
Regarding Claim 15, Ando ‘098, Chang ‘178, Yeo ‘056, Kwok ‘364 and Loub ‘760are shown to teach all the features of the claim with the exception of explicitly the limitations: “the first upper region has a same germanium concentration as the second upper region”.
However, it has been held to be within the general skill of a worker in the art to select the first upper region has a same germanium concentration as the second upper region on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. A person of ordinary skills in the art is motivated to select the first upper region has a same germanium concentration as the second upper region in order to improve the performance (e.g. increasing the drive currents…) of the MOSFET transistor device.
Regarding Claim 18, Yeo ‘056 teaches the protective cap (70) comprises a semiconductor material (Si; [0054]).
Regarding Claim 19, Ando ‘098 teaches the isolation region (Fig. 3, (300); [0036]) is around the silicon portion of the fin.
Regarding Claim 20, Ando ‘098 teaches the first upper region (502) extends along sidewalls and a top surface of the first lower region (504) (see Fig. 7).
Regarding Claim 21, Chang ‘178 teaches a gate stack (68/69; [0023]) on the silicon germanium portion of the fin; and an epitaxial source/drain region (64; [0023]) in the silicon germanium portion of the fin (SiGe fin (54); [0021]), wherein the second lower region and the second upper region of the LDD region (62; [0023]) are both disposed between the epitaxial source/drain region (62) and the gate stack (68/69).
Regarding Claim 22, Kwok ‘364 teaches the protective cap (44) is disposed between the gate stack (24/26) and the epitaxial source/drain region (42; [0023]).
Response to Arguments
Applicant’s arguments with respect to claims 1-12, 14-15 and 18-23, filed on January 30th, 2026, have been considered but are moot in view of the new ground of rejection.
Interviews After Final
Applicants note that an interview after a final rejection is permitted in order to place the application in condition for allowance or to resolve issues prior to appeal. However, prior to the interview, the intended purpose and content of the interview should be presented briefly, preferably in writing. Upon review of the agenda, the Examiner may grant the interview if the examiner is convinced that disposal or clarification for appeal may be accomplished with only nominal further consideration. Interviews merely to restate arguments of record or to discuss new limitations will be denied. See MPEP § 714.13
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Examiner Dzung Tran whose telephone number is (571) 270-3911. The examiner can normally be reached on M-F 8 AM-5PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Supervisor Sue Purvis can be reached on 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DZUNG TRAN/
Primary Examiner, Art Unit 2893