DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 20, 2026 has been entered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 9, 11 and 13 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Labonte et al. (US 2016/0336399, hereinafter “Labonte”, previously cited).
Regarding claim 9, Labonte teaches in Figs. 3-6 (annotated Fig. 6 shown below) and related text a semiconductor device, comprising:
a substrate (102, annotated Fig. 6 and ¶[0017]);
a first gate structure (150, annotated Fig. 6 and ¶[0017]) on the substrate;
a first spacer (160, annotated Fig. 6 and ¶[0017]) on a first sidewall of the first gate structure;
a second spacer (160, annotated Fig. 6 and ¶[0017]) on a second sidewall of the first gate structure opposite to the first sidewall;
a gate cap insulating layer (170, annotated Fig. 6 and ¶[0017]);
an interlayer dielectric (ILD) layer (190, annotated Fig. 6 and ¶[0017]); and
a first gate contact (185, annotated Fig. 6 and ¶[0017]) interposed between the first spacer (160, annotated Fig. 6) and the gate cap insulating layer (170, annotated Fig. 6), wherein the gate cap insulating layer (e.g. 170, annotated Fig. 6) is interposed between the first gate contact (185, annotated Fig. 6) and the second spacer (e.g. 160 on the right side of 185, annotated Fig. 6), preventing direct contact entirely between the first gate contact (185, annotated Fig. 6) and the second spacer (e.g. 160 on the right side of 185, annotated Fig. 6) along a first direction extending along the first gate structure; and
a first source/drain (S/D) structure (120, 180, annotated Fig. 6 and ¶¶[0017] and [0027]) including a first S/D conductive layer (i.e. section of 120 above a top elevation 110, annotated Fig. 6) disposed on a first S/D epitaxial layer (¶[0017]) and a first S/D cap insulating layer (180, annotated Fig. 6 and ¶[0017]) disposed on the first S/D conductive layer, wherein an upper surface of the first gate contact (185, annotated Fig. 6) is located at a different level from an upper surface of the first S/D conductive layer (annotated Fig. 6),
wherein:
a vertical center line of the first gate contact (185, annotated Fig. 6 and ¶[0017]) is offset from a vertical center line of the first gate structure (150, annotated Fig. 6 and ¶[0017]) , and
a height of the first spacer (i.e. height of 160 along 2nd direction, annotated Fig. 6) is different from a height of the second spacer (i.e. height of 160 along 2nd direction, annotated Fig. 6).
[AltContent: textbox (2nd spacer)]
[AltContent: ][AltContent: textbox (1st gate structure)][AltContent: ][AltContent: textbox (2nd gate structure)][AltContent: textbox (gate cap insulating layer)][AltContent: ][AltContent: ][AltContent: textbox (upper surface of 1st gate contact)][AltContent: ]
[AltContent: ][AltContent: textbox (2nd gate contact)][AltContent: oval][AltContent: ][AltContent: textbox (1st spacer)][AltContent: oval][AltContent: oval][AltContent: textbox (2nd direction)][AltContent: textbox (1st direction)][AltContent: arrow][AltContent: arrow][AltContent: textbox (1st S/D conductive layer)][AltContent: ][AltContent: textbox (upper surface of 1st S/D conductive layer)][AltContent: ][AltContent: textbox (S/D capping layer)][AltContent: ][AltContent: textbox (Annotated Figure)]
PNG
media_image1.png
517
787
media_image1.png
Greyscale
Regarding claim 11 (9), Labonte teaches wherein:
the first gate contact (185, annotated Fig. 6) penetrates the gate cap insulating layer (170, annotated Fig. 6) and contacts a side face of the gate cap insulating layer (170, annotated Fig. 6).
Regarding claim 13 (9), Labonte further teaches a second gate structure (150, annotated Fig. 6);
a second gate contact (185, annotated Fig. 6) disposed on the second gate structure (annotated Fig. 6),
wherein the first and second gate structures extend in the first direction (annotated Fig. 6), and the first gate contact and the second gate contact are aligned along a second direction (annotated Fig. 6) crossing the first direction.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Labonte as applied to claim 9 above, and further in view of Soss et al. (US 2011/0062501, hereinafter “Soss”, previously cited).
Regarding claim 10 (9), teaching of Labonte was discussed above in the rejection of claim 9. Labonte, however, does not explicitly teach that the first gate contact laterally extends beyond the first spacer.
Soss, in a similar field of endeavor, teaches in Figs. 9B and 9C, and related text, a gate contact (903, Fig. 9C) laterally extending beyond a gate first spacer (109, Fig. 1C) and a gate contact (902, Fig. 9B) not extending latterly beyond the gate spacer (Fig. 9B), in a similar manner to that disclosed by Labonte, are different types of gate contacts that can be used in order to meet specific device and/or manufacturing requirements.
Thus, since the prior art teaches all of the claimed elements using such elements would lead to predictable results and as such it would have been obvious to one of ordinary skill in the art to form the gate contact disclosed by Labonte so that it extends latterly beyond the gate spacer, as disclosed by Soss, in order to meet specific device and/or manufacturing requirements.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Labonte as applied to claim 9 above, and further in view of by Lin et al. (US 2015/0171084, hereinafter “Lin”, previously cited).
Regarding claim 12 (9), teaching of Labonte was discussed above in the rejection of claim 9. Labonte, however, does not explicitly teach wherein the first gate structure includes a high-k gate dielectric layer having a U-shape cross section and a work function metal layer having a U-shape cross section. Nonetheless, replacing the first gate structure disclosed by Labonte, with a gate structure that it includes a high-k gate dielectric layer having a U-shape cross section and a work function metal layer having a U-shape cross section, would be within the capabilities of one of ordinary skill in the art as evidenced by Lin. Specifically, Lin teaches in Figs. 16-17 and related text that a gate structure, can include a U-shaped high-k dielectric layer (168, Fig. 17 and ¶¶[0023], [0025], [0027] and [0054]) and work function metal (170, Fig. 17 and ¶¶[0023], [0025], [0027] and [0053]-[0055]) in order to meet specific design requirements for the semiconductor device.
Thus, since the prior art teaches all of the claimed elements using such elements would lead to predictable results, and as such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the U-shaped high-k dielectric layer and work function metal disclosed by Lin for the high-k dielectric layer disclosed by Labonte in order to meet specific design requirements for the semiconductor device.
Allowable Subject Matter
Claim(s) 1, 3-8, 14 and 16-22 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 1, the prior art of record, alone or in combination, and to the examiner’s knowledge does not teach, disclose, suggest, or render obvious, at least to the skilled artisan, the instant invention regarding a semiconductor device, particularly characterized by a first gate electrode the upper surface of which is located at a different level from an upper surface of the first S/D conductive layer where a thickness of a first gate cap insulating layer disposed on the first gate electrode is greater than a thickness of the S/D cap insulating layer disposed on the first S/D conductive layer and wherein the top surface of the first gate cap insulating layer is coplanar with a top surface of the first S/D cap insulating layer in combination with all other elements of the semiconductor device recited in claim 1. The closest prior art of record to Shieh et al. (US 2015/0118837) fails to teach the above noted elements of the claim. Claims 3-8 which either directly or indirectly depend from claim 1 and which include all of the limitations of claim 1 are allowed for similar reasons.
Regarding claim 14, the prior art of record, alone or in combination, and to the examiner’s knowledge does not teach, disclose, suggest, or render obvious, at least to the skilled artisan, the instant invention regarding a semiconductor device, particularly characterized by first to fourth gate structures formed across a same single fin structure with a first source/drain (S/D) structure disposed between the first and second gate structures, a second S/D structure disposed between the second and third gate structures, a third S/D structure disposed between the third and fourth gate structures, and a fourth S/D structure disposed adjacent to the fourth gate structure where a first S/D contact contacts the third S/D structure, and a second S/D contact contacts the fourth S/D structure, a third gate contact contacts a gate electrode of the fourth gate structure and the fourth gate structure, the third gate contact, the third S/D structure, the first S/D contact, the fourth S/D structure, and the second S/D contact form a first transistor on the same single fin structure, and the third gate contact is spaced apart from the same single fin structure in plan view in combination with all other elements of the semiconductor device recited in claim 14. The closest prior art of record to Song et al. (US 2015/0129971), Chen et al.(US 2014/0346575) and Kavalieros et al. (US 2007/0096293) fails to teach the above noted elements of the claim. Claims 16-22 which either directly or indirectly depend from claim 14 and which include all of the limitations of claim 14 are allowed for similar reasons.
Response to Arguments
Applicant's arguments filed on January 20, 2026 have been fully considered but they are not persuasive. To begin with, as noted in the Examiner Interview Summary dated December 4, 2025, no agreement was reached regarding specific amendments that would help overcome the cited prior art of record, but rather that additional clarifying language would be needed to distinguish the claimed invention over the cited prior art. Moreover, as discussed above in the rejection of claim 9, Labonte teaches all elements of the claim, including a first source/drain (S/D) structure (120, 180, annotated Fig. 6) including a first S/D conductive layer (i.e. section of 120 above a top elevation 110, annotated Fig. 6) disposed on a first S/D epitaxial layer (¶[0017]) and a first S/D cap insulating layer (180, annotated Fig. 6) disposed on the first S/D conductive layer, wherein an upper surface of the first gate contact (185, annotated Fig. 6) is located at a different level from an upper surface of the first S/D conductive layer (annotated Fig. 6). These elements are similar to those shown in Fig. 24 of the instant application, such as, a first source/drain (S/D) structure (70, 80, Fig. 24) including a first S/D conductive layer (70, Fig. 24) disposed on a first S/D epitaxial layer (25, Fig. 24) and a first S/D cap insulating layer (80, Fig. 24) disposed on the first S/D conductive layer (70, Fig. 24), wherein an upper surface of the first gate contact (100, Fig. 24) is located at a different level from an upper surface of the first S/D conductive layer (70, Fig. 24). Accordingly, contrary to the applicant’s arguments, the cited prior art teaches all elements of the amended claim 9.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANETA B CIESLEWICZ whose telephone number is 303-297-4232. The examiner can normally be reached M-F 8:30 AM - 2:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/A.B.C/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893