DETAILED ACTION
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-19 and 21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 1 ll. 21-22, it is indefinite as to whether the first functional circuit block refers to the first group of the plurality of FD-SOI transistors or some other block. For purposes of examination the former interpretation will be used.
Claim 1 recites the limitation "the first functional circuit block" in ll. 21-22. There is insufficient antecedent basis for this limitation in the claim.
Claims 2-29 and 20 do not clear up the deficiencies of claim 1.
In claim 13, ll. 4-5, it is indefinite as to whether the “a third second back gate line“ refers to the third, second, or some other back gate line. For purposes of examination the first interpretation will be used.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-9, 13-19, and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Du et al. (US 2015/0333056) (“Du”), Cheng et al. (US 2019/0181264) (“Cheng”), and Cai et al. (US 2012/0299105) (“Cai”).
With regard to claim 1, fig. 5 of Du discloses a microelectronic circuit structure comprising: a stack of bonded layers (50, 70) including a bottom layer 50 and at least one upper layer 70 bonded by hybrid direct bonding (“metal bonding pads 62, 78 of the interconnection metal layers 70, 76 are bonded (block 32) such as by oxide bonding”, par [0032]), the at least one upper layer 70 comprising an [insulating] layer (insulating layer between second back gate 84 and channel of second transistor 74) having a back surface (bottom surface of second back gate 84) and a front surface (top surface of channel of second transistor 74) closer to the bottom layer 50 than the back surface (bottom surface of 84); a plurality of silicon-on-insulator (SOI) transistors 74 built on the front surface of the [insulating] layer (insulating layer between second back gate 84 and channel of second transistor 74); and a plurality of back gate lines 84 on the back surface of the [insulating] layer (insulating layer between second back gate 84 and channel of second transistor 74) configured to provide a back gate bias 84 to the plurality of SOI transistors 74, wherein each back gate line 84 is electrically connected to a metal 86 of an interconnection separated from the back gate lines 84 by a passivation layer (insulating layer above back surface 80).
Du does not disclose an oxide layer; the back surface being an oxide surface exposed by removing a bulk silicon substrate from a silicon-on-insulator (SOI) substrate; and fully depleted silicon-on-insulator (FD-SOI) transistors; and a power supply circuitry connected to a first back gate line of the plurality of back gate lines to selectively provide a first back gate bias directly to a first portion of the oxide layer corresponding to a first functional circuit block including a first group of the plurality of FD-SOI transistors, and further connected to a second back gate line of the plurality of back gate lines to selectively provide a second back gate bias, different from the first back gate bias, directly to a second portion of the oxide layer corresponding to a second functional circuit block including a second group of the plurality of FD-SOI transistors different from the first group of the plurality of FD-SOI transistors, wherein the first functional circuit block is physically and functionally separate from the second functional circuit block.
However, figs. 4-5 of Cheng disclose an oxide layer 104; the back surface being an oxide surface (top of 104, fig. 4) exposed by removing a bulk silicon substrate 102 from a silicon-on-insulator (SOI) substrate (“SOI”, par [0028]); and fully depleted silicon-on-insulator (FD-SOI) transistors (“FDSOI transistor”, par [0031]).
Cheng does not disclose a power supply circuitry connected to a first back gate line of the plurality of back gate lines to selectively provide a first back gate bias directly to a first portion of the oxide layer corresponding to a first group of the plurality of FD-SOI transistors electrically arranged as processor transistors, and further connected to a second back gate line of the plurality of back gate lines to selectively provide a second back gate bias, different from the first back gate bias, directly to a second portion of the oxide layer corresponding to a second functional circuit block including a second group of the plurality of FD-SOI transistors electrically arranged as memory transistors, wherein the first functional circuit block and the second functional circuit block are integrated in a same one of the at least one upper layer.
However, fig.4 of Cai discloses a power supply circuitry connected to a first back gate line (“p-type back gate”, par [0035]) of the plurality of back gate lines 4 to selectively provide a first back gate bias directly to a first portion of the oxide layer BOX corresponding to a first group of the plurality of FD-SOI transistors (Logic) electrically arranged as processor transistors (Logic), and further connected to a second back gate line (4 under SRAM) of the plurality of back gate lines to selectively provide a second back gate bias (4 under SRAM), different from the first back gate bias (“p-type back gate”, par [0035]), directly to a second portion of the oxide layer BOX corresponding to a second functional circuit block (SRAM) including a second group of the plurality of FD-SOI transistors (SRAM) electrically arranged as memory transistors (SRAM), wherein the first functional circuit block (Logic) and the second functional circuit block (SRAM) are integrated in a same one of the at least one upper layer 3.
Therefore, it would have been obvious to one of ordinary skill in the art to form the transistors of Du with the FDSOI transistors as taught in Cheng in order to provide the capability of tuning transistor threshold voltage, and thus power management, by back gating. See par [0044] of Cheng.
It would have been obvious to one of ordinary skill in the art to form the transistors of Du with the two back gates as taught in Cai in order to provide different threshold voltages. See par [0035] of Cai.
With regard to claim 2, figure 5 of Du discloses that the metal 86 is disposed on and above an upper surface (surface below second back metal layers 86) of the passivation layer (insulating layer above second back surface 80).
With regard to claim 3, figure 5 of Du disclose at least one of the back gate lines 84 extend on the back surface of the oxide layer corresponding to multiple SOI transistors (right two second transistors 74) and provides the back gate bias (right two second back gates share a bias) to the multiple SOI transistors (right two second transistors 74).
Du does not disclose the fully depleted silicon-on-insulator (FD-SOI) transistors.
However, figs. 4-5 of Cheng disclose an oxide layer 104; the back surface being an oxide surface (top of 104, fig. 4) exposed by removing a bulk silicon substrate 102 from a silicon-on-insulator (SOI) substrate (“SOI”, par [0028]); and fully depleted silicon-on-insulator (FD-SOI) transistors (“FDSOI transistor”, par [0031]).
Therefore, it would have been obvious to one of ordinary skill in the art to form the transistors of Du with the FDSOI transistors as taught in Cheng in order to provide the capability of tuning transistor threshold voltage, and thus power management, by back gating. See par [0044] of Chen.
With regard to claim 5, figure 5 of Du discloses a plurality of contacts 76, wherein at least one contact 76 directly connects a metal feature (via between 76 and 78) of the interconnection to a metal feature 62 of the bottom layer 50.
With regard to claim 6, figure 5 of Du discloses a plurality of contacts 88, wherein at least one contact (rightmost 88) directly connects a metal feature 86 of the interconnection to a metal feature 76 of the at least one upper layer 70 on a front surface side (bottom of 74) of the [insulating] layer (insulating layer between 84 and 74).
Du does not explicitly disclose an oxide layer.
However, figs. 4-5 of Cheng discloses an oxide layer (“buried dielectric layer 104 can comprise any suitable dielectric material such as a buried oxide (or BOX) layer”, par [0026]).
Therefore, it would have been obvious to one of ordinary skill in the art to form the transistors of Du with the buried oxide layer as taught in Chen in order to provide the capability of tuning transistor threshold voltage, and thus power management, by back gating. See par [0044] of Chen.
With regard to claim 7, figure 5 of Du discloses a plurality of contacts (via between 86 and 84), wherein at least one contact (via between 86 and 84) directly connects a metal feature 86 of the interconnection to a back gate line 84.
With regard to claim 8, figure 5 of Du does not discloses at least one back gate line of the plurality of back gate lines is electrically connected to a direct bonding pad.
However, Du discloses at least one back gate line 84 of the plurality of back gate lines 84 and a direct bonding pad 78.
Therefore, it would have been obvious to one of ordinary skill in the art to form the backs gate of Du electrically connected with each other in order to vary the threshold voltage of the first and second transistors as needed or desired providing greater flexibility in circuit design. See par [0043] of Du.
With regard to claim 9, figure 5 of Du discloses the first group of the plurality of transistors 56 form part of a processor (“CPU”, par [0045]); and the second group of the plurality of transistors 74 form part of a memory (“memory”, par [00045]).
Du does not disclose FD-SOI transistors.
However, figs. 4-5 of Cheng discloses FD-SOI transistors (“FDSOI transistor”, par [0031]).
Therefore, it would have been obvious to one of ordinary skill in the art to form the transistors of Du with the FDSOI transistors as taught in Chen in order to provide the capability of tuning transistor threshold voltage, and thus power management, by back gating. See par [0044] of Cheng.
With regard to claim 13, figure 5 of Du discloses a second back gate line 52 of the plurality of back gate lines (84, 52) is configured to provide the second back gate bias 52 to the second group of transistors of the plurality of FD-SOI transistors 56 belonging to a first memory (“RAM”, par [0050]), and wherein the power supply circuitry is connected to a third back gate line 84 of the plurality of back gate lines (84, 52) is configured to provide a third back gate bias 84 to the third group of transistors of the plurality of FD-SOI transistors 74 belonging to a second memory operating at a lower speed (flash memory operate at lower speeds than RAM) than the first memory (“RAM”, par [0050]).
With regard to claim 14, figure 5 of Du disclose that the second gate bias of a first value 52 is configured to be provided to the first back gate line 52, and the third back gate bias signal 84 of a second value different (84 and 52 not connected) from the first value 52 is configured to be provided to the third back gate line 84.
With regard to claim 15, figure 5 of Du disclose a memory control circuit connected to the second group of transistors of the plurality of FD-SOI transistors belonging to the first memory (“RAM”, par [0050]) through a plurality of first data lines and connected to the third group of transistors of the plurality of FD-SOI transistors belonging to the second memory (“flash memory”, par [0050]) through a plurality of second data lines operating at a lower speed than the first data lines (flash memory operate at lower speeds than RAM).
With regard to claim 16, figure 5 of Du discloses a clock generating circuit configured to supply a first clock signal to the second group of transistors of the plurality of FD-SOI transistors belonging to the first memory (“RAM”, par [0050]) and supply a second clock signal at lower frequency (flash memory operate at lower speeds than RAM) than the first clock signal to the second group of transistors of the plurality of FD- SOI transistors belonging to the second memory (“flash memory”, par [0050]).
With regard to claim 17, figure 5 of Du the at least one upper layer (70, “additional tiers”, par [0034]) comprises a first upper layer 70 and a second upper layer (“additional tiers”, par [0034]) and the second upper layer (“additional tiers”, par [0034]) is bonded to the first upper layer 70 through direct bonding interconnect (DBI) (“additional second back metal bonding pads 92”, par [0034]).
With regard to claim 18, figure 5 of Du discloses that the bottom layer 50 comprises a silicon-on-insulator (SOI) integrated circuit (“silicon on insulator (SOI) first tier 50”, par [0030]).
With regard to claim 19, figure 5 of Du discloses that the bottom layer 50 comprises a bulk substrate integrated circuit (“first holding substrate 54 is bulk silicon”, par [0030]).
With regard to claim 21, Du does not disclose that at least one of the back gate lines extend laterally on the back surface of the oxide layer to overlap two or more of the FD-SOI transistors and serve as a common back gate electrode for the two or more of the FD-SOI transistors.
However, Cheng disclose the FD-SOI transistors (“FDSOI transistor”, par [0031]).
Cheng does not disclose that at least one of the back gate lines extend laterally on the back surface of the oxide layer to overlap two or more of the SOI transistors and serve as a common back gate electrode for the two or more of the SOI transistors.
However, fig. 1 of Mazure disclose that at least one of the back gate lines GP2 extend laterally on the back surface of the oxide layer (BOX) to overlap two or more of the SOI transistors (T4, T5, T6) and serve as a common back gate electrode GP2 for the two or more of the SOI transistors (T4, T5, T6).
Therefore, it would have been obvious to one of ordinary skill in the art to form the back gates of Du overlapping multiple transistors as taught in Mazure in order to control the threshold voltages of multiple transistors. See col. 7 ll. 46 of Mazure.
With regard to claim 22, fig. 5 of Du discloses that the each back gate line 84 and the metal (86 above 84) are directly connected to each other by opposing ends of the single conductive pathway 88 extending in a stacking direction.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Du et al. (US 2015/0333056) (“Du”), Cheng et al. (US 2019/0181264) (“Cheng”), Cai et al. (US 2012/0299105) (“Cai”), and Lebby et al. (US 2008/0135924) (“Lebby”).
With regard to claim 4, Du does not disclose further comprising: a group of FD-SOI transistors of the plurality of FD-SOI transistors with no back gate line extending on the back surface of the oxide layer corresponding to the group of FD-SOI transistors.
However, Cheng disclose the plurality of FD-SOI transistors (“FDSOI transistor”, par [0031]).
Cheng and Cai do not disclose a group of FD-SOI transistors with no back gate line extending on the back surface of the oxide layer corresponding to the group of FD-SOI transistors.
However, fig. 4 of Lebby discloses a group of FD-SOI transistors (“FDSOI MOSFETs”, par [0023]) with no back gate line extending on the back surface of the oxide layer BOX corresponding to the group of FD-SOI transistors (“FDSOI MOSFETs”, par [0023]).
Therefore, it would have been obvious to one of ordinary skill in the art to form the transistor of Du with no back gate as taught in Lebby in provide improved methods and apparatus for controlling short channel effects, leakage, and threshold effects of FDSOI MOSFETs. See par [0023] of Lebby.
Claims 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Du et al. (US 2015/0333056) (“Du”), Cheng et al. (US 2019/0181264) (“Cheng”), Cai et al. (US 2012/0299105) (“Cai”), and Hanafi et al. (US 2005/0204319) (“Hanafi”).
With regard to claim 10, Du, Cheng, and Cai do not disclose the first back gate bias of a first value is configured to be applied to the first back gate line during an idle state of the processor and the first back gate bias signal of a second value different from the first value is configured to be applied to the first back gate line during a computing state of the processor.
However, Hanafi discloses the first back gate bias (“nMOSFET back-gate”, par [0004]) of a first value (proper bias applied to nMOSFET back-gate to change the threshold voltage to “high values”, par [0004]) is configured to be applied to the first back gate line (“nMOSFET back-gate”, par [0004]) during an idle state of the processor (“idle periods”, par [0004]) and the first back gate bias of a second value (proper bias applied to nMOSFET back-gate to change the threshold voltage to “low values”, par [0004]) different from the first value (proper bias applied to nMOSFET back-gate to change the threshold voltage to “high values”, par [0004]) is configured to be applied to the first back gate line (“nMOSFET back-gate”, par [0004]) during a computing state (“active periods for maximum performance”, par [0004]) of the processor.
Therefore, it would have been obvious to one of ordinary skill in the art to form the back gates of Du with applying the proper bias as taught in Hanafi in order to dynamically change the threshold voltage of the MOSFET and provide maximum performance during system active periods and minimum leakage power during system idle periods. See par [0004] of Hanafi.
With regard to claim 11, Du Cheng, and Cai do not disclose a third back gate bias of a third value different from the first value and the second value is provided to the first back gate line.
However, Hanafi discloses a third back gate bias (between high and low values, par [0004]) different from the first value (“high values”, par [0004]) and the second value (“low value”, par [0004]) is provided to the first back gate line (“nMOSFET back-gate”, par [0004]).
Therefore, it would have been obvious to one of ordinary skill in the art to form the back gates of Du with applying the proper bias as taught in Hanafi in order to dynamically change the threshold voltage of the MOSFET and provide maximum performance during system active periods and minimum leakage power during system idle periods. See par [0004] of Hanafi.
With regard to claim 12, Du, Cheng, and Cai do not discloses the second value is adjustable based on a fluctuating computational workload.
However, Hanafi discloses the second value (proper bias applied to nMOSFET back-gate to change the threshold voltage to “low values”, par [0004]) is adjustable based on a fluctuating computational workload (“system active periods”, par [0004]).
Therefore, it would have been obvious to one of ordinary skill in the art to form the back gates of Du with applying the proper bias as taught in Hanafi in order to dynamically change the threshold voltage of the MOSFET and provide maximum performance during system active periods. See par [0004] of Hanafi.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/BENJAMIN TZU-HUNG LIU/Primary Examiner, Art Unit 2893