Detailed Action
This office action is in response to the request for continued examination filed on July 3rd, 2025. Claims 1, 6-16, 18, and 20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on July 3rd, 2025, has been entered.
Response to Arguments
Applicant's arguments filed July 3rd, 2025, have been fully considered but they are not persuasive.
Applicant argues (pgs. 8-16, “Remarks”) that Ohguro and the other cited references fail to teach the limitations presented in amended Claims 1, 15, and 16.
However, as seen below, Claim 1 is rejected by the combination of Lamy, Zia, and Ohguro. Claims 15 and 16 are rejected by Lamy, Zia, Ohguro, and Koezuka.
Therefore, applicant’s arguments are not persuasive and are moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6, and 8-14 are rejected under 35 U.S.C. 103 as being unpatentable over Lamy et al. (2018/0358381 A1; hereinafter Lamy) in view of Zia et al. (2006/0105508 A1; hereinafter Zia) and Ohguro (2006/0261410 A1; hereinafter Ohguro).
Regarding Claim 1, Lamy (fig. 5D) teaches a semiconductor-on-insulator multilayer structure ([0128], 200), comprising:
a back stack ([0127], 102, 104, 106) including the following layers from a back side (bottom side of 200, see fig. 5D) to a front side (top side of 200, see fig. 5D) of the structure: a semiconductor carrier substrate (102) having an electrical resistivity between 500 Ω*cm and 30 kΩ*cm ([0089], 102 has an electrical resistivity more than about 0.5 kΩ*cm),
a first electrically insulating layer (106),
a first semiconductor layer (104), and
a polysilicon charge-trapping layer ([0127], 108) arranged between the semiconductor carrier substrate (102) and the first electrically insulating layer (106);
at least one trench isolation ([0131]-[0132], 202, 204) that extends through the back stack (102, 104, 106) at least down to the first electrically insulating layer (106);
at least one FD-SOI first region ([0134], region 216 containing FDSOI components 214) [] and
at least one digital component ([0004], [0134], FDSOI components 214 formed for digital applications) in the active layer ([0090], electronic components are made in layer 104 and can be considered as the active layer), wherein the active layer (104) comprises a fully depleted semiconductor layer ([0001], FDSOI is fully depleted), [] and
at least one RF-SOI second region ([0136], region 222 containing RF components 220) electrically isolated (see fig. 5D) from the at least one FD-SOI region (216) by the at least one trench isolation (202, 204), the at least one RF-SOI second region (222) comprising at least one radiofrequency component ([0136], 220) in the active layer (104) and plumb (see fig. 5D) with the first electrically insulating layer (106).
Lamy doesn’t teach a front stack, the front stack arranged on the back stack, the front stack comprising: a second electrically insulating layer arranged on the first semiconductor layer, a second semiconductor layer arranged on the second electrically insulating layer, the second semiconductor layer being an active layer and the first electrically insulating layer has a thickness larger than that of the second electrically insulating layer, and the first semiconductor layer has a thickness larger than that of the active layer.
However, Zia (fig. 12) teaches a front stack ([0014], 22, 24), the front stack (22, 24) arranged on the back stack ([0013], 16, 18, 20), the front stack (22, 24) comprising: a second electrically insulating layer (22) arranged on the first semiconductor layer (20), a second semiconductor layer (24) arranged on the second electrically insulating layer (22), the second semiconductor layer (24) being an active layer ([0017], devices are formed in 24 and may be considered the active layer), and at least one digital component ([0017], 44) in the active layer (24) and at least one radiofrequency component ([0017], 40) in the active layer (24). Zia also teaches that a dual SOI substrate provides an improved method for integrating non-MOS transistor devices with CMOS electronic devices on the same integrated circuit allowing for high yields ([0006]-[0007]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor-on-insulator device of Lamy to include the dual SOI structure of Zia to integrate non-MOS and CMOS devices while allowing for high yields.
Zia doesn’t explicitly teach and the first electrically insulating layer has a thickness larger than that of the second electrically insulating layer, and the first semiconductor layer has a thickness larger than that of the active layer.
However, Ohguro (fig. 1) teaches the first electrically insulating layer ([0028], 20) has a thickness larger ([0029], 20 has a thickness of 1000 nm while 40 has a thickness of 10 nm) than that of the second electrically insulating layer ([0028], 40), and the first semiconductor layer ([0028], 30) has a thickness larger ([0029], 30 has a thickness of 1500 nm while 50 has a thickness of 10 nm) than that of the active layer ([0028], 50). Ohguro also teaches that these thicknesses are adequately controlled for digital and analog circuits respectively ([0058]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor-on-insulator device of Zia to include the various thicknesses of Ohguro to control the thicknesses as needed for digital and analog circuits.
Regarding Claim 6, Lamy (fig. 5D) teaches the structure of claim 1, wherein the first semiconductor layer (104) comprises crystalline material ([0090], monocrystalline silicon).
Regarding Claim 8, Zia doesn’t teach the structure of claim 1, wherein the second semiconductor layer comprises crystalline material.
However, Ohguro (fig. 1) teaches the second semiconductor layer (50) comprises crystalline material ([0029]) while yielding the predictable results of a functional semiconductor layer.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the crystalline material of Ohguro for the silicon of Zia since simple substitution of semiconductor layers for another is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Regarding Claim 9, Lamy (fig. 5D) teaches the structure of claim 1, wherein the first electrically insulating layer (106) is a layer of silicon oxide ([0091], SiO2).
Regarding Claim 10, Zia doesn’t teach the structure of claim 1, wherein the second electrically insulating layer is a layer of silicon oxide.
However, Ohguro (fig. 1) teaches the second electrically insulating layer (40) is a layer of silicon oxide ([0029]) while yielding the predictable results of a functional buried oxide.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the silicon oxide of Ohguro for the oxide of Zia since simple substitution of buried oxides for another is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Regarding Claim 11, Lamy (fig. 5D) teaches the structure of claim 1, wherein the first electrically insulating layer (106) has a thickness between 50 nm and 1500 nm ([0091], has a thickness between about 10 nm and 100 nm).
Regarding Claim 12, Ohguro (fig. 1) teaches the structure of claim 1, wherein the second electrically insulating layer (40) has a thickness between 10 nm and 100 nm ([0029], 40 has a thickness of 10 nm).
Regarding Claim 13, Lamy (fig. 5D) teaches the structure of claim 1, wherein the first semiconductor layer (104) has a thickness between 10 nm and 200 nm ([0090], has a thickness between about 10 nm and 20 nm).
Regarding Claim 14, Ohguro (fig. 1) teaches the structure of claim 1, wherein the active layer (50) has a thickness between 3 nm and 30 nm ([0029], 50 has a thickness of 10 nm).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Lamy, Zia, and Ohguro as applied to Claim 1 above, and further in view of Sun (U.S. Patent Number 9,824,891 B1; hereinafter Sun).
Regarding Claim 7, Lamy doesn’t teach the structure of claim 1, wherein the first semiconductor layer comprises amorphous material.
However, Sun (fig. 1) teaches that the first semiconductor layer (Col. 3, lines 15-40, labeled amorphous silicon) comprises amorphous material. Sun also teaches that a SOI wafer with amorphous silicon effectively inhibits parasitic conductivity of the surface of the substrate (Col. 3, lines 15-40).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor-on-insulator device of Lamy to include the amorphous silicon of Sun to inhibit parasitic capacitance.
Claims 15-16, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lamy in view of Zia and Koezuka (2011/0244660 A1; hereinafter Koezuka).
Regarding Claim 15, Lamy (fig. 5D) teaches a method of fabricating a semiconductor-on-insulator multilayer structure ([0128], 200), comprising the following steps:
providing a first donor substrate ([0127], 104), []
transferring the first semiconductor layer ([0127], 104) to a semiconductor carrier substrate ([0127], 102),
a first electrically insulating layer ([0127], 106) being at an interface between the donor substrate (104) and the semiconductor carrier substrate (102) so as to form a back stack (102, 104, 106) comprising the semiconductor carrier substrate (102), the first electrically insulating layer (106) and the transferred first semiconductor layer (104), []
comprising an active layer ([0090], electronic components are made in layer 104 and can be considered as the active layer), wherein the active layer (104) comprises a fully depleted semiconductor layer ([0001], FDSOI is fully depleted), []
forming at least one trench isolation ([0131]-[0132], 202, 204) that extends [] through the back stack (102, 104, 106) at least down to the first electrically insulating layer (106), in order to electrically isolate two adjacent regions, including at least one FD-SOI region ([0134], region 216 containing FDSOI components 214) and at least one RF-SOI region ([0136], region 222 containing RF components 220), and producing:
at least one digital component ([0004], [0134], FDSOI components 214 formed for digital applications) in the active layer (104) within the at least one FD-SOI region (216), and
at least one radiofrequency component ([0136], 220) in the active layer (104) and plumb (see fig. 5D) with the first electrically insulating layer (106).
Lamy doesn’t teach providing a second donor substrate, transferring the second semiconductor layer to the back stack, a second electrically insulating layer being at the interface between the second donor substrate and the back stack, so as to form a front stack comprising the second electrically insulating layer and the transferred second semiconductor layer.
However, Zia (fig. 12) teaches providing a second donor substrate ([0014], 24), transferring the second semiconductor layer ([0014], 24) to the back stack ([0013], 16, 18, 20), a second electrically insulating layer ([0014], 22) being at the interface between the second donor substrate (24) and the back stack (16, 18, 20), so as to form a front stack (22, 24) comprising the second electrically insulating (22) layer and the transferred second semiconductor layer (24), the second semiconductor layer (24) being an active layer ([0017], devices are formed in 24 and may be considered the active layer). Zia also teaches that a dual SOI substrate provides an improved method for integrating non-MOS transistor devices with CMOS electronic devices on the same integrated circuit allowing for high yields ([0006]-[0007]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor-on-insulator device of Lamy to include the dual SOI structure of Zia to integrate non-MOS and CMOS devices while allowing for high yields. Furthermore, it would have been obvious for the trench isolations of Lamy to extend through the front stack of Zia to electrically separate the FDSOI region from the RFSOI region in the front stack.
Lamy and Zia fail to teach forming a weakened zone in the first donor substrate, so as to delineate a first semiconductor layer, forming a weakened zone in the second donor substrate, so as to delineate a second semiconductor layer.
However, Koezuka (see fig. 2A-C) teaches providing a first donor substrate ([0041], 100), forming a weakened zone ([0059], 108) in the first donor substrate (100), so as to delineate a first semiconductor layer ([0076], 110). Koezuka also teaches that by forming a semiconductor layer through this process may be made to have a high degree of flatness and can be used to make high-performance and highly reliable semiconductor elements ([0029]-[0031]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method for fabricating a semiconductor-on-insulator device of Lamy to include the method for forming a first semiconductor layer of Koezuka to form semiconductor layers with a high degree of flatness.
Additionally, it would have then been obvious to one of ordinary skill in the art to apply the teachings of Koezuka to the second semiconductor layer of Zia in order to provide a semiconductor layer with a high degree of flatness. Therefore, the combination of Zia and Koezuka teaches providing a second donor substrate, forming a weakened zone in the second donor substrate, so as to delineate a second semiconductor layer.
Regarding Claim 16, Lamy (fig. 5D) teaches a method of fabricating a semiconductor-on-insulator multilayer structure ([0128], 200), comprising the following steps:
forming a back stack ([0127], 102, 104, 106) by depositing a first semiconductor layer (104) on a carrier substrate (102) covered with a first electrically insulating layer (106), []
the [] semiconductor layer (104) comprises a fully depleted semiconductor layer ([0001], FDSOI is fully depleted), []
forming at least one trench isolation ([0131]-[0132], 202, 204) that extends [] through the back stack (102, 104, 106) at least down to the first electrically insulating layer (106), in order to electrically isolate two adjacent regions, including at least one FD-SOI region ([0134], region 216 containing FDSOI components 214) and at least one RF-SOI region ([0136], region 222 containing RF components 220), and producing:
at least one digital component ([0004], [0134], FDSOI components 214 formed for digital applications) in the active layer (104) within the at least one FD-SOI region (216), and
at least one radiofrequency component ([0136], 220) in the active layer (104) and plumb (see fig. 5D) with the first electrically insulating layer (106).
Lamy doesn’t teach providing a donor substrate, transferring the second semiconductor layer to the back stack, a second electrically insulating layer being at the interface between the second donor substrate and the back stack, so as to form a front stack on the back stack.
However, Zia (fig. 12) teaches providing a donor substrate ([0014], 24), transferring the second semiconductor layer ([0014], 24) to the back stack ([0013], 16, 18, 20), a second electrically insulating layer ([0014], 22) being at the interface between the second donor substrate (24) and the back stack (16, 18, 20), so as to form a front stack (22, 24) on the back stack (16, 18, 20), the second semiconductor layer (24) being an active layer ([0017], devices are formed in 24 and may be considered the active layer). Zia also teaches that a dual SOI substrate provides an improved method for integrating non-MOS transistor devices with CMOS electronic devices on the same integrated circuit allowing for high yields ([0006]-[0007]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor-on-insulator device of Lamy to include the dual SOI structure of Zia to integrate non-MOS and CMOS devices while allowing for high yields. Furthermore, it would have been obvious for the second semiconductor layer of Zia maintain the fully depleted feature of Lamy and for the trench isolations of Lamy to extend through the front stack of Zia to electrically separate the FDSOI region from the RFSOI region in the front stack.
Lamy and Zia fail to teach forming a weakened zone in the donor substrate, so as to delineate a second semiconductor layer.
However, Koezuka (see fig. 2A-C) teaches providing a donor substrate ([0041], 100), forming a weakened zone ([0059], 108) in the donor substrate (100), so as to delineate a second semiconductor layer ([0076], 110). Koezuka also teaches that by forming a semiconductor layer through this process may be made to have a high degree of flatness and can be used to make high-performance and highly reliable semiconductor elements ([0029]-[0031]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method for fabricating a semiconductor-on-insulator device of Zia to include the method for forming a second semiconductor layer of Koezuka to form semiconductor layers with a high degree of flatness.
Regarding Claim 18, Lamy (fig. 5D) teaches the method of claim 16, further comprising, before the transferring step ([0103], layers are formed successively), forming a charge-trapping layer ([0127], 108) on the carrier substrate (102), the charge-trapping layer (108) being arranged between the carrier substrate (102) and the first electrically insulating layer (106).
Regarding Claim 20, Lamy (fig. 5D) teaches the method of claim 15, further comprising, before the transferring step ([0103], layers are formed successively), forming a charge-trapping layer ([0127], 108) on the carrier substrate (102), the charge-trapping layer (108) being arranged between the carrier substrate (102) and the first electrically insulating layer (106).
Conclusion
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/A.H./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 January 20, 2026