Prosecution Insights
Last updated: April 19, 2026
Application No. 17/421,367

DISPLAY DEVICE AND MANUFACTURING METHOD THEREFOR

Final Rejection §112
Filed
Jul 07, 2021
Examiner
BELL, LAUREN R
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Display Co., Ltd.
OA Round
4 (Final)
40%
Grant Probability
At Risk
5-6
OA Rounds
3y 7m
To Grant
70%
With Interview

Examiner Intelligence

Grants only 40% of cases
40%
Career Allow Rate
148 granted / 375 resolved
-28.5% vs TC avg
Strong +31% interview lift
Without
With
+30.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
61 currently pending
Career history
436
Total Applications
across all art units

Statute-Specific Performance

§103
42.1%
+2.1% vs TC avg
§102
19.7%
-20.3% vs TC avg
§112
33.1%
-6.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 375 resolved cases

Office Action

§112
DETAILED ACTION Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claim 1, 3-4, 8-9, and 11-19 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Regarding claim 1, the limitation “a first substrate including: a plurality of pixel areas configured to display different colors, each of the pixel areas including…” does not appear to have support in the originally filed disclosure. Specifically, the disclosure appears to provide that the areas of different color are “sub-pixel area[s]” and the pixel areas as an arrangement of plural sub-pixels. Accordingly, there is no disclosure of a pixel area including the elements required by the claim and “configured to display different colors.” Regarding claim 1, the limitation “a pixel circuit layer on the first conductive layer in the second area and comprising a transistor and a power line,” does not appear to have support in the originally filed disclosure. Specifically, the power line is not disclosed as being on the first conductive layer with the transistor. Regarding claim 1, the limitation “the first conductive layer has a same area as an area of the third bank pattern in a plan view,” does not appear to have support in the originally filed disclosure. Specifically, it is noted that no plan view is shown which includes an area of the first conductive layer and the third bank pattern, and therefore the relationship cannot be established. Regarding claim 13, the limitation “the second electrode extends to the non-display area,” does not appear to have support in the originally filed disclosure. Specifically, the claimed second area is understood to be NEMA1 and NEMA2 and the claimed non-display area is understood to be NDA. There is no disclosure of the second electrode extending to NDA or NEMA2 being in NDA. Note the dependent claims do not cure the deficiencies of the claims on which they depend. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 1, 3-4, 8-9, and 11-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 1, the limitation “a first substrate including: a plurality of pixel areas configured to display different colors, each of the pixel areas including…” is unclear as to what is required by the “pixel area” displaying different colors. Specifically, the disclosure appears to define the areas of different color as “sub-pixel area[s]” and the pixel areas as an arrangement of plural sub-pixels. Accordingly, it is unclear as to what is required of the claimed “pixel areas” recited to include the elements which appear to be associated with a sub-pixel area but also required by the claim to be “configured to display different colors.” Regarding claim 1, the limitation “a pixel circuit layer on the first conductive layer in the second area and comprising a transistor and a power line, wherein the transistor is in direct physical contact with and connected to the first conductive layer, and wherein the power line is located on and connected to the second conductive layer in the second area” is unclear as to what is required. Specifically, the first part of the limitation appears to require the pixel circuit to be “on the first conductive layer,” and also comprising the transistor and the power line, and would therefore be understood as requiring the power line to be on the first conductive layer. The second portion of the limitation, however, appears to be contradictory in that it requires the power line to be “on and connected to the second conductive layer. Accordingly, it is unclear what structure is required by the claim. Regarding claim 1, the limitations “a first (second/third) bank pattern interposed between the first substrate and the first electrode in the first area” are unclear as to how they are related to “a first substrate including: a plurality of pixel areas configured to display different colors, each of the pixel areas including…” Specifically, the “substrate” is recited as comprising the pixel area. The pixel area is then recited as comprising the first (second/third) bank. It is therefore unclear as to how the bank can be “between the substrate” and another element, as the bank is understood to be a part of the pixel area, which is a part of the substrate. Regarding claim 1, the limitation “the first end and the second end are spaced apart in a second direction that is perpendicular to the thickness direction and different from the first direction, and the first conductive semiconductor layer, the active layer, and the second conductive semiconductor layer are stacked in the second direction,” is unclear as to how the second direction is related to the longitudinal direction previously recited. Regarding claim 3, the limitation “the pixel circuit layer further comprises a transmissive component overlapping the first area of the first substrate” is unclear as to how it are related to “a first substrate including: a plurality of pixel areas configured to display different colors, each of the pixel areas including…,” recited in claim 1. Specifically, the “substrate” is recited as comprising the pixel area, the pixel area is then recited as comprising the pixel circuit layer. It is therefore unclear as to how the transmissive component can be “overlapping the first substrate,” as the component is understood to be a part of the pixel area, which is a part of the substrate. Regarding claim 13, the limitation “the second electrode extends to the non-display area,” is unclear as to what is required. Specifically the claimed non-display area is understood to be NDA. As there is no disclosure of the second electrode extending to NDA or NEMA2 being in NDA, it is unclear what is meant or required by “non-display area,” ”extends to.” Regarding claim 17, the limitation “a bank” is unclear as to how it is related to the first/second/third banks of claim 1. Note the dependent claims necessarily inherit the indefiniteness of the claims on which they depend. Response to Arguments Applicant's arguments filed 12/29/2025 have been fully considered but are moot in view of the new grounds of rejection presented above. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lauren R Bell whose telephone number is (571)272-7199. The examiner can normally be reached M-F 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LAUREN R BELL/Primary Examiner, Art Unit 2896 2/13/2026
Read full office action

Prosecution Timeline

Jul 07, 2021
Application Filed
May 20, 2024
Non-Final Rejection — §112
Aug 07, 2024
Examiner Interview Summary
Aug 07, 2024
Applicant Interview (Telephonic)
Aug 23, 2024
Response Filed
Nov 14, 2024
Final Rejection — §112
Feb 04, 2025
Applicant Interview (Telephonic)
Feb 10, 2025
Examiner Interview Summary
Feb 19, 2025
Response after Non-Final Action
Mar 18, 2025
Request for Continued Examination
Mar 19, 2025
Response after Non-Final Action
Sep 22, 2025
Non-Final Rejection — §112
Nov 21, 2025
Examiner Interview Summary
Nov 21, 2025
Applicant Interview (Telephonic)
Dec 29, 2025
Response Filed
Feb 13, 2026
Final Rejection — §112
Apr 16, 2026
Applicant Interview (Telephonic)
Apr 16, 2026
Examiner Interview Summary

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604518
SEMICONDUCTOR DEVICE
2y 5m to grant Granted Apr 14, 2026
Patent 12588472
VIA ACCURACY MEASUREMENT
2y 5m to grant Granted Mar 24, 2026
Patent 12581934
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
2y 5m to grant Granted Mar 17, 2026
Patent 12575197
PHOTONIC STRUCTURE AND METHODS OF MANUFACTURING
2y 5m to grant Granted Mar 10, 2026
Patent 12563957
DISPLAY DEVICE
2y 5m to grant Granted Feb 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

5-6
Expected OA Rounds
40%
Grant Probability
70%
With Interview (+30.7%)
3y 7m
Median Time to Grant
High
PTA Risk
Based on 375 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month