Prosecution Insights
Last updated: July 17, 2026
Application No. 17/423,321

DISPLAY DEVICE

Non-Final OA §103
Filed
Jul 15, 2021
Priority
Jan 15, 2019 — RE 10-2019-0005433 +1 more
Examiner
TRAN, TONY
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Display Co., Ltd.
OA Round
7 (Non-Final)
70%
Grant Probability
Favorable
7-8
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 70% — above average
70%
Career Allowance Rate
608 granted / 863 resolved
+2.5% vs TC avg
Strong +34% interview lift
Without
With
+33.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
47 currently pending
Career history
922
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
82.9%
+42.9% vs TC avg
§102
16.1%
-23.9% vs TC avg
§112
0.5%
-39.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 863 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/22/2026 has been entered. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 3, 6-8, 15, 17-18, 20, 21, and 22-23, 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over KIM (Pub. No.: US 2018/0012876) in view of SATO et al. (Pub. No.: US 2020/0043931) (hereinafter SATO) and further in view of DO (Pub. No.: US 2017/0138549) and another SATO (Pub. No.: US 2015/0206929) (hereinafter `929). Re claim 1, KIM, FIG. 17 teaches a display device comprising: a light-emitting element (30, ¶ [0116]); a first transistor (TFT1, [0120]) configured to transmit a driving current to the light-emitting element; a second transistor (TFT2, [0121]) configured to transmit a data signal to the first transistor, a via layer (605, ¶ [0130], note that 605 is the same scenario as via layer 200 of FIG. 10 in Applicant’ specification, ¶ [0152]) between the first and second transistors (TFT1/TFT2) and the light-emitting element (30), the via layer being an organic film selected from acrylic resin, epoxy resin, phenolic resin, polvamide resin, and polvimide resin (605, [0130]); and an electrode line (12/52) on the via layer (613) connecting the first transistor (TFT1) to the light-emitting element (30), PNG media_image1.png 612 761 media_image1.png Greyscale a first protection film (602, FIG. 18) on a first source electrode ([SE], FIG. 18 [as shown above]) and a first drain electrode [DE] of the first transistor (TFT1); a first voltage line (614, note that the drain electrode connected to electrical voltage of 5V, therefore, it is considered as the VOLTAGE LINE) on the first protection film (602) and electrically connected to the first transistor (TFT1), the first protection film (602) being between the first source [SE] and drain electrodes [DE] and the first voltage line (614); and a second protection film (604) on the first voltage line (614) and between the first protection film (602) and the via layer (605), the first transistor includes a first active layer (611), wherein the first active layer of the first transistor includes an oxide semiconductor (611, [0122]). the second transistor includes a second active layer containing an organic semiconductor (621, [0122]), the electrode line comprises a reflective layer (12, [0055]) and an electrode layer (52) on the reflective layer, the via layer (605) and the first (602) and second (604) protection films defines a contact hole (which later on it was filling up by 613 and 12) penetrating the via layer (613) and the first (602) and second (604) protection films, at least a portion of the reflective layer (12) is disposed in the contact hole, and the light-emitting element includes a first conductivity type semiconductor having a first polarity (p-type 34, [0049]); a second conductivity type semiconductor having a second polarity different from the first polarity (n-type 33, [0048]); and a third active material layer (35) disposed between the first conductivity type semiconductor (34) and the second conductivity type semiconductor (33). KIM fails to teach a second active layer containing an oxide semiconductor. However, KIM discloses a first active layer containing an oxide semiconductor (611, [0122]). It would have been for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching since it has been held to be within the general skill of a worker in the art to select the same material for second active region via the first active region on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 277 F.2d 197, 125 USPQ 416, as taught by KIM. Moreover, KIM fails to teach at least a portion of the electrode layer is disposed in the contact hole. SATO teaches at least a portion of the electrode layer (162a, FIG. 1, ¶ [0133]) is disposed in the contact hole. It would have been for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of miniaturized the foot print of manufacturing the semiconductor device as taught by SATO, [0010]. Additionaly, KIM fails to teach a length of the light-emitting element being in a range of about 4 µm to about 7 µm and an aspect ratio of the light-emitting element being in a range of about 1.2 to about 100 DO teaches a length of the light-emitting element being in a range of about 4 µm to about 7 µm and an aspect ratio of the light-emitting element being in a range of about 1.2 to about 100 ¶ [0076]. It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of ultilizing the small nano-scale LED devices as taught by DO, [0076]. Finally, KIM/SATO/DO fails to teach a light blocking layer below the first active layer and separated from the first active layer by a buffer layer, and the light blocking layer overlaps a portion of the first voltage line in a plan view. `929 teaches a light blocking layer (172, FIG. 7, ¶ [0040]) below the first active layer (224) and separated from the first active layer by a buffer layer (165), and the light blocking layer (172) overlaps a portion of the first voltage line (223, note that it is the SAME DRAIN electrode as discloses in KIM, FIG. 18 as 614) in a plan view (by looking down from the top), It would have been for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of improving visibility and response speed as taught by `929 [0005]. Re claim 3, in the combination, KIM, FIG. 17 teaches the display device of claim 2, wherein the oxide semiconductor includes indium-gallium-tin oxide (IGTO) or indium-gallium-zinc-tin oxide (IGZTO) [0122]. PNG media_image2.png 592 792 media_image2.png Greyscale Re claim 6, KIM, FIG. 17 [as shown above] teaches the display device of claim 1, wherein the first active layer includes: a first conductive region [FCR], a second conductive region [SCR], and a channel region [CR] disposed between the first conductive region and the second conductive region. Re claim 7, KIM, FIG. 17 teaches the display device of claim 6, wherein the first transistor further includes: a third gate electrode (612) disposed on the first active layer; the first source electrode (614) that is electrically connected to the first conductive region [FCR] through a first contact hole (the opening before forming 614) passing through an interlayer insulating film (604) disposed on the third gate electrode; and the first drain electrode (613) that is connected to the second conductive region [SCR] through a second contact hole (the opening before forming 613) passing through the interlayer insulating film. Re claim 8, KIM, FIG. 17 teaches the display device of claim 7, wherein the first active layer includes polycrystalline silicon (611, [0122]). Re claim 15, KIM, FIG. 17 teaches a display device comprising: a base layer (5); a first electrode (12/52) and a second electrode (11/51) spaced apart from each other on the base layer in a first direction (horizontal); at least one light-emitting element (30) connected to at least one of the first electrode (12/52) and the second electrode (11/51) and having a shape extending in the first direction; a driving transistor (TFT1, [0120]) configured to transmit a driving current to the at least one light-emitting element (30), a via layer (605) between the first and second electrode and the driving transistor, a first protection film (602, FIG. 18) on a source electrode and a drain electrode (613/614) of the driving transistor (TFT1), the first protection film (602) being between the first source [SE] and drain electrodes [DE] and the first voltage line (614); a first voltage line (614, note that the drain electrode connected to electrical voltage of 5V, therefore, it is considered as the VOLTAGE LINE) on the first protection film and electrically connected to the driving transistor (TFT1); and a second protection film (604) on the first voltage line (614) and between the first protection film (602) and the via layer (605), wherein the driving transistor includes a first active layer having an oxide semiconductor (611, [0122]), and the light-emitting element (30) includes a first conductivity type semiconductor including having a first polarity (p-type layer 34, [0049]); a second conductivity type semiconductor (n-type layer 33, [0048]) having a second polarity different from the first polarity (p-type layer 34); and a second active material layer (35, [0050]) disposed between the first conductivity type semiconductor and the second conductivity type semiconductor, the first electrode (12/52) comprises a reflective layer (12, [0055]) and an electrode layer (52) on the reflective layer, the via layer (605) and the first (602) and second (604) protection films defines a contact hole (which later on it was filling up by 613 and 12) penetrating the via layer and the first (602) and second (604) protection films, and at least a portion of the reflective layer (12) is disposed in the contact hole. Moreover, KIM fails to teach at least a portion of the electrode layer is disposed in the contact hole. SATO teaches at least a portion of the electrode layer (162a, FIG. 1, ¶ [0133]) is disposed in the contact hole. It would have been for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of miniaturized the foot print of manufacturing the semiconductor device as taught by SATO, [0010]. Finally, KIM fails to teach Finally, KIM fails to teach a wherein a length of the at least one light-emitting element in the first direction is in a range of about 4 µm to about 7 µm, and an aspect ratio of the at least one light-emitting element is in a range of about 1.2 to about 100. DO teaches wherein a length of the at least one light-emitting element in the first direction is in a range of about 4 µm to about 7 µm, and an aspect ratio of the at least one light-emitting element is in a range of about 1.2 to about 100 ¶ [0076]. It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of ultilizing the small nano-scale LED devices as taught by DO, [0076]. Finally, KIM/SATO/DO fails to teach a light blocking layer below the first active layer and separated from the first active layer by a buffer layer, and the light blocking layer overlaps a portion of the first voltage line in a plan view. `929 teaches a light blocking layer (172, FIG. 7, ¶ [0040]) below the first active layer (224) and separated from the first active layer by a buffer layer (165), and the light blocking layer (712) overlaps a portion of the first voltage line (223, note that it is the SAME DRAIN electrode as discloses in KIM, FIG. 18 as 614) in a plan view (by looking down from the top). It would have been for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of improving visibility and response speed as taught by `929 [0005]. Re claim 17, in the combination, KIM, FIG. 17 teaches the display device of claim 15, wherein each of the first electrode (613) and the second electrode (614) has a shape extending on the base layer in a second direction (vertical) different from the first direction. PNG media_image3.png 527 1065 media_image3.png Greyscale Re claim 18, in the combination, `929 teaches the display device of claim 17 a first contact electrode (131/132, [0042]) in directly contact with each of the first electrode ([FE], FIG. 7 [as shown above]) and one end portion of the at least one light-emitting element (LEA) (133); and a second contact electrode in contact with the second electrode (233) and the other end portion of the at least one light-emitting element (LEA) [OEofLED]. It would have been for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of improving visibility and response speed as taught by `929 [0005]. Re claim 20, in the combination, KIM, FIG. 17 [as shown above] teaches the display device of claim 17, wherein the first conductivity type semiconductor (p-type layer 34), the second active material layer (35), and the second conductivity type semiconductor (n-type layer 33) are disposed in a direction parallel to an upper surface of the base layer (5). Re claim 21, in the combination, SATO, FIG. 1 teaches the display device of claim 1, wherein the reflective layer (162a, [0151]) and the electrode layer (162b, [0133]) are coextensive (planarize) in a plan view. Re claim 22, in the combination, DO teaches he display device of claim 1, wherein the light-emitting element is an inorganic light emitting diode and has a cylindrical shape (20, FIG. 5, [0073]). Re claim 23, in the combination, DO teaches the display device of claim 1, wherein the light-emitting element is comprised of a semiconductor crystal (n/p-type semiconductor crystal, [0005]). Re claim 24, in the combination, KIM, FIG. 17 [as shown above] teaches the display device of claim 1, wherein a side surface of the reflective layer is covered by the electrode layer (52, note that transparent electrode is having some level of reflective in there wherein it is redirected the light, [0093]). Response to Arguments Applicant's arguments with respect to claims 1 and 15 on the remarks filed on 04/22/2026 have been considered but they are not persuasive. Please see the detail of rejection as listed above. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONY TRAN whose telephone number is (571)270-1749. The examiner can normally be reached Monday-Friday, 8AM-5PM, EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TONY TRAN/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Show 14 earlier events
Aug 27, 2025
Response after Non-Final Action
Sep 11, 2025
Non-Final Rejection mailed — §103
Dec 11, 2025
Response Filed
Jan 22, 2026
Final Rejection mailed — §103
Mar 20, 2026
Response after Non-Final Action
Apr 22, 2026
Request for Continued Examination
Apr 28, 2026
Response after Non-Final Action
Jul 06, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

7-8
Expected OA Rounds
70%
Grant Probability
99%
With Interview (+33.8%)
2y 9m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 863 resolved cases by this examiner. Grant probability derived from career allowance rate.

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