DETAILED ACTION
Table of Contents
I. Notice of Pre-AIA or AIA Status 3
II. Continued Examination Under 37 CFR 1.114 3
III. Claim Rejections - 35 USC § 112 3
A. Claim 17 is rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. 3
B. Claims 21, 22, 24 and 26 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. 4
IV. Claim Rejections - 35 USC § 103 5
A. Claims 1-3, 8, 30, 36, 38-41, and 15-17, and 21, 22, 24, 26 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0148153 (“Cheng”) in view of US 2002/0042202 (“Fujimoto”), US 2007/0018331 (“Chen”), US 2022/0068633 (“Shin”), and US 2021/0057335 (“Yang-335”). 6
B. Claims 19, 20, 35 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Fujimoto, Chen, Shin, and Yang-335, as applied to claim 1 above, and further in view of US 2014/0367857 (“Yang-857”). 26
V. Response to Arguments 28
Conclusion 29
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I. Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant’s submission filed on 01/09/2026 has been entered.
III. Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
A. Claim 17 is rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement.
The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor at the time the application was filed, had possession of the claimed invention.
Taking Fig. 6F of the Instant Application as an example of the elected species, the features of claim 17, as currently amended, based on the limitations in claim 15, are shown as follows:
Claim 17 reads,
17. (Currently Amended) The semiconductor structure of claim 15, further comprising:
[1] a third barrier layer [?] between the first metal structure 240a and a first oxide layer [?],
[2] wherein the first oxide layer [?] resides above the second carbon-based layer 262b.
Claim 15 requires (1) the first barrier layer 600 to be on sidewalls of the second metal structure 246a, (2) the second barrier layer 600 to be on the sidewalls and bottom of the second dummy metal structure 246b, and (3) the second carbon based layer 262b to be on the first dummy metal structure 240b. The first metal structure is required to be below the second metal structure 246a; therefore, the first metal structure must be 240a. The only oxide layer above the second carbon-based layer 262b is the layer denoted by reference character 218. However, the only barrier layer shown is denoted by reference character 600, which is each of the first and second barrier layers. Therefore, there is no disclosure of “a third barrier layer between the first metal structure 240a and a first oxide layer 218” that is distinct from either of the first and second barrier layers.
As such, claim 17 introduced new matter.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
B. Claims 21, 22, 24 and 26 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 21, as currently amended, recites the following limitations in 7th through 8th to last lines:
wherein a portion of the second oxide layer is between the second carbon-based layer and the second carbon-based layer and prevents contact between the second dummy metal structure and the second carbon-based layer,
It is unclear what Applicant is trying to claim here because the second oxide layer cannot be between the same, “second carbon-based layer”.
Claims 22, 24, and 26 are rejected for including the same indefinite feature by depending from claim 21.
IV. Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A. Claims 1-3, 8, 30, 36, 38-41, and 15-17, and 21, 22, 24, 26 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0148153 (“Cheng”) in view of US 2002/0042202 (“Fujimoto”), US 2007/0018331 (“Chen”), US 2022/0068633 (“Shin”), and US 2021/0057335 (“Yang-335”).
The applied reference, Yang-335, has a common Assignee with the Instant Application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
In addition to including any one of the statements pursuant to 35 U.S.C. 102(b)(2)(A) through (C), (supra), to overcome Yang-335 as prior art available under 35 USC 102(a)(2), it is still applicable as prior art under 35 U.S.C. 102(a)(1) that cannot be excepted under 35 U.S.C. 102(b)(2)(C). In this instance, Applicant may rely on the exception under 35 U.S.C. 102(b)(1)(A) to overcome this rejection under 35 U.S.C. 102(a)(1) by a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application, and is therefore not prior art under 35 U.S.C. 102(a)(1). Alternatively, applicant may rely on the exception under 35 U.S.C. 102(b)(1)(B) by providing evidence of a prior public disclosure via an affidavit or declaration under 37 CFR 1.130(b).
Turning now to the rejection …
Claim 1 reads,
1. (Currently Amended) A semiconductor structure, comprising:
[1] a first oxide layer;
[2] a second oxide layer above the first oxide layer;
[3a] a first metal structure in the first oxide layer,
[3b] wherein the first metal structure is a gate interconnect in contact with a gate contact, and
[3c] the gate contact is in contact with a gate that is associated with a first source or drain,
[3d] wherein the gate contact fully covers a top surface of the gate in a first dimension, and
[3e] wherein the gate contact and the gate have substantially a same length in the first dimension;
[4a] a first dummy metal structure in the first oxide layer,
[4b] wherein a bottom surface of the first dummy metal structure is in contact with a third oxide layer below the first oxide layer;
[5] a first carbon-based layer directly on a top surface of the first metal structure; and
[6] a second metal structure in the second oxide layer,
[7a] wherein the second metal structure has a first barrier layer on sidewalls of the second metal structure and
[7b] the first barrier layer is absent from a bottom surface of the second metal structure, and
[8] wherein the bottom surface of the second metal structure is in contact with the first carbon-based layer;
[9a] a second dummy metal structure in the second oxide layer,
[9b] wherein the second dummy metal structure has a height that is less than a height of the second metal structure,
[10] wherein a portion of the second oxide layer is between the second dummy metal structure and the first dummy metal structure and prevents contact between the second dummy metal structure and the first dummy metal structure, and
[11] wherein the second dummy metal structure has a second barrier layer on sidewalls of the second dummy metal structure and on a bottom surface of the second dummy metal structure; and
[12a] a second carbon-based layer directly on a top surface of the first dummy metal structure,
[12b] wherein the portion of the second oxide layer is also between the second dummy metal structure and the first dummy metal structure,
[12c] wherein the second carbon-based layer is separate from the first carbon-based layer, and
[12d] wherein a thickness of the second carbon-based layer is greater than a thickness of the first carbon-based layer.
With regard to claim 1, Cheng discloses, generally in Fig. 1H,
1. (Currently Amended) A semiconductor structure, comprising:
[1] a first oxide layer 130 [¶ 40];
[2] a second oxide layer 132 [¶ 40] above the first oxide layer 130;
[3a] a first metal structure 142 [¶ 41] in the first oxide layer 130 [¶ 40],
[3b] wherein the first metal structure 142 is a gate interconnect in contact with a gate contact 112 [¶ 38], and
[3c] the gate contact 112 is in contact with a gate 22 [¶ 38] that is associated with a first source or drain 28 [¶ 41]
[3d]-[3e] … [not taught] … ;
[4a]-[4b] … [not taught] …
[5] … [not taught] …
[6] a second metal structure 152 [¶ 41] in the second oxide layer 132 [¶ 40],
[7a] wherein the second metal structure 152 has a first barrier layer [not shown but like 72 (¶ 42, infra)] on sidewalls of the second metal structure 152 [see explanation below] and
[7b] … [not taught] …
[8]-[12d] … [not taught] …
With regard to feature [7a] of claim 1, Cheng does not show the barrier layer on the sidewalls of the metal line 152 but states that one may be present:
In some implementations, via contacts 140-144 and/or conductive lines 150-154 includes similar materials and/or similar layers to contacts 110-114. For example, in some implementations, via contacts 140-144 and/or conductive lines 150-154 include a contact barrier layer, such as contact barrier layer 72, and a contact bulk layer, such as contact bulk layer 100, where the contact barrier layer is disposed on nitridized surfaces of the MLI feature.
(Cheng: ¶ 42; emphasis added)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include form the metal line 152 like 110-114 having the barrier layer 72 and bulk fill 100 because Cheng suggests doing this (id.).
This is all of the features of claim 1 disclosed in Cheng.
With regard to features [3d]-[3e] of claim 1,
[3d] wherein the gate contact fully covers a top surface of the gate in a first dimension, and
[3e] wherein the gate contact and the gate have substantially a same length in the first dimension;
Cheng does not teach the limitations recited in features [3d]-[3e] of claim 1.
Fujimoto, like Cheng, teaches a transistor having a contact holes 407c, 407d overlying the gate electrodes 11c, 11d that are subsequently filled with doped polysilicon plugs 18 (not shown in Fig. 7(c)) (Fujimoto: Figs. 7(a)-7(c); ¶¶ 40, 135-136). Fujimoto further states,
[0140] According to the contact-hole forming method of the fourth embodiment, the protective films are formed on the side walls of the gate electrodes 11c and 11d in the top surfaces of which the contact holes 407 are formed and the first and second contact holes are then formed at the same time. This-can also provide the gate electrodes 11c and 11d with an alignment margin by the protective films on the side walls. The embodiment can therefore form contact holes which do not have an alignment margin with respect to the gate electrodes 11 or can form contact holes whose diameters are approximately equal to the gate length. Accordingly, the embodiment can easily cope with the future demand for further miniaturization of semiconductor devices.
(Fujimoto: ¶ 140; emphasis added)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the contact holes to the gate electrode 22 and therefore the gate contact 112 of Cheng to have the same diameter as the “length in the first dimension”, because Fujimoto teaches that this configuration is suitable for the gate electrode and gate contact.
Moreover, it has been held that the configurational differences amount to a matter of design choice “absent persuasive evidence that the particular configuration …[is]… significant” In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.) Here the is no discussion in the Instant Application as to the significance of the relative dimensions of the bottom surface of the gate contact and the top surface of the gate electrode and, consequently, no evidence as to the significance of the relative dimensions.
With regard to features [4a]-[4b], [9a]-[9b], [10], and [11] of claim 1,
[4a] a first dummy metal structure in the first oxide layer,
[4b] wherein a bottom surface of the first dummy metal structure is in contact with a third oxide layer below the first oxide layer;
[9a] a second dummy metal structure in the second oxide layer,
[9b] wherein the second dummy metal structure has a height that is less than a height of the second metal structure,
[10] wherein a portion of the second oxide layer is between the second dummy metal structure and the first dummy metal structure and prevents contact between the second dummy metal structure and the first dummy metal structure, and
[11] wherein the second dummy metal structure has a second barrier layer on sidewalls of the second dummy metal structure and on a bottom surface of the second dummy metal structure; and
Cheng does not teach a dummy structure and does not therefore teach features [4a]-[4b], [9a]-[9b], [10], and [11].
Chen, like Cheng, teaches a semiconductor device 20 including an integrated circuit 22 including gate electrode (shown but not labeled) and a multilayered metallization, generally including active interconnect, i.e. “conductors, vias, and/or wiring 44” (Chen: ¶ 18) formed over and connected to the integrated circuit 22 including to the gate electrode (Chen: Fig. 2; ¶¶ 16-18). Chen further teaches that the multilayered metallization includes dummy patterns 34 in the dielectric layer of each metal level that is formed simultaneously with the interconnect 44, thereby beneficially avoiding additional steps:
Preferably, the seal ring structure 30 and the dummy structures 34, 40 are formed simultaneously with the formation of other conductors, vias, and/or wiring 44 on that level. In such case, no additional steps for forming the dummy structures 34, 40 and seal ring structure 30 need to be added. Instead, the masks for patterning the conductors, vias, and/or wiring 44 may be modified during a layout stage, for example.
(Chen: ¶ 18; emphasis added)
In addition, Chen teaches the benefit of the dummy metal patterns 34 to add mechanical strength to the low-k dielectric layers in which the interconnect 44 is formed by dispersing said dummy metal patterns 34 adjacent to the active interconnect 44 in each of the metal levels (Chen: ¶¶ 3, 8, 9, 18, 39). The oxide dielectric layers, e.g. 130 and 132, in Cheng include low-k oxides (Cheng: ¶ 40) and, consequently, would benefit from the dummy metal structures taught in Chen.
Among the configurations of dummy metal structures 34 in each of the dielectric layers 22 in Fig. 2 of Chen (annotated and reproduced below) are those formed in or extending through the low-k dielectric layer to have a bottom surface contacting only the underlying dielectric layer—as required by features [4a]-[4b]. Two annotated versions of Fig. 2 of Chen showing how the claimed first and second dummy metal structures and the first through third oxide layers (i.e. dielectric layers), configured as required in features [4a], [4b], and [10] are shown below.
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It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include a first dummy metal structure 34 in the first oxide layer 130 of Cheng—as required by feature [4a]—configured, e.g., as shown in Fig. 2 of Chen (supra), i.e. having “a bottom surface of the first dummy metal structure 34 [of Chen] … in contact with only the third [i.e. underlying] oxide layer 32 [of Cheng]”—as required by feature [4b]—and to include a second dummy metal structure in the second oxide layer above and separated from the first dummy metal structure by the second oxide layer—as required by feature [10] of claim 1—because Chen teaches that this configuration is suitable for increasing the strength of the low-k oxide dielectric material of Cheng in which the active interconnect is formed (Chen: ¶¶ 3, 8, 9, 18, 39). As such, Chen may be seen as an improvement to Cheng in this aspect. (See MPEP 2143.)
Because (1) the second dummy metal structure 34 of Chen does not extend through the thickness of the second dielectric layer and (2) the second metal layer 152 of Cheng does extend all of the way through the second oxide layer 132, “the second dummy metal structure 34 [of Chen used in Cheng’s second oxide layer 132] has a height that is less than a height of the second metal structure 152 [of Cheng]—as required by features [9a]-[9b] of claim 1.
Because (1) Chen teaches that the active interconnect 44 and dummy metal structures 34 are formed simultaneously (Chen: ¶ 18, quoted above) and (2) Cheng teaches that the second metal layer includes a barrier layer 72 and bulk fill 100 (Cheng: ¶ 42, quoted above), including the dummy metal structures of Chen, simultaneously formed with the metallization process of Cheng would result in the second dummy metal structure also including a barrier layer 72 on the sidewalls and bottom surface of the bulk fill 100, as shown in Cheng—as required by feature [11].
This is all of the limitations of features [4a]-[4b], [9a]-[9b], [10], and [11].
With regard to features [5], [8], and [12a]-[12d] of claim 1,
[5] a first carbon-based layer directly on a top surface of the first metal structure; and
[8] wherein the bottom surface of the second metal structure is in contact with the first carbon-based layer;
[12a] a second carbon-based layer directly on a top surface of the first dummy metal structure,
[12b] wherein the portion of the second oxide layer is also between the second dummy metal structure and the first dummy metal structure,
[12c] wherein the second carbon-based layer is separate from the first carbon-based layer, and
[12d] wherein a thickness of the second carbon-based layer [i.e. on the first dummy metal structure] is greater than a thickness of the first carbon-based layer [i.e. on the first metal structure].
Cheng does not teach dummy metal structures or carbon-based layers on the metal structures, as required by features [5], [8], and [12a]-[12d].
Shin, like Cheng, teaches a multi-level interconnect including lower 210 and upper 280 metal structures in lower 220 and upper 260/270 dielectric layers, respectively, separated by a “second insulating layer 250”, which functions as an etch stop layer, as shown in Figs. 20 of Shin (Shin: ¶¶ 113, 120).
Shin further teaches selectively depositing a carbon-based layer 240 or 231/240 including an organic “surface pretreatment layer 231” (¶ 87) followed by a graphene layer 240 directly on the top surfaces of each of the lower metal patterns 210 (Shin: Fig. 23; ¶¶ 87-88, 93-100), thereby resulting in the carbon-based layer 240 or 231/240 being at the contact interface between the lower metal pattern 210 and overlaying metal pattern 280—as required by features [5] and [8]. As shown in Figs. 11-15, 18, 20, and 23, the carbon-based layer 240 or 231/240 is formed before the dielectric layers 250, 260, 270 are formed thereover (Shin: Fig. 23; ¶¶ 106, 111, 119, 120), resulting in said carbon-based layer 240 or 231/240 being within the etch stop layer 250—as further required by claim 2 (infra)—as well as, separate carbon-based layers, on the top surfaces of each of the lower metal patterns 210, including those to which no overlying contact metal is made, such as to a dummy metal layer, e.g. the dummy metal layer 34 of Chen used in Cheng (supra). Because the dummy metal structures 34 and the active metal structures 44 of Chen used in Cheng are formed simultaneously, as taught in Chen (Chen: ¶ 18, quoted above), the carbon-based layer 240 or 231/240 of Shin, used in Cheng, will also be formed on all of the dummy metal structures—as required by features [12a] and [12c].
Shin states that the benefit is that graphene reduces electrical resistance and increases electromigration resistance, stating,
[0114] In addition, as illustrated in FIG. 20, only a portion of the carbon layer 240 having an sp2 bonding structure and formed on some of the first metal layers 210 may be removed. The carbon layer 240 having an sp2 bonding structure and remaining on the first metal layer 210 may act as a capping layer in an interconnect structure. The capping layer described above may reduce electrical resistance of the first metal layer 210, thus increasing electromigration resistance.
(Shin: ¶ 114; emphasis added)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the carbon based layer 231/240 including the “carbon layer 240 having the sp2 bonding structure” (id.) which includes graphene (Shin: e.g. ¶ 94) on the upper surfaces of the metal structures, e.g. 140, 142, and 144, of Cheng, including the first metal structure 142 of Cheng, in order to reduce electrical resistance and increase electromigration resistance, as taught by Shin (id.). As such, Shin may be seen as an improvement to Cheng in this aspect. (See MPEP 2143.)
and because Cheng includes a barrier layer 72 surrounding the bulk metal fill 100, the deposition of the graphene layer 228 of Yang-335 at the surfaces of each of the vias 140, 142, 144 of Cheng would also result graphene simultaneously being deposited on the dummy metal patterns 34 of Chen formed in the first oxide layer 130 of Cheng.
Further with regard to feature [12d] of claim 1, Shin also teaches that the graphene layer 240 is formed thicker over metal surfaces [right metal structure 210 in Fig. 23 of Shin) to which no overlying metal is physically connected than at said interface between lower 210 and upper 280 metal structures (Shin: Fig. 23: ¶ 120).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the “thickness of the second carbon-based layer [of Shin on the first dummy metal structure of Chen used in Cheng] is greater than a thickness of the first carbon-based layer [of Shin on the first metal structure 142 of Cheng]” because Shin teaches that maintaining only a portion of the thickness of the graphene layer 240 as a “capping layer (Shin: ¶¶ 114, 120), results in reduced resistance and improved electromigration resistance (id.).
Further with regard to feature [12b] of claim 1, Cheng modified according to include the first and second dummy metal structures of Chen in Cheng will result in “the portion of the second oxide layer is also between the second dummy metal structure and the first dummy metal structure”, as shown in the annotated figures of Chen (supra).
This is all of the limitations of features [5], [8], and [12a]-[12d].
With regard to feature [7b] of claim 1,
[7b] the first barrier layer is absent from a bottom surface of the second metal structure, and
Cheng does not teach that the first barrier layer 72 is absent from a bottom surface of the second metal structure 152, as required by feature [7b].
Yang-335, like Cheng and Shin, teaches a multi-level interconnect including lower 216 and upper 234 metal structures in lower 210 and upper 220 dielectric layers, respectively separated by an etch stop layer 218 (Yang-335: Fig. 5B; ¶¶ 21-24, 29). Also like Cheng, Yang-335 deposits a diffusion barrier layer 232 before the metal fill 234 in order to prevent diffusion of the metal fill 234 into the surrounding dielectric 220.
Like Shin, Yang-335 further teaches selectively forming a graphene 228 layer on the top surface of the lower metal layer 216 (Yang-335: Figs. 2, 3B; ¶ 26). Yang-335 states that the benefit is that “[t]he graphene layer of the present disclosure not only serves as a blocking layer for the barrier layer but also exhibit low contact resistance.” (Yang-335: ¶ 13). Yang-335 further states,
[0042] The MEOL contact structures and BEOL interconnect structures disclosed herein provide several benefits. In some embodiments, by forming a graphene layer either directly on a conductive metal surface or on a catalytic metal layer to block formation of barrier materials, the barrier layer can be selectively formed over sidewalls of via openings and trenches, while the graphene layer remains free of any barrier layer. Compared to the barrier layer, the superior conductivity of the graphene layer at the contact interface can greatly reduce contact resistance, decrease RC delay and improve device performance.
(Yang-335: ¶ 42; emphasis added)
Thus, Yang-335 also teaches that the precursors used to deposit the barrier layer 232 selectively deposit on the sidewalls of the openings 222/224 and not on the graphene layer 228 (id.) as shown in Figs. 4A and 4B (Yang-335: ¶ 28). The barrier layer 228 may be TiN deposited by ALD (Yang-335: ¶ 28), just as in Cheng (¶¶ 30-32).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the barrier layer 72 of Cheng using the graphene layer 240 or 231/240 of Shin used on the top surface of the metal pattern 142 of Cheng to block the barrier layer deposition on the graphene layer/metal pattern and thereby “greatly reduce contact resistance, decrease RC delay and improve device performance”, as taught in Yang-335 (id.). Therefore, Yang-335 may be seen as an improvement to both Cheng and Shin, in this aspect. (See MPEP 2143.)
This is all of the limitations of claim 1.
With regard to claim 2, Cheng modified according to Yang-335 to form the graphene layer across the entire surface of the first metal structure 142 of Cheng, as explained above under feature [5] and [12a] of claim 1, would result in the features of claim 2 as follows:
2. (Currently Amended) The semiconductor structure of claim 1, further comprising:
[1] an etch stop layer 136 [of Cheng (¶ 40)] deposited between the first oxide layer 130 and the second oxide layer 132,
[2] wherein the first carbon-based layer and the second carbon-based layer [each of Yang-335 used in Cheng] reside within the at least one etch stop layer 136 [as explained under features [5], [8], and [12a]-[12d] of claim 1 (supra)].
Claim 3 reads,
3. (Previously Presented) The semiconductor structure of claim 1, wherein the second barrier layer on the bottom surface of the second dummy metal structure contacts the second dummy metal structure and the second oxide layer.
As explained above, because the dummy metal structure and the active metal structures are formed simultaneously, as taught in Chen, and because Cheng includes a barrier layer 72 surrounding the bulk metal fill, the “the second barrier layer 72 on the bottom surface of the second dummy metal structure [34 of Chen used in Cheng] contacts the second dummy metal structure [34 of Chen used in Cheng] and the second oxide layer 132 [of Cheng]”, as required by claim 3.
With regard to claims 8 and 30, Cheng further discloses,
8. (Previously Presented) The semiconductor structure of claim 1, wherein the second metal structure 152 comprises a metallization layer [Cheng; ¶ 41; Fig. 1H].
30. (Previously Presented) The semiconductor structure of claim 1, further comprising:
[1] a third metal structure 100, 114 in the third oxide layer 32 [Cheng: ¶ 41],
[2] wherein the third metal structure 100, 114 is a source contact or a drain contact and is coupled with a second source or drain 28 [Cheng: Fig. 1H].
With regard to claims 36 and 38, Cheng further discloses,
36. (Currently Amended) The semiconductor structure of claim 1, wherein the gate contact 112 extends from a top surface of the third oxide layer 32 through a bottom of the third oxide layer 32 [as shown in Fig. 1H of Cheng].
38. (New) The semiconductor structure of claim 1, wherein the gate contact 112 is within the third oxide layer 32 [as shown in Fig. 1H of Cheng].
With regard to claims 39 and 41, Cheng modified to include the carbon-based layer 240 or 231/240 of Shin, as explained above under claim 1 results in the configuration claimed below, as shown in Fig. 23 of Shin:
39. (New) The semiconductor structure of claim 1,
[1] wherein a bottom surface of the first carbon-based layer 240 [between 210 and 280] resides on a same plane as a bottom surface of the second carbon-based layer 231/240 [on left lower metal pattern 210], and
[2] wherein a top surface of the first carbon-based layer 240 [between 210 and 280] resides below a top surface of the second carbon-based layer 231/240 [on left lower metal pattern 210].
41. (New) The semiconductor structure of claim 2, wherein a top surface of the etch stop layer 136 [of Cheng equal to 250 of Shin] resides above a top surface of the first carbon-based layer 240 [between 210 and 280] [as shown in Fig. 23 of Shin].
With regard to claim 40, Cheng modified according to Shin and Yang-335, as explained under claim 1 would result in the configuration of claim 40, as follows:
40. (New) The semiconductor structure of claim 2, wherein the first barrier layer 72 [of Cheng (not shown (supra)] is in contact with the second metal structure 152 [of Cheng], the second oxide layer 132 [of Cheng], and the etch stop layer 136 [of Cheng].
As explained under claim 1, Cheng does not show, but forms, a barrier layer on the opening in each of the dielectric layers 130, 132 before forming the respective metal fill (supra), thereby yielding the configuration of the barrier layer in claim 40. Because the carbon-based layer 240 is Shin is recessed within the etch stop 250, and consequently within the etch stop layer 136 of Cheng—as explained under feature [12d] of claim 1—the barrier layer 72 of Cheng (not shown) would be in contact with the portion of the etch stop layer 136 over the recessed portion of the carbon-based layer 240 of Shin/Cheng.
Claim 15 reads,
15. (Currently Amended) A semiconductor structure, comprising:
[1a] a first metal structure,
[1b] wherein the first metal structure is a gate interconnect in contact with a gate contact below the first metal structure, and
[1c] the gate contact is in contact with a gate, associated with a first source or drain, that is below the gate contact,
[1d] wherein the gate contact fully covers a top surface of the gate in a first dimension, and
[1e] wherein the gate contact and the gate have substantially a same length in the first dimension;
[2a] a second metal structure above the first metal structure,
[2b] wherein the second metal structure has a first barrier layer on sidewalls of the second metal structure and
[2c] the first barrier layer is absent from a bottom surface of the second metal structure;
[3a] a first carbon-based layer between the first metal structure and the second metal structure,
[3b] wherein the bottom surface of the second metal structure is in contact with the first carbon-based layer;
[4a] a first dummy metal structure adjacent to the first metal structure,
[4b] wherein a bottom surface of the first dummy metal structure is in contact with only an oxide layer that is below the first dummy metal structure and the first metal structure;
[5a] a second dummy metal structure adjacent to the second metal structure,
[5b] wherein the second dummy metal structure has a height that is less than a height of the second metal structure,
[6] wherein the second dummy metal structure is separated from the first dummy metal structure, and
[7] wherein the second dummy metal structure has a second barrier layer on sidewalls of the second dummy metal structure and on a bottom surface of the second dummy metal structure; and
[8a] a second carbon-based layer residing directly on the first dummy metal structure,
[8b] wherein the second carbon-based layer is a distance away from the second dummy metal structure,
[8c] wherein the second carbon-based layer is separate from the first carbon-based layer, and
[8d] wherein a thickness of the second carbon-based layer is greater than a thickness of the first carbon-based layer.
The following features of claim 15 have been addressed under the rejection of claim 1, as follows:
Features [1a]-[1e] of claim 15 have been addressed under features [3a]-[3e] of claim 1.
Features [2a]-[2c] of claim 15 have been addressed under features [6], [7a], and [7b] of claim 1.
Features [3a]-[3b] of claim 15 have been addressed under features [5] and [8] of claim 1.
Features [4a]-[4b] of claim 15 have been addressed under features [4a] and [4b] of claim 1.
Features [5a] and [5b] of claim 15 have been addressed under feature [9a]-[9b] of claim 1.
Feature [6] of claim 15 has been addressed under feature [10] of claim 1.
Features [7] of claim 15 has been addressed under feature [11] of claim 1.
Features [8a]-[8d] of claim 15 have been addressed under features [12a]-[12d] of claim 1.
Further with regard to feature [5a] of claim 15, the second dummy metal layer 34 of Chen used in Cheng would be adjacent to the second metal layer 152 of Cheng because both metal structures are formed separately in the same oxide layer 132 of Cheng, as taught in Chen.
This is all of the limitations of claim 15.
With regard to claim 16, Cheng modified according to Shin further teaches,
16. (Currently Amended) The semiconductor structure of claim 15, wherein the first carbon-based layer [240 or 231/240 of Shin] substantially prevents contact between the first metal structure 142 [of Cheng] and the second metal structure 152 [of Cheng] [as explained under claim feature [8] of claim 1].
Claim 17 reads,
17. (Currently Amended) The semiconductor structure of claim 15, further comprising:
[1] a third barrier layer between the first metal structure and a first oxide layer,
[2] wherein the first oxide layer resides above the second carbon-based layer.
Bearing in mind the rejection under 35 USC 112(a), above, the limitations of claim 17 are taught by the combination of Cheng in view of Chen, Shin, and Yang-335 to every extent that it is disclosed in the Instant Application.
Claim 21 reads,
21. (Currently Amended) A semiconductor structure, comprising:
[1a] a first metal structure in a first oxide layer,
[1b] wherein the first metal structure is a gate interconnect, in contact with a gate contact, and is coupled with a gate that is associated with a first source or drain,
[1c] wherein the gate contact fully covers a top surface of the gate in a first dimension, and
[1c] wherein the gate contact and the gate have substantially a same length in the first dimension;
[2a] a first carbon-based layer directly on a top surface of the first metal structure,
[2b] wherein the first carbon-based layer is in an etch stop layer between the first oxide layer and a second oxide layer,
[2c] the second oxide layer being above the first oxide layer;
[3] a second metal structure in the second oxide layer,
[4a] wherein the second metal structure has a first barrier layer on sidewalls of the second metal structure and
[4b] the first barrier layer is absent from a bottom surface of the second metal structure, and
[5] wherein the bottom surface of the second metal structure is in contact with the first carbon-based layer;
[6a] a first dummy metal structure in the first oxide layer,
[6b] wherein a bottom surface of the first dummy metal structure is in contact with only a third oxide layer below the first oxide layer;
[7a] a second carbon-based layer, in the etch stop layer, directly on the first dummy metal structure,
[7b] wherein the second carbon-based layer is separate from the first carbon-based layer, and
[7c] wherein a thickness of the second carbon-based layer is greater than a thickness of the first carbon-based layer; and
[8] a second dummy metal structure in the second oxide layer,
[9] wherein a portion of the second oxide layer is between the second carbon-based layer and the second carbon-based layer and prevents contact between the second dummy metal structure and the second carbon-based layer, and
[10] wherein the second dummy metal structure has a second barrier layer on sidewalls of the second dummy metal structure and on a bottom surface of the second dummy metal structure.
The following features of claim 21 have been addressed under the rejection of claims 1 and 4, above, as follows:
Features [1a]-[1d] of claim 21 have been addressed under features [1] and [3a]-[3e] of claim 1.
Feature [2a] of claim 21 has been addressed under feature [5] of claim 1.
Feature [2b] of claim 21 has been addressed under claim 2.
Feature [2c] of claim 21 has been addressed under feature [2] of claim 1.
Feature [3], [4a]-[4b], and [5] of claim 21 has been addressed under features [6], [7a]-[7b], and [8] of claim 1, respectively.
Features [6a]-[6b] of claim 21 have been addressed under features [4a]-[4b] of claim 1.
Feature [7a]-[7c] of claim 21 has been addressed under features [12a], [12c], and [12d] of claim 1 and claim 2.
Feature [8] of claim 21 has been addressed under feature [9] of claim 1.
Bearing in mind the rejection under 35 USC 112(b), feature [9] of claim 21 has been addressed under feature [10] and [12b] of claim 1 and claim 2 taken in consideration with feature [7a] of claim 21.
Feature [10] of claim 21 has been addressed under feature [11] of claim 1.
This is all of the limitations of claim 21.
Claim 22 reads,
22. (Currently Amended) The semiconductor structure of claim 21, wherein the first carbon-based layer and the second carbon-based layer reside within the etch stop layer 136.
See discussion under claim 2, above.
Claim 24 reads,
24. (Currently Amended) The semiconductor structure of claim 21, further comprising: wherein the second barrier layer contacts the second dummy metal structure and the second oxide layer.
See discussion under claim 3, above.
With regard to claim 26, Cheng further discloses,
26. (Previously Presented) The semiconductor structure of claim 21, wherein the second metal structure 152 comprises a metallization layer [Cheng: ¶ 41].
B. Claims 19, 20, 35 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Fujimoto, Chen, Shin, and Yang-335, as applied to claim 1 above, and further in view of US 2014/0367857 (“Yang-857”).
Claims 35 and 20 read,
35. (Currently Amended) The semiconductor structure of claim 1, wherein each of the first carbon-based layer and the second carbon-based layer has a depth of at least 1 nanometer (nm).
20. (Currently Amended) The semiconductor structure of claim 15, wherein each of the first carbon-based layer and the second carbon-based layer has a depth that is within a range from approximately 1 nanometer (nm) to approximately 5 nm.
The prior art of Cheng in view of Fujimoto, Chen, Shin, and Yang-335, as explained above, teaches each of the features of claims 1 and 15.
Neither of Shin and Yang-335 gives the thickness of the carbon-based layers.
Yang-857 teaches that the thickness of a graphene layer 115 between lower metal pattern 103 and upper metal pattern 117 is from 1 Å to 50 Å (i.e. 0.1 nm to 5 nm) (Yang-857: ¶ 34, last sentence).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the thickness of the first and second carbon-based layers of Shin used in Cheng to be from 0.1 nm to 5 nm because Shin is merely silent as to the thickness such that one having ordinary skill in the art would use known thicknesses suitable for forming an interface between metal layers in electrical contact, such as the thickness taught in Yang-857.
So done, the claimed thickness or “depth” range for the first and second carbon-based layers overlaps or falls within the range taught in the prior art. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); MPEP 2144.05(I)). In such a situation, Applicant must show that the particular ranges are critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. See In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). (See MPEP 2144.05(III)(A); emphasis added.)
This is all of the limitations of claims 35 and 20.
Claim 19 reads,
19. (Currently Amended) The semiconductor structure of claim 15, further comprising:
[1] an etch stop layer having a thickness within a range from approximately 1 nanometer (nm) to approximately 3 nm,
[2] wherein the first carbon-based layer and the second carbon-based layer reside in the etch stop layer.
Cheng modified to include the dummy metal layers of Chen and the carbon-based layers of Shin formed on both the dummy and active metal structures teaches feature [2] of claim 19, as explained under claim 2, above.
With regard to feature [1] of clam 19, Cheng does not give the thickness of the etch stop layers 34, 134, 136.
Fig. 2f of Yang-857 shows that the thicknesses of the adjacent etch stop layer 105 and the graphene layer 115 are the same. Fig. 3B of Yang-335 shows the same as Yang-857. Shin shows that the carbon based layers are equal to or less than the thickness of the etch stop layer 250 (Shin: Fig. 23).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use the same thickness for the etch stop layers 34, 134, 136 of Cheng as that of the graphene layer because each of Yang-857, Yang-335, and Shin teaches that it is suitable to make the etch stop layer 105 and the graphene layer 115 the same thickness.
As such, the claimed thickness range for the etch stop layer of 1 nm to 3 nm falls within thickness range of the etch stop layer of Yang-857 used in Cheng of 0.1 nm to 5 nm. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); MPEP 2144.05(I)). In such a situation, Applicant must show that the particular ranges are critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. See In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). (See MPEP 2144.05(III)(A); emphasis added.)
This is all of the limitations of claim 19.
V. Response to Arguments
Applicant’s arguments filed 01/09/2026 have been full considered but art moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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Signed,
/ERIK KIELIN/
Primary Examiner, Art Unit 2814