Detailed Action
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-4. 6, 9-10, 12-15, 18-20 and 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 20130277852 A1 hereinafter Chen) and further in view of Hedler et. Al. (US 20080029850 A1 hereinafter Hedler).
Regarding claim 1, Chen teaches in Figs. 18 with associated text a microelectronic assembly, comprising:
a plurality of microelectronic substrates 68-86, comprising at least three microelectronic substrates, direct bonded to form a vertical stack of microelectronic substrates (Fig. 18, [0042]-[0043]);
a conductive pad 24 disposed at a first relative position on a bonding surface (top surface of 26 hard mask 30 is optional [0040] so that the upper surface of for each substrate) on top of each of the plurality of microelectronic substrates (Fig. 18, [0039]); and
a continuous conductive material 64 extending through an interior area of the conductive pad of each of the plurality of microelectronic substrates except one thereof (24 of 86) (Fig. 18, [0044]).
Chen does not specify the conductive pad of each subsequent microelectronic substrate of the vertical stack of microelectronic substrates is offset a distance relative to the conductive pad on the bonding surface of a previously placed microelectronic substrate of the vertical stack of microelectronic substrates.
Hedler teaches in Figs. 6A-6D with associated text a microelectronic assembly similar to that of Chen wherein s conductive pad 602 of each subsequent microelectronic substrate of a vertical stack of microelectronic substrates (first three substrates 601) is offset a distance relative to the conductive pad on the bonding surface of a previously placed microelectronic substrate of the vertical stack of microelectronic substrates (Fig. 6B-6C, [0061]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the conductive pad of each subsequent microelectronic substrate of the vertical stack of microelectronic substrates of Chen to be offset a distance relative to the conductive pad on the bonding surface of a previously placed microelectronic substrate of the vertical stack of microelectronic substrates as taught by Hedler because according to Hedler a misalignment 603 may still be acceptable, since a conductive material may still be able to flow around the misalignment 603 and consequently fill a continuous channel of the through holes 610. A misalignment 603, in line with this embodiment of the present invention, may be acceptable up to 10 percent, 30 percent, or up to 45 percent of an average aperture diameter, the aperture being a cross section of a through hole 610 (Hedler [0061]) so that by allowing misalignment to occur in the procedure for making the microelectronic assembly of Chen expensive alignment equipment and time consuming alignment procedures that would be needed to ensure that the conductive pads were perfectly aligned could be avoided so that throughput could be improved and cost could be reduced. It would have been obvious to one of ordinary skill in the art, in view of the teachings of Chen and Hedler, since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods to with no change in their respective functions, and the combination would have yielded nothing more than predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S., 82 USPQ2d 1385 (2007).
Regarding claim 12, Chen teaches in Fig. 18 with associated text a microelectronic assembly, comprising:
a plurality of microelectronic substrates 68-86, comprising at least three microelectronic substrates (20a-20d), stacked to form a vertical stack of microelectronic substrates (Fig. 18, [0042]-[0043]);
a conductive pad 24 disposed on a bonding surface on top of (top surface of 26 hard mask 30 is optional [0040] so that the upper surface of for each substrate) of each of the plurality of microelectronic substrates (Fig. 18, [0039]); and
a continuous conductive material (19 and 62) extending through an interior area of the conductive pad of each of the plurality of microelectronic substrates except one thereof (24 of 86) (Fig. 18, [0044]).
Chen does not specify the conductive pad of each subsequent microelectronic substrate of the vertical stack of microelectronic substrates is offset a distance relative to the conductive pad on the bonding surface of a previously placed microelectronic substrate of the vertical stack of microelectronic substrates.
Hedler teaches in Figs. 6A-6D with associated text a microelectronic assembly similar to that of Chen wherein s conductive pad 602 of each subsequent microelectronic substrate of a vertical stack of microelectronic substrates (first three substrates 601) is offset a distance relative to the conductive pad on the bonding surface of a previously placed microelectronic substrate of the vertical stack of microelectronic substrates (Fig. 6B-6C, [0061]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the conductive pad of each subsequent microelectronic substrate of the vertical stack of microelectronic substrates of Chen to be offset a distance relative to the conductive pad on the bonding surface of a previously placed microelectronic substrate of the vertical stack of microelectronic substrates as taught by Hedler because according to Hedler a misalignment 603 may still be acceptable, since a conductive material may still be able to flow around the misalignment 603 and consequently fill a continuous channel of the through holes 610. A misalignment 603, in line with this embodiment of the present invention, may be acceptable up to 10 percent, 30 percent, or up to 45 percent of an average aperture diameter, the aperture being a cross section of a through hole 610 (Hedler [0061]) so that by allowing misalignment to occur in the procedure for making the microelectronic assembly of Chen expensive alignment equipment and time consuming alignment procedures that would be needed to ensure that the conductive pads were perfectly aligned could be avoided so that throughput could be improved and cost could be reduced. It would have been obvious to one of ordinary skill in the art, in view of the teachings of Chen and Hedler, since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods to with no change in their respective functions, and the combination would have yielded nothing more than predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S., 82 USPQ2d 1385 (2007).
Regarding claim 19, Chen teaches in Figs. 18 with associated text a microelectronic assembly, comprising:
a plurality of microelectronic substrates 68-86, comprising at least three microelectronic substrates, stacked to form a vertical stack of microelectronic substrates (Fig. 18, [0042]-[0043]);
a conductive pad 24 disposed at a first relative position on a bonding surface of each of the plurality of microelectronic substrates (Fig. 18, [0039]);
a cavity 108 extending through an interior area of the conductive pad of each of the plurality of microelectronic substrates except one thereof (24 of 86) (Fig. 18, [0053]) the cavities of the different microelectronic substrates at least partially aligned (each cavity overlaps (Fig. 18) and so is interpreted to be partially aligned); and
a conductive material 64 filled within the cavity to form a continuous through silicon via (TSV) common to each of the microelectronic substrates of the vertical stack of microelectronic substrates, the TSV comprising an interlayer connection electrically coupling the conductive pad on the bonding surface of each of the plurality of microelectronic substrates (Fig. 18, [0053]).
Chen does not specify each of the microelectronic substrates of the vertical stack of microelectronic substrates being misaligned with respect to at least one other microelectronic substrate of the vertical stack of microelectronic substrates (Fig. 6A-6D, [0059] and [0061]).
Helder teaches in Figs. 6A-6K with associated text each of a plurality of microelectronic substrates 601 of a vertical stack of microelectronic substrates being misaligned with respect to at least one other microelectronic substrate of the vertical stack of microelectronic substrates (Fig. 6A-6D, [0059] and [0061]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make each of the microelectronic substrates of the vertical stack of microelectronic substrates of Chen to be misaligned with respect to at least one other microelectronic substrate of the vertical stack of microelectronic substrates as taught by Hedler because according to Hedler a misalignment 603 may still be acceptable, since a conductive material may still be able to flow around the misalignment 603 and consequently fill a continuous channel of the through holes 610. A misalignment 603, in line with this embodiment of the present invention, may be acceptable up to 10 percent, 30 percent, or up to 45 percent of an average aperture diameter, the aperture being a cross section of a through hole 610 (Hedler [0061]) so that by allowing misalignment to occur in the procedure for making the microelectronic assembly of Chen expensive alignment equipment and time consuming alignment procedures that would be needed to ensure that the conductive pads were perfectly aligned could be avoided so that throughput could be improved and cost could be reduced. It would have been obvious to one of ordinary skill in the art, in view of the teachings of Chen and Hedler, since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods to with no change in their respective functions, and the combination would have yielded nothing more than predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S., 82 USPQ2d 1385 (2007).
Regarding claims 2 and 13, Chen teaches at least a portion of the conductive pad on the bonding surface of each of the plurality of microelectronic substrates is aligned with at least a portion of the conductive pad on the bonding surface of any other one of the plurality of microelectronic substrates (the area enclosed by the overlap so that they are at least partially aligned Fig. 18).
Regarding claims 3 and 14, Chen teaches the continuous conductive material forms an interlayer connection electrically coupling the conductive pad on the bonding surface of each of the plurality of microelectronic substrates (Fig. 18).
Regarding claim 4, Chen teaches an exterior perimeter of the conductive pad on the bonding surface of each of the plurality of microelectronic substrates has a first size and shape and wherein the interior area of the conductive pad on the bonding surface of each of the plurality of microelectronic substrates or each of the plurality of microelectronic substrates except one thereof has a second size and shape (the claim does not necessarily require the size and shapes to be different Fig. 18).
Regarding claims 6 and 18, Chen teaches the second shape comprises a polygon, a geometric shape, an eccentric shape, an irregular shape, or a multi-faceted shape (the shape is necessarily either geometric or irregular).
Regarding claim 9, Chen in view of Hedler teaches the offset of each subsequent microelectronic substrate is in a first offset direction relative to the previously placed microelectronic substrate (each are offset backward and forwards in a horizontal direction Hedler Fig. 6B).
Regarding claim 10, Chen in view of Hedler teaches the microelectronic assembly of claim 1.
Chen does not specify the offset distance is larger than an average die placement error of die placement tools used to stack the plurality of microelectronic substrates to form the vertical stack however Hedler does teach the offset distance is significant as compared to the size of an opening in the conductive pad [0062] so that the offset distance would be larger than an average die placement error of die placement tools that could be used to stack the plurality of microelectronic substrates to form the vertical stack.
Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985)
Because Hedler teaches a structure that is the same as or obvious to the claimed offset distance, the process limitations “an average die placement error of die placement tools used to stack the plurality of microelectronic substrates to form the vertical stack” in claim 10 as any die placement error would only arise in dependence of the process of stacking, and so would not carry weight in a claim drawn to structure. In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985), MPEP 2113
Regarding claim 15, Chen teaches the continuous conductive material comprises a common TSV that is adjacent to a portion of the conductive pad on the bonding surface of each of the plurality of microelectronic substrates (Fig. 6K).
Regarding claim 20, Chen in view of Hedler teaches the conductive pad on the bonding surface of each of the plurality of microelectronic substrates is misaligned with respect to at least one other conductive pad on the bonding surface of another microelectronic substrate of the vertical stack of microelectronic substrates (Hedler Fig. 6B, [0061]).
Regarding claim 22, Chen in view of Hedler teaches the microelectronic assembly of claim 19, a size of the interior area of the conductive pad on the bonding surface of each of the plurality of microelectronic substrates is uniform (Chen Fig. 18).
Regarding claim 23, Chen teaches the size of the interior area of the conductive pad has a predetermined size (determined by shape of mask 100 Fig. 16 and 18 [0051]).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Hedler as applied to claim 1 and further in view of Tsai et. Al. (US 20150348917 A1 hereinafter Tsai).
Regarding claim 5, Chen in view of Hedler teaches the microelectronic assembly of claim 4.
Cheng does not specify the conductive pad on the bonding surface of each of the plurality of microelectronic substrates or each of the plurality of microelectronic substrates except one thereof has an "O," a "C," a "D," a "G," or a "U" shape however Chen does teach such conductive pads having an opening [0039].
Tsai discloses in Figs. 1E with associated text a conductive pad 108a-108b similar to the conductive pad on the bonding surface of each of the plurality of microelectronic substrates or each of the plurality of microelectronic substrates except one microelectronic substrate of Chen in view of Hedler has an "O" shape (Fig. 1E).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the conductive pad on the bonding surface of each of the plurality of microelectronic substrates or each of the plurality of microelectronic substrates except one microelectronic substrate of Chen in view of Hedler have an "O," shape as taught by Tsai because according to Tsai such a shape is suitable for such a contact pad [0048], furthermore it would have been an obvious matter of design choice to use an O shape since such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Hedler as applied to claim 1 and further in view of Enquist et. Al. (US 20070037379 A1 hereinafter Enquist).
Regarding claim 11, Chen in view of Hedler teaches the microelectronic assembly of claim 1.
Chen does not specify the at least three microelectronic substrates are direct bonded using an ambient temperature direct bonding technique without adhesives.
Enquist discloses in Figs. 2A-2F with associated text microelectronic substrates direct bonded using an ambient temperature direct bonding technique without adhesives [0069].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the microelectronic substrates of Chen in view of Hedler direct bonded using an ambient temperature direct bonding technique without adhesives as taught by Enquist because according to Enquist the bonding surface 20 of die 14 is bonded to bonding surface 13 of substrate 10, This may be accomplished by a number of methods, but is preferably bonded at room temperature using a bonding method as described in application Ser. No. 09/505,283, where bonds of a strength in the range of 500-2000 mJ/m.sup.2 so that the method of Enquist would be suitable for bonding the substrates of Chen in view of Hedler
Allowable Subject Matter
Claims 24-29 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
After completing a thorough search of dependent claims 24 and 26, the prior art of record, alone or in combination does not disclose, teach or fairly suggest a microelectronic assembly, comprising: a conductive pad disposed on a bonding surface disposed on top of each of the plurality of microelectronic substrates, the conductive pad on the bonding surface of each subsequent microelectronic substrate of the plurality of microelectronic substrates offset a distance relative to the conductive pad on the bonding surface of a previously placed microelectronic substrate of the plurality of microelectronic substrates; and a continuous conductive material extending through an interior area of the conductive pad of each of the plurality of microelectronic substrates except one thereof, wherein a first width of a first portion of the continuous conductive material extending through the interior area of the conductive pad of a first microelectronic substrate of the plurality of microelectronic substrates is larger than a second width of a second portion of the continuous conductive material extending through the interior area of the conductive pad of a second microelectronic substrate of the plurality of microelectronic substrates in combination with the rest of the limitations of the claim.
After completing a thorough search of dependent claim 28, the prior art of record, alone or in combination does not disclose, teach or fairly suggest a microelectronic assembly, comprising: a plurality of microelectronic substrates each of the microelectronic substrates of the vertical stack of microelectronic substrates being misaligned with respect to at least one other microelectronic substrate of the vertical stack of microelectronic substrates; a conductive pad disposed at a first relative position on a bonding surface disposed on top of each of the plurality of microelectronic substrates; and a conductive material filled within the cavity to form a continuous through silicon via (TSV) common to each of the microelectronic substrates of the vertical stack of microelectronic substrates, the TSV comprising an interlayer connection electrically coupling the conductive pad on the bonding surface of each of the plurality of microelectronic substrates, wherein a first width of a first portion of the cavity extending through the interior area of the conductive pad of a first microelectronic substrate of the plurality of microelectronic substrates is larger than a second width of a second portion of the cavity extending through the interior area of the conductive pad of a second microelectronic substrate of the plurality of microelectronic substrates
in combination with the rest of the limitations of the claim.
Claims 25, 27 and 29 are also allowed being dependent on allowable claims 24, 26 and 28.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 and 22-23 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/AARON J GRAY/Examiner, Art Unit 2897