DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on August 29, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1, 5, 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Ishizaka et al (U.S. 2010/0248473), Fukushima (U.S. 2012/0193696), and Basker et al (U.S. 2016/0099246).
Regarding claim 1. Ishizaka et al discloses a processing system (FIG. 7, item 700) comprising:
a first transfer chamber (FIG. 7, item 705);
a plurality of process chambers (FIG. 7, items 704B-C, 706A-D) coupled to the first transfer chamber (FIG. 7, item 705); and
a controller (FIG. 7, item 710;[0096]) having a central processing unit (CPU)([0096] i.e. computer) and memory ([0097], i.e. The controller 710 can include a microprocessor, memory)
Ishizaka et al further discloses computer instruction code therein ([0098]), the computer instruction code when implemented by the cpu ([0096]-[0098]) causes a process ([0099]) to be performed without a vacuum break ([0091], i.e. FIG. 7 is a schematic diagram of a vacuum processing tool for performing integrated processing according to embodiments of the invention. The vacuum processing tool 700 contains a substrate (wafer) transfer system 701 that includes cassette modules 701A and 701B, and a substrate alignment module 701C. Load-lock chambers 702A and 702B are coupled to the substrate transfer system 701) in the processing system (FIG. 7, item 700)
forming a trench (FIG. 4A, item 450) in a dielectric material (FIG. 4A, item 404) to expose a region ([0064]; FIG. 4A); performing a pre-clean process ([0068]) on the region (FIG. 4A, item 403) and the dielectric material (FIG. 4A, item 404);
filling the trench (FIG. 4C, item 450) with a conductor (FIG. 4D, item 422),
forming a cap layer (FIG. 4E, item 418) on the metal layer (FIG. 4E, item 420).
disposing the conductor (FIG. 4E, item 422) on the cap layer (FIG. 4E, item 418)
Ishizaka et al fails to explicitly disclose a trench to expose a source/drain region, perform a pre-clean process on the source/drain region, forming a doped semiconductor layer on the source/drain region, wherein the doped semiconductor layer has a lower electrical resistance than the source/drain region; forming a metal silicide layer on the doped semiconductor layer; forming a cap layer on the metal silicide layer; ; and disposing a contact etch stop layer on a portion of the source/drain region.
However, Fukushima teaches a trench ([0060], i.e. a storage-node contact hole (hole) is defined) to expose a source/drain region (Claim 19, i.e. contact hole exposing a source/drain region formed in the semiconductor),
perform a pre-clean process ([0062], i.e. Next, after cleaning inside of the third groove 14A, DOPOS 16 for a storage-node contact is formed in the entire surface and subsequently, is etched back to have a thickness lower than the mask nitride film 10 on the bit line) on the source/drain region (FIG. 17, item 3)
forming a doped semiconductor layer (FIG. 19A, item 16G; [0008], introducing predetermined impurity to polycrystalline silicon prior to forming the metal silicide layer)) on the source/drain region (FIG. 17A, item 3), wherein the doped semiconductor layer (FIG. 19, item 16G; [0046], i.e. a polycrystalline silicon film (Ge-Poly-Si) 16G, into which germanium ion is introduced; [0062], i.e. germanium is ion-implanted into the etched-back DOPOS 16, for example, at energy of 20 KeV and with a dose of 3 X1014 atoms/cm2). As a result, Ge-Poly-Si 16G is prepared (FIG. 19)) has a lower electrical resistance ([0008], i.e. to reduce contact resistance by introducing predetermined impurity to polycrystalline silicon) than the source/drain region ([0050], i.e. diffusion layer 3, which is a source or drain region of a transistor, is formed. For example, phosphorous is used as the impurity and is introduced by ion-implantation at energy of 30 KeV and with a dose of 2X1013 atoms/cm2);
filling the trench with a conductor (Claim 18, i.e. forming a conductive layer in the substrate contact hole);
forming a metal silicide layer (FIG. 22(a), item 19; [0065], i.e. cobalt silicide film 19 is formed) on the doped semiconductor layer (FIG. 22(a), item 16G); forming a cap layer (FIG. 23(a), item 20) on the metal silicide layer (FIG. 23(a), item 19); disposing the conductor (FIG. 23(a), item 21) on the cap layer (FIG. 23(a), item 20);
Since Both Ishizaka et al and Fukushima teach a cleaning process for forming contacts, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the processing system as disclosed to modify Ishizaka et al with teachings of the trench to expose a source/drain region, perform a pre-clean process on the source/drain region, forming a doped semiconductor layer on the source/drain region, wherein the doped semiconductor layer has a lower electrical resistance than the source/drain region; forming a metal silicide layer on the doped semiconductor layer; forming a cap layer on the metal silicide layer as disclosed by Fukushima. The use of introducing predetermined impurity to polycrystalline silicon prior to forming the metal silicide layer in Fukushima provides for reduced contact resistance (Fukushima, [0008]).
Ishizaka et al and Fukushima et al fail to explicitly disclose disposing a contact etch stop layer on a portion of the source/drain region.
Basker et al, teaching an analogous art to that of Fukushima, discloses a contact etch stop layer 60L disposed on a second portion of source/drain region 32, 34 [Figs. 11-13, item 60L; [0075], i.e. The nitride cap layer 60L, which has a good etch resistance to protect the first and the second epitaxial source/drain regions 32, 34)].
Since Ishizaka et al, Fukushima and Basker et al teach contacts, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the source/drain region as disclosed to modify Ishizaka et al, and Fukushima with the teachings of the etch stop layer as disclosed by Basker et al. The use of the nitride cap layer in Basker et al provides for a good etch resistance to protect the first and the second epitaxial source/drain regions 32, 34 from any damage during subsequent etching of the ILD layer (Basker et al, [0075]).
Regarding claims 5. Ishizaka et al, Fukushima, and Basker et al discloses all the limitation of the processing system (FIG. 7, item 700) of claim 1 above.
Ishizaka et al further discloses wherein the computer instruction code ([0062], i.e. The controller 310 may be implemented as a general purpose computer system that performs a portion or all of the microprocessor based processing steps of the invention in response to a processor executing one or more sequences of one or more instructions contained in a memory) causes a process to be performed in the processing system that includes:
forming a cap layer (FIG. 4E, item 418) on the metal layer (FIG. 4E, item 420).
disposing the conductor (FIG. 4E, item 422) on the cap layer (FIG. 4E, item 418)
Ishizaka et al fail to explicitly disclose forming a metal silicide layer on the doped semiconductor layer; forming a cap layer on the metal silicide layer; and disposing a contact etch stop layer on a portion of the source/drain region.
However, Fukushima teaches forming a metal silicide layer (FIG. 22(a), item 19; [0065], i.e. cobalt silicide film 19 is formed) on doped semiconductor layer (FIG. 22(a), item 16G; [0008], i.e. to reduce contact resistance by introducing predetermined impurity to polycrystalline silicon prior to forming the metal silicide layer); - forming a cap layer (FIG. 23(a), item 20) on the metal silicide layer (FIG. 23(a), item 19);
Since Ishizaka et al and Fukushima teach a cleaning process for forming contacts, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the processing system as disclosed to modify Ishizaka et al with the teachings of the forming a metal silicide layer on the doped semiconductor layer; forming a cap layer on the metal silicide layer; and disposing a contact etch stop layer on a portion of the source/drain region as disclosed by Fukushima. The use of introducing predetermined impurity to polycrystalline silicon prior to forming the metal silicide layer in Fukushima provides for reduced contact resistance (Fukushima, Col 1, line 60-62).
Ishizaka et al and Fukushima are silent about an etch stop layer. Basker, teaching an analogous art to that of Fukushima, discloses a contact etch stop layer 60L disposed on a second portion of source/drain region 32, 34 [Figs. 11-13, item 60L; [0075], i.e. The nitride cap layer 60L, which has a good etch resistance to protect the first and the second epitaxial source/drain regions 32, 34)].
It would have been obvious to a person having skills in the art to have modified the device in Fukushima by utilizing etch stop layer for the purpose of protect underlying source/drain region from subsequent layer etching in Basker et al ([0075]).
Since Ishizaka et al, Fukushima and Basker et al teach contacts, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the source/drain region as disclosed to modify Ishizaka et al and Fukushima with the teachings of the etch stop layer as disclosed by Basker et al. The use of the nitride cap layer in Basker et al provides for a good etch resistance to protect the first and the second epitaxial source/drain regions 32, 34 from any damage during subsequent etching of the ILD layer (Basker et al, [0075]).
Regarding claims 10. Ishizaka et al, Fukushima, and Basker et al discloses all the limitation of the processing system (FIG. 7, item 700) of claim 1 above.
Ishizaka et al further discloses wherein the computer instruction code ([0098]) further causes a process ([0099]) to be performed in the processing system ([0096]-[0099]) that forms a semiconductor device ([Abstract]) comprising:
a region ([0065];FIG. 4A) extending between dielectric material (FIG. 4A, item 404) and from a semiconductor structure ([Abstract]),
a conductor (FIG. 4E, item 422) filled in a trench (FIG. 4D, item 450), wherein the trench (FIG. 4A, item 450) is formed in a dielectric material (FIG. 4A, item 404) to expose the region ([0065];FIG. 4A), wherein the cap layer (FIG. 4E, item 418) is additionally disposed on the dielectric material (FIG. 4E, item 404).
Ishizaka et al fails to explicitly disclose a source/drain region extending between dielectric material, a doped semiconductor layer disposed on a first portion of the source/drain region, wherein the trench is formed in a dielectric material to expose the source/drain region.
Fukushima teaches a source/drain region (FIG. 17A, item 3; [0050], i.e. diffusion layer 3, which is a source or drain region of a transistor) extending between ([0060], i.e. e first interlayer insulating film 14 in the memory cell region is etched to have a line shape so as to form third groove 14A exposing the diffusion layer 3) dielectric material (FIG. 17A, item 14; [0060], i.e. first interlayer insulating film), a doped semiconductor layer (FIG. 19A, item 16G; [0008], introducing predetermined impurity to polycrystalline silicon prior to forming the metal silicide layer)) disposed on a first portion ([0050], i.e. that diffusion layer 3, which is a source or drain region of a transistor, is formed) of the source/drain region (FIG. 17A, item 3) , wherein the trench ([0060], i.e. a storage-node contact hole (hole) is defined) is formed ([0060], i.e. Next, in order to form a storage-node contact, the first interlayer insulating film 14 in the memory cell region is etched to have a line shape so as to form third groove 14A exposing the diffusion layer 3 on the surface of the semiconductor substrate) in a dielectric material (FIG. 16A, item 14) to expose the source/drain region (FIG. 16A, item 3).
Since Ishizaka et al and Fukushima teach a cleaning process for forming contacts, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the processing system as disclosed to modify Ishizaka et al with the teachings of the forming a metal silicide layer on the doped semiconductor layer; forming a cap layer on the metal silicide layer; disposing the conductor on the cap layer; and disposing a contact etch stop layer on a portion of the source/drain region as disclosed by Fukushima. The use of introducing predetermined impurity to polycrystalline silicon prior to forming the metal silicide layer in Fukushima provides for reduced contact resistance (Fukushima, [0008]).
Regarding claim 11. Ishizaka et al, Fukushima, and Basker et al discloses all the limitation of the processing system (FIG. 7, item 700) of claim 10 above.
Ishizaka et al discloses wherein the computer instruction code has instructions ([0098])
Fukushima further discloses which form the source/drain region (FIG. 2, 3(a)-3(c), item 3; [0051], i.e. FIGS. 3(a) to 3(c) show cross sectional views after the diffusion layer 3 is formed in the memory cell region. FIG. 3(a) shows the A-A cross section in FIG. 2,) from a silicon, germanium, silicon-germanium, or group Ill/V compound semiconductors ([0049], i.e. P-type silicon substrate)
Regarding claim 12. Ishizaka et al, Fukushima, and Basker et al discloses all the limitation of the processing system (FIG. 7, item 700) of claim 11 above.
Ishizaka et al discloses wherein the computer instruction code has instructions ([0098]).
Fukushima discloses which form the semiconductor structure (FIG. 2, 3(a)-3(c), item 1) from a silicon, germanium, silicon-germanium, or group Ill/V compound semiconductors ([0049], i.e. First, a P-type silicon substrate is used as the semiconductor substrate 1).
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Ishizaka et al (U.S. 2010/0248473) and Fukushima (U.S. 2012/0193696), and Basker et al (U.S. (U.S. Patent No. 2016/0099246) as applied to claim 1 above, and further in view of Dube et al (U.S. 2017/0084449)
Regarding claim 2. Ishizaka et al, Fukushima, and Basker et al discloses all the limitation of the processing system (FIG. 7, item 700) of claim 1 above.
Ishizaka et al further discloses wherein the plurality of process chambers (FIG. 7, item 704B-C,706A-D) comprises a first process chamber (FIG. 7, item 706A, 706C) configured to perform an deposition process ([0093], i.e. processing system 706A configured for exposing the patterned substrates to a deposition gas to deposit metal-containing cap layers onto the substrates, and processing system 706C for optionally exposing metal-containing cap layers to a dopant gas).
Ishizaka et al, Fukushima, and Basker et al fails to explicitly disclose a first processing chamber configured to perform an epitaxial deposition process.
However, Dube et al teaches a first processing chamber (FIG. 7, item 190B) configured to perform an epitaxial deposition process ([0050], i.e. epitaxial deposition chamber adapted to epitaxially deposit one or more materials).
Since Ishizaka et al, Fukushima, Basker et al and Dube et al teach deposition process, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the processing system as disclosed to modify Ishizaka et al, Fukushima, and Basker et al with the teachings of the first processing chamber configured to perform an epitaxial deposition process as disclosed by Dube et al. The use of the epitaxial deposition chamber adapted to epitaxially deposit one or more materials in Dube provides for an apparatus suitable for performing improved semiconductor processing methods (Dube et al, [0007])
Regarding claim 3. Ishizaka et al, Fukushima, Basker et al, and Dube et al discloses all the limitation of the processing system (FIG. 7, item 700) of claim 2 above.
Ishizaka et al further discloses wherein the plurality of process chambers (FIG. 7, items 704B-C, 706A-D) further comprises a second process chamber (FIG. 7, item 706B, 706D) configured to perform a pre-clean process ([0095] plasma excited reducing gas containing H.sub.2, NH.sub.3, N.sub.2, NH(CH.sub.3).sub.2, N.sub.2H.sub.4, or N.sub.2H.sub.3CH.sub.3, or a combination thereof.) .
Regarding claim 4. Ishizaka et al, Fukushima, Basker et al, and Dube et al discloses all the limitation of the processing system (FIG. 7, item 700) of claim 3 above.
Ishizaka et al further discloses further comprising a second transfer chamber (FIG.7, item 703) coupled to the first transfer chamber (FIG. 7, item 705) by pass-through chambers (FIG. 7, item 704E).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Ishizaka et al (U.S. 2010/0248473), Fukushima (U.S. Patent No. 2012/0193696), Basker et al (U.S. 2016/0099246) as applied to claim 5 above, and further in view of Dube et al (U.S. 2017/0084449).
Regarding claim 6. Ishizaka et al, Fukushima, and Basker et al discloses all the limitation of the processing system (FIG. 7, item 700) of claim 5 above.
Ishizaka et al, Fukushima and Basker et al fail to explicitly disclose wherein the computer instruction code causes a selective epitaxial deposition process.
Fukushima discloses the doped semiconductor layer 16G comprising doped silicon-germanium ([Fig. 19A, item 16G; [0062]). Fukushima does not suggest the doped semiconductor layer formed by a selective epitaxial deposition process.
Dube et al discloses wherein the computer instruction code ([0047], i.e. microprocessor controller 181 programmed to carry out the various processing methods described herein) causes a selective epitaxial deposition process (abstract, i.e. apparatus for performing the methods, an epitaxial deposition chamber)
Since Ishizaka et al, Fukushima, Basker et al, and Dube teach contacts. It would have been obvious to one having skills in the art to have modified the technique for forming the doped semiconductor layer in Ishizaka et al, Fukushima, and Basker et al by utilizing the first processing chamber configured to perform an epitaxial deposition process as disclosed by Dube et al. The use of the epitaxial deposition chamber adapted to epitaxially deposit one or more materials in Dube et al provides for an apparatus suitable for performing improved semiconductor processing methods (Dube et al, [0007])
Claims 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Ishizaka et al (U.S. 2010/0248473), Fukushima (U.S. U.S. 2012/0193696), and Basker et al (U.S. (U.S. 2016/0099246) and Dube et al (U.S. 2017/0084449) discloses all the limitations of claim 6 above, and further in view of Bao et al (U.S. 2018/0076065).
Regarding claim 7. Ishizaka et al, Fukushima, Basker et al and Dube et al discloses all the limitation of the processing system (FIG. 7, item 700) of claim 6 above.
Fukushima discloses the metal silicide layer 19 comprises titanium silicide [col. 7, ln.22],. cobalt silicide or ruthenium silicide. Fukushima does not suggest the metal silicide layer formed by a selective epitaxial deposition process.
Dube et al further discloses wherein the computer instruction code ([0047], i.e. microprocessor controller 181 programmed to carry out the various processing methods described herein) causes a selective epitaxial deposition process (abstract, i.e. apparatus for performing the methods, an epitaxial deposition chamber)
Ishizaka et al, Fukushima, Basker et al and Dube et al fails to explicitly disclose a selective epitaxial process to form the metal silicide.
However, Bao et al teaches a selective epitaxial process to form the metal silicide ([0022], i.e. At operation 160, the substrate is transferred to a fifth process chamber and a titanium silicide layer may be selectively formed on the substrate. The fifth process chamber may be a RP Epi chamber that is available from Applied Materials, Inc. of Santa Clara, Calif. In one implementation, operation 140, operation 150 and operation 160 are performed in the same process chamber)
Since Ishizaka et al, Fukushima, Basker et al, Dube et al and Bao et al teach contacts, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the wherein the computer instruction code causes a selective epitaxial deposition process as disclosed to modify Ishizaka et al, Fukushima, Basker et al and Dube et al with the teachings of the selective epitaxial process to form the metal silicide as disclosed by Bao et al. The use of the substrate is transferred to a fifth process chamber and a titanium silicide layer may be selectively formed on the substrate and the fifth process chamber may be a RP Epi chamber in Bao et al provides for the surface of the substrate is contaminant free which improves the quality of the epitaxial layer subsequently formed on the surface of the substrate (Bao et al, [0021]).
Regarding claim 8. Ishizaka et al, Fukushima, Basker et al, Dube et al and Bao et al discloses all the limitation of the processing system (FIG. 7, item 700) of claim 7 above.
Dube et al further discloses wherein the computer instruction code ([0047], i.e. microprocessor controller 181 programmed to carry out the various processing methods described herein) causes a atomic deposition process to form the cap layer (FIG. 1, item 214; ([0043], i.e. capping layer 214 may be deposited by an atomic layer deposition (ALD) process) with a titanium nitride, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, or manganese oxide ([0044] Suitable materials for the capping layer 214 include metal oxide materials, such as aluminum oxide, hafnium oxide, zirconium oxide, manganese oxide, among others)
Regarding claim 9, Ishizaka et al, Fukushima, Dube et al, Basker et al and Bao et al discloses all the limitation of the processing system (FIG. 3, item 300) of claim 8 above.
Ishizaka et al further discloses wherein the computer instruction code ([0098]) forms the conductor (FIG. 4E, item 422) with a metal ([0075], i.e. Cu metal layer 422 contains Cu metal surface 423 and can be formed by filling the recessed feature 450 with bulk Cu metal).
Claims 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over Ishizaka et al (U.S. 2010/0248473) and Fukushima (U.S. 2012/0193696), and Basker et al (U.S. (U.S. Patent No. 2016/0099246) as applied to claim 12 above, and further in view of Dube et al (U.S. 2017/0084449)
Regarding claim 13. Ishizaka et al, Fukushima, and Basker et al discloses all the limitation of the processing system (FIG. 7, item 700) of claim 12 above.
Ishizaka et al, Fukushima and Basker et al fail to explicitly disclose wherein the computer instruction code causes a selective epitaxial deposition process to form the doped semiconductor layer from a doped silicon, doped germanium, doped silicon- germanium, or doped group Ill/V compound semiconductors.
Fukushima discloses the doped semiconductor layer (FIG. 19A, item 16G) comprising doped silicon-germanium ([Fig. 19A, item 16G; [0062]).
Fukushima does not suggest the doped semiconductor layer formed by a selective epitaxial deposition process.
Dube et al discloses wherein the computer instruction code ([0047], i.e. microprocessor controller 181 programmed to carry out the various processing methods described herein) causes a selective epitaxial deposition process (abstract, i.e. apparatus for performing the methods, an epitaxial deposition chamber)
Since Ishizaka et al, Fukushima and Basker et al and Dube et al teach contacts. It would have been obvious to one having skills in the art to have modified the technique for forming the doped semiconductor layer in Ishizaka et al, Fukushima and Basker et al by utilizing the first processing chamber configured to perform an epitaxial deposition process as disclosed by Dube et al. The use of the epitaxial deposition chamber adapted to epitaxially deposit one or more materials in Dube et al provides for an apparatus suitable for performing improved semiconductor processing methods (Dube et al, [0007])
Regarding claim 14. Ishizaka et al, Fukushima, Basker et al, and Dube et al discloses all the limitation of the processing system (FIG. 7, item 700) of claim 13 above.
Ishizaka et al further discloses wherein the computer instruction code ([0098]) has instructions ([0096]-[0098]).
Fukushima discloses which form the metal silicide layer (FIG. 22(a), item 19) from a titanium silicide, cobalt silicide, or ruthenium silicide ([0065], i.e. cobalt silicide film 19 is formed).
Regarding claim 15. Ishizaka et al, Fukushima, Basker et al, and Dube et al discloses all the limitation of the processing system (FIG. 7, item 700) of claim 14 above.
Ishizaka et al further discloses wherein the computer instruction code has instructions ([0096]-[0098]), which form the cap layer (FIG. 4E, item 418) from a titanium nitride, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, or manganese oxide ([0076])
Regarding claim 16. Ishizaka et al, Fukushima, Basker et al, and Dube et al discloses all the limitation of the processing system (FIG. 7, item 700) of claim 15 above.
Ishizaka et al further discloses wherein the computer instruction code has instructions ([0096]-[0099]) which forms the conductor (FIG. 4E, item 422) with a metal ([0075], i.e. Cu metal layer 422 contains Cu metal surface 423 and can be formed by filling the recessed feature 450 with bulk Cu metal).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Ishizaka (U.S. 2010/0248473), Fukushima (U.S. 2012/0193696), and Basker et al (U.S. 2016/0099246) as applied to claim 10 above, and further in view of Futase (U.S. 2010/0227472).
Regarding claims 17. Ishizaka et al, Fukushima, and Basker et al discloses all the limitation of the processing system (FIG. 7, item 700) of claim 10 above.
Ishizaka et al discloses wherein the computer instruction code has instructions ([0096]-[0099])
Basker et al suggest which form the contact etch stop layer (FIG. 11-13, item 60L; [0075], i.e. The nitride cap layer 60L) from a titanium nitride or tantalum nitride ([0075]).
Ishizaka et al, Fukushima, and Basker et al fails to explicitly disclose a contact etch stop layer from a silicon nitride, silicon oxynitride, silicon carbon nitride, or a combination thereof.
However, Futase et al teaches etch stop layer from a silicon nitride ([0084], i.e. The silicon nitride film is frequently used as an etch stop film in the SAC (Self-Aligned Contact) technology).
It would have been obvious to one of ordinary skill in the art to have modified the etch stop layer of Basker et al by utilizing the etch stop layer of silicon nitride of Futase as the selection of a known material based on its suitability for its intended use of an etch stop layer. The use of the silicon nitride film used as an etch stop film in Futase provides for use as a stress imparting film in SMT (Stress Memorization Technique). (Futase, [0084])
The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) (Claims to a printing ink comprising a solvent having the vapor pressure characteristics of butyl carbitol so that the ink would not dry at room temperature but would dry quickly upon heating were held invalid over a reference teaching a printing ink made with a different solvent that was nonvolatile at room temperature but highly volatile when heated in view of an article which taught the desired boiling point and vapor pressure characteristics of a solvent for printing inks and a catalog teaching the boiling point and vapor pressure characteristics of butyl carbitol. "Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.).
See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960) (selection of a known plastic to make a container of a type made of plastics prior to the invention was held to be obvious);
See MPEP 2144.07 Art Recognized Suitability for an intended purpose.
Response to Arguments
Applicant's arguments filed January 13, 2025 have been fully considered but they are not persuasive.
On page 6 of Applicant’s arguments, Applicant appears to argue that Ishizaka et al fails to disclose the computer instruction code when implemented by the CPU causes a process to be performed without a vacuum break in the processing system that includes: forming a trench in a dielectric material to expose a source/drain region.
Examiner respectfully points out that Ishizaki discloses computer instruction code therein ([0098]), the computer instruction code when implemented by the cpu ([0096]-[0098]) causes a process ([0099]) to be performed without a vacuum break ([0091], i.e. FIG. 7 is a schematic diagram of a vacuum processing tool for performing integrated processing according to embodiments of the invention. The vacuum processing tool 700 contains a substrate (wafer) transfer system 701 that includes cassette modules 701A and 701B, and a substrate alignment module 701C. Load-lock chambers 702A and 702B are coupled to the substrate transfer system 701) in the processing system (FIG. 7, item 700)
forming a trench (FIG. 4A, item 450) in a dielectric material (FIG. 4A, item 404) to expose a region ([0064]; FIG. 4A).
The Ishizaki reference states in ([0099]) stored on any one or on a combination of computer readable media, the present invention includes software for controlling the controller 710, for driving a device or devices for implementing the invention, and/or for enabling the controller 710 to interact with a human user. Such software may include, but is not limited to, device drivers, operating systems, development tools, and applications software. Such computer readable media further includes the computer program product of the present invention for performing all or a portion (if processing is distributed) of the processing performed in implementing the invention.
Examiner respectfully further points out that Fukushima teaches a trench ([0060], i.e. a storage-node contact hole (hole) is defined) to expose a source/drain region (Claim 19, i.e. contact hole exposing a source/drain region formed in the semiconductor).
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
On Page 7-8 of applicant’s remarks, applicant’s appears to be arguing that claims 2-4, 6-9 , 13-17 are allowable for the same analogous reasons as claim 1 above.
Examiner respectfully points out that claims 2-17 are rejected for the same analogous reasons as claim 1 above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/S.E.B./ Examiner, Art Unit 2815 /JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815