Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 12/1/2025 have been fully considered but they are not persuasive. Applicant argued that the prior art does not disclose: “ the first diffusion barrier layer is planar; the second diffusion barrier layer is physically and continuously joined to an additional diffusion barrier of a respective underlying one of the first plurality of vias.” Examiner respectfully disagree: Mountsier discloses (Fig. 1D) a diffusion barrier layer that is planar (under the via) and no where in the claim does it say that the barrier layer cannot be on the side surface of the via.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/10/2025 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10, 12 - 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over KANEKO et al. (US 20140097009 A1, “KANEKO”) in view of Mountsier et al. (US 20100187693 A1, “Mountsier”).
Regarding claim 10, KANEKO discloses (Fig. 1A, 17 & 18) a package (1) comprising: a plurality of polymer layers (39); a plurality of molding compound layers (31, 33, 35, 37), wherein the plurality of polymer layers and the plurality of molding compound layers are positioned alternatingly (para [0142] the insulating layer 32, 34 and 36 can be replaced by 39), and each of the plurality of molding compound layers physically contacts an overlying one and an underlying one of the plurality of polymer layers (Fig. 1A); a first plurality of vias (42, 44, 46), each in one of the plurality of polymer layers; and a second plurality of vias (41, 43, 45, 47), each in one of the plurality of molding compound layers, wherein the first plurality of vias and the second plurality of vias are electrically interconnected (see Fig. 1A); a first plurality of metal lines (20G, 20E), each in one of the plurality of polymer layers (39), wherein each of the first plurality of metal lines comprises a first diffusion barrier layer, and the first diffusion barrier layer is planar; and a second plurality of metal lines (20F, 20D), each in one of the plurality of molding compound layers (32, 34 and 36), wherein each of the second plurality of metal lines comprises a second diffusion barrier layer, and the second diffusion barrier layer is physically and continuously joined to an additional diffusion barrier of a respective underlying one of the first plurality of vias.
KANEKO fails to disclose wherein each of the first plurality of metal lines comprises a first diffusion barrier layer, and the first diffusion barrier layer is planar; and wherein each of the second plurality of metal lines comprises a second diffusion barrier layer, and the second diffusion barrier layer is physically and continuously joined to an additional diffusion barrier of a respective underlying one of the first plurality of vias
However, Mountsier discloses (Fig. 1D) wherein each of the first plurality of metal lines comprises a first diffusion barrier layer (105), and the first diffusion barrier layer is planar (see Fig. 1D); and wherein each of the second plurality of metal lines comprises a second diffusion barrier layer (105), and the second diffusion barrier layer is physically and continuously joined to an additional diffusion barrier of a respective underlying one of the first plurality of vias (109).
KANEKO and Mountsier are both considered to be analogous to the claimed invention because they are in the same field of multi-layer substrate. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified KANEKO to incorporate the teachings of Mountsier and provide wherein each of the first plurality of metal lines comprises a first diffusion barrier layer (105), and the first diffusion barrier layer is planar (see Fig. 1D); and wherein each of the second plurality of metal lines comprises a second diffusion barrier layer (105), and the second diffusion barrier layer is physically and continuously joined to an additional diffusion barrier of a respective underlying one of the first plurality of vias (109). Doing so would block the conductive materials from conductive lines into dielectric materials (abstract).
Regarding claim 12, KANEKO in view of Mountsier discloses the package of claim 10, wherein KANEKO further discloses that each of the first plurality of vias (42, 44, 46) is physically and continuously connected to an overlying conductive line without interface in between (see fig. 1A). .
Regarding claim 13, KANEKO in view of Mountsier discloses the package of claim 10, wherein KANEKO further discloses that the plurality of polymer layers (39) are thinner than the plurality of molding compound layers (para [0140]).
Claim(s) 11, 14 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over KANEKO et al. (US 20140097009 A1, “KANEKO”) in view of Mountsier et al. (US 20100187693 A1, “Mountsier”) as applied to claim 10 above, and further in view of MAEDA et al. (US 20130161079 A1, “MAEDA”).
Regarding claim 11, KANEKO in view of Mountsier discloses the package of claim 10, KANEKO in view of Mountsier fails to disclose wherein each of the second plurality of vias forms a planar interface with an overlying conductive line (see annotated figure below).
However MAEDA discloses, wherein each of the second plurality of vias forms a planar interface with an overlying conductive line (see annotated figure below). It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have each of the second plurality of vias forms a planar interface with an overlying conductive line as shown by MAEDA, with the circuit board of KANEKO in view of Mountsier, since as shown by MAEDA having each of the second plurality of vias forms a planar interface with an overlying conductive line is commonly done as it simplifies the manufacturing process.
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Regarding claim 14, KANEKO in view of Mountsier discloses the package of claim 10, KANEKO in view of Mountsier fails to disclose wherein each of the second plurality of vias has a top surface coplanar with a top surface of a respective one of the molding compound layers.
However MAEDA discloses, wherein each of the second plurality of vias has a top surface coplanar with a top surface of a respective one of the molding compound layers (see annotated figure above). It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have each of the second plurality of vias has a top surface coplanar with a top surface of a respective one of the molding compound layers as shown by MAEDA, with the circuit board of KANEKO in view of Mountsier, since as shown by MAEDA having wherein each of the second plurality of vias has a top surface coplanar with a top surface of a respective one of the molding compound layers is commonly done as it simplifies the manufacturing process.
Regarding claim 16, KANEKO in view of Mountsier discloses the package of claim 10, wherein each of the plurality of polymer layers (39) is formed of a homogeneous material (para [0140]), and each of the plurality of molding compound layers (31, 33, 35, 37) comprises a base material (para [0140]).
KANEKO in view of Mountsier fails to disclose filler particles in the base material.
However, MAEDA discloses (Fig. 3) filler particles in the base material (para [0046]).
KANEKO in view of Mountsier and MAEDA are both considered to be analogous to the claimed invention because they are in the same field of wiring substrate. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified KANEKO in view of Mountsier to incorporate the teachings of MAEDA and provide filler particles in the base material (para [0046]). Doing so would lower the coefficient of thermal expansion.
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over KANEKO et al. (US 20140097009 A1, “KANEKO”) in view of Mountsier et al. (US 20100187693 A1, “Mountsier”) as applied to claim 10 above, and further in view of LAI et al. (US 20150214162 A1, “LAI”).
Regarding claim 21, KANEKO in view of Mountsier discloses the package of claim 10, KANEKO in view of Mountsier is silent on wherein an entirety of the first diffusion barrier layer is planar, and wherein the first diffusion barrier layer comprises both of a vertical portion and a horizontal portion.
However, LAI discloses (Fig. 2) wherein an entirety of the first diffusion barrier layer (150) is planar, and wherein the first diffusion barrier layer comprises both of a vertical portion and a horizontal portion (see Fig. 2).
KANEKO in view of Mountsier and LAI are both considered to be analogous to the claimed invention because they are in the same field of multi-layer substrate. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified KANEKO in view of Mountsier to incorporate the teachings of LAI and provide wherein an entirety of the first diffusion barrier layer (150) is planar, and wherein the first diffusion barrier layer comprises both of a vertical portion and a horizontal portion (see Fig. 2). Doing so would provide long-term reliability and optimal electrical performance.
Allowable Subject Matter
Claim 1 – 5, 7 – 9 and 17 – 20 are allowed.
Claim 22 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SIDI MOHAMED MAIGA whose telephone number is (703)756-1870. The examiner can normally be reached Monday - Friday 8 am 5 pm.
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/SIDI M MAIGA/
Examiner, Art Unit 2847
/STANLEY TSO/Primary Examiner, Art Unit 2847