DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 21-26, 32-38, and 40-44 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US PGPub 2019/0148375, hereinafter referred to as “Lin”).
Lin discloses the semiconductor method as claimed. See figures 1A-29 and corresponding text, where Lin teaches, claim 21, a method for forming a semiconductor arrangement, comprising:
forming a gate electrode layer (802); (sacrificial gate material) (figures 8A and 8B; [0066])
etching the gate electrode layer (802) to define a gate electrode (802), a first portion (1206) of the gate electrode (802) overlying an interface (the examiner views the interface being defined as the portions where the active area and isolation structure meet) where a top surface of a substrate (102) abuts a top surface of a shallow trench isolation (STI) structure (104); (figures 1A-1B and 8-9B; [0021], Lin teaches that the STI structures are formed within an upper surface of the substrate, thus examiner views this abuts a top surface [0066-0069])
forming a mask (1202) over the first portion of the gate electrode (1206) such that the mask overlies the interface (the examiner views that since the masks are located above portions where the active area and isolation structure meet, the mask overlies the interface portions); (figures 12A and 12B; [0072])
removing a second portion of the gate electrode (802) while the mask (1202) is over the first portion of the gate electrode (802) to define a first gate cavity (1302);
forming a first gate electrode portion (116) in the first gate cavity (1302); (figures 13A and 13B; [0073])
removing the first portion of the gate electrode (802) to define a second gate cavity (1502) after forming the first gate electrode portion; (figures 15A and 15B; [0075])
forming a first gate dielectric layer (112) in the second gate cavity (1502); and (figures 15A and 15B; [0075])
forming a second gate electrode portion (114) in the second gate cavity (1302) after forming the first gate dielectric layer (112), wherein the first gate dielectric layer (112) separates at least some of the first gate electrode portion from at least some of the second gate electrode portion lying in a same plane, parallel to the top surface of the substrate (102), as the at least some of the first gate electrode portion (figures 16A and 16B; [0076], the examiner views that the limitation does not require that entire gate electrode portions to be in the same plane. In addition, Lin teaches that there is discontinuity between the first and second gate electrode portions respectively, where the portions that do not overly the gate dielectric layer is separate from the portions that are over the dielectric layer). (See modified illustration below)
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Lin teaches, claim 22, wherein a material composition of the second gate electrode portion is different than a material composition of the first gate electrode portion. ([0024])
Lin teaches, claim 23, comprising:
forming a sidewall spacer (302) around the gate electrode (802) prior to forming the mask. (figures 12A and 12B; [0072])
Lin teaches, claim 24, comprising:
forming a dielectric layer (1002) after etching the gate electrode layer to define the gate electrode, wherein forming the mask comprises forming the mask to overlie a first portion of the dielectric layer overlying the STI structure. (figures 10A and 10B; [0070])
Lin teaches, claim 25, comprising:
forming a second gate dielectric layer in the first gate cavity prior to forming the first gate electrode portion, wherein the second gate dielectric layer separates the first gate electrode portion from the first portion of the gate electrode. ([0065])
Lin teaches, claim 26, wherein a sidewall of the second gate dielectric layer contacts a sidewall of the first gate dielectric layer. (figures 15A and 15B; [0075])
Lin teaches, claim 32, wherein forming the second gate electrode portion comprises forming the second gate electrode portion such that some of the first gate electrode portion contacts some of the second gate electrode portion. (figures 16A and 16B; [0076-0077])
Lin teaches, claim 33, a method for forming a semiconductor arrangement, comprising:
forming a gate electrode layer (802);
etching the gate electrode layer (802) to define a gate electrode (802), a first portion of the gate electrode overlying an interface between a substrate (102) and a shallow trench isolation (STI) structure (104);
forming a mask (1202) over the first portion of the gate electrode (116) such that the mask overlies the interface;
removing a second portion of the gate electrode (116) while the mask (1202) is over the first portion of the gate electrode to define a first gate cavity (1302) wherein the STI structure is not exposed when the second portion of the gate electrode is removed (figures 13A and 13B; [0071-0073], the examiner views that portions under the mask (302) are not exposed when the second portion of the gate electrode is formed);
forming a first gate dielectric layer (112) in the first gate cavity; (1302)
forming a first gate electrode portion (116) in the first gate cavity after forming the first gate dielectric layer (112);
removing the first portion of the gate electrode (802) to define a second gate cavity (1502) after forming the first gate electrode portion (116); and
forming a second gate electrode portion (114) in the second gate cavity (1502), wherein the first gate dielectric layer (112) separates at least some of the first gate electrode portion (116) from at least some of the second gate electrode portion (114).
Lin teaches, claim 34, wherein a material composition of the second gate electrode portion is different than a material composition of the first gate electrode portion. ([0024])
Lin teaches, claim 35, comprising:
forming a sidewall spacer (302) around the gate electrode (802) prior to forming the mask. (figures 12A and 12B; [0072])
Lin teaches, claim 36, comprising:
forming a dielectric layer (1002) after etching the gate electrode layer (802) to define the gate electrode (802), wherein forming the mask comprises forming the mask to overlie a first portion of the dielectric layer (1002) overlying the STI structure (104).
Lin teaches, claim 37, comprising:
forming a second gate dielectric layer in the second gate cavity before forming the second gate electrode portion. ([0065])
Lin teaches, claim 38, wherein forming the second gate dielectric layer comprises forming the second gate dielectric layer to contact a sidewall of the first gate dielectric layer. ([0065])
Lin teaches, claim 40, wherein the first gate electrode portion is separated from the first portion of the gate electrode by the first gate dielectric layer. (figures 16A and 16B; [0076-0077])
Lin teaches, claim 41, a method for forming a semiconductor arrangement, comprising:
forming a gate electrode layer (802);
etching the gate electrode layer (802) to define a gate electrode (802), a first portion of the gate electrode (802) overlying an interface where a top surface of a substrate (102) abuts a top surface of a shallow trench isolation (STI) structure (104);
forming a mask (1202) over the first portion of the gate electrode (802) such that the mask overlies the interface;
removing a second portion of the gate electrode (802) while the mask is over the first portion of the gate electrode to define a first gate cavity (1302) such that a sidewall of the first gate dielectric layer contacts a sidewall of the first portion of the gate electrode;
forming a first gate dielectric layer (112) in the first gate cavity (1302) such that a sidewall of the first gate dielectric layer contacts a sidewall of the first portion of the gate electrode (figures 15A and 15B; [0073-0075], the examiner views that the portions underneath the gate electrode portions are the sidewalls);
removing a first portion of the first gate dielectric layer (112); ([0065])
forming a first gate electrode portion (116) in the first gate cavity (1302) after removing the first portion of the first gate dielectric layer; (figures 15A and 15B; [0075])
removing the first portion of the gate electrode (802) to define a second gate cavity (1502) after forming the first gate electrode portion (116); and
forming a second gate electrode portion (114) in the second gate cavity (1502); wherein a second portion of the first gate dielectric layer (112) separates at least some of the first gate electrode portion (116) from at least some of the second gate electrode portion (114).
Lin teaches, claim 42, wherein forming the second gate electrode portion comprises forming the second gate electrode portion such that some of the first gate electrode portion contacts some of the second gate electrode portion. (figures 16A and 16B; [0076-0077])
Lin teaches, claim 43, comprising:
forming a sidewall spacer (302) around the gate electrode prior to forming the mask. (figures 12A and 12B; [0072])
Lin teaches, claim 44, comprising:
forming a dielectric layer (1002) after etching the gate electrode layer (802) to define the gate electrode, wherein forming the mask (1202, 1204) comprises forming the mask to overlie a first portion of the dielectric layer (1002) overlying the STI structure. (figures 11A and 11B; [0071])
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 28 and 39 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US PGPub 2019/0148375, hereinafter referred to as “Lin”) as applied to claims 1 and 33 above, and further in view of Chao et al. (US PGPub 2019/0148241, hereinafter referred to as “Chao”).
Lin discloses the semiconductor method substantially as claimed. See the rejection above.
However, Lin fails to show, in claim 28, comprising:
removing a portion of the first gate dielectric layer prior to forming the second gate electrode portion to expose a sidewall of the first gate electrode portion.
Lin does teach that a second etchant may include various chemistries that also include a wet etching ([0075]).
Chao teaches, in claim 28, the selectivity of first and second etching processes of a dummy gate electrode layer (220) and dummy gate dielectric layers (210) that includes the second etchant to be a wet etching process ([0076]). In addition, provides the advantages of reducing short channel effect and higher current flow ([0003]).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was filed, to incorporate removing a portion of the first gate dielectric layer prior to forming the second gate electrode portion to expose a sidewall of the first gate electrode portion, in the method of Lin, according to the teachings of Chao, with the motivation of reducing short channel effect and higher current flow.
Lin fails to show, claim 39, comprising:
removing a portion of the first gate dielectric layer prior to forming the first gate electrode portion to expose a sidewall of the first portion of the gate electrode.
Lin does teach that a second etchant may include various chemistries that also include a wet etching ([0075]).
Chao teaches, in claim 39, the selectivity of first and second etching processes of a dummy gate electrode layer (220) and dummy gate dielectric layers (210) that includes the second etchant to be a wet etching process ([0076]). In addition, provides the advantages of reducing short channel effect and higher current flow ([0003]).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was filed, to incorporate removing a portion of the first gate dielectric layer prior to forming the second gate electrode portion to expose a sidewall of the first gate electrode portion, in the method of Lin, according to the teachings of Chao, with the motivation of reducing short channel effect and higher current flow.
Response to Arguments
Applicant's arguments filed 12/16/25 have been fully considered but they are not persuasive. In the Remarks on pages 7-10:
Applicant raises the clear issue as to whether Lin suggests or renders obvious the limitation of “wherein the first gate dielectric layer separates at least some of the first gate electrode portion from at least some of the second gate electrode portion lying in a same plane, parallel to the top surface of the substrate, as the at least some of the first gate electrode portion.”; “etching the gate electrode layer to define a gate electrode, a first portion of the gate electrode overlying an interface wherein a top surface of a substrate abuts a top surface of a shallow trench insolation.
The examiner views that Lin does suggest the above limitations and/or statements. Specifically, the claim language does not require the entire gate electrode portion to be in the same plane. Therefore, Lin teaches in figures 16A and 16B; [0076], portions of the first and second gates, respectively, located over the gate dielectric layer are separate from portions that are not located over the gate dielectric (See the modified illustration) because the gate portions are discontinuous. In addition, the examiner views the interface being defined as the portions where the active area and isolation structure meet, where a top surface of a substrate (102) abuts a top surface of a shallow trench isolation (STI) structure (104). Furthermore, in figures 1A-1B and 8-9B; [0021], Lin teaches that the STI structures are formed within an upper surface of the substrate, thus abuts a top surface [0066-0069]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANETTA D ISAAC whose telephone number is (571)272-1671. The examiner can normally be reached M-F 10-6.
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/STANETTA D ISAAC/Examiner, Art Unit 2898 February 26, 2026