DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 11, 38, 39, 57-59 and 68-71, 73-75, 80 and 81 have been considered but are moot on grounds of new rejection.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11 and 80 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 11 recites the limitation "the monolithic encapsulant" in line 30. There is insufficient antecedent basis for this limitation in the claim. Appropriate correction is required. Claim 80 inherits these deficiencies due to its dependency.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 11 is/are rejected under 35 U.S.C. 103 as being obvious over Chen et al. (Chen) (US 20190131273 A1) in view of We et al. (We) (US 9,443,824 B1) as evidenced by or in view of Chen et al. (Chen’264) (US 2014/0185264 A1) or Lin et al. (Lin) (US 2020/0328161 A1).
In regards to claim 1, Chen (Figs. 4-6, 7D, 7F, 7G, 9, 12 and associated text and items) discloses an electronic device (Figs. 1-6, 7G, 12, 14), comprising: a low density wiring structure (first layer of multilayer item 102, paragraph 15); a high density wiring structure (second or more layers of multilayer items 102 with more items 104, paragraph 15) disposed on and electrically connected to the low density wiring structure (first layer of multilayer item 102, paragraph 15); a first electronic component (items 100 or 200, 101 or 201) including a first conductive via (items TSV1 or TSV2) extending through the first electronic component (items 100 or 200, 101 or 201); a solder (item 501) electrically connecting the first conductive via (items TSV1 or TSV2) of the first electronic component (items 100 or 200, 101 or 201) and the high density wiring structure (second or more layers of multilayer items 102 with more items 104, paragraph 15); a first monolithic molding compound (items E1 or E1 plus UF2, paragraphs 21, 30, both E1 and UF2 can be made of epoxy, thus an integral structure) encapsulating the first electronic component (items 100 or 200) and directly contacting the first electronic component (items 100 or 200, 101 or 201) and the solder (item 501); a second wiring structure (item RDL2) disposed on the first monolithic molding compound (items E1 or E1 plus UF2, paragraphs 21, 30, both E1 and UF2 can be made of epoxy, thus an integral structure); a second electronic component (items 300 or 400) disposed on and electrically connected to the second wiring structure (item RDL2), wherein the first electronic component (items 100 or 200, 101 or 201) is within a vertical projection of the second electronic component (items 300 or 400) in a cross-sectional view; and a second monolithic molding compound (items E2 or E2 plus UF1, paragraphs 21, 30, both E2 and UF1 can be made of epoxy, thus an integral structure) encapsulating the second electronic component (items 300 or 400), wherein a lateral surface of the low density wiring structure (first layer of multilayer item 102, paragraph 15), a lateral surface of the high density wiring structure (second or more layers of multilayer items 102 with more items 104, paragraph 15), a lateral surface of the first monolithic molding compound (items E1 or E1 plus UF2, paragraphs 21, 30, both E1 and UF2 can be made of epoxy, thus an integral structure), a lateral surface of the second wiring structure (item RDL2) and a lateral surface of the second monolithic molding compound (items E2 or E2 plus UF1, paragraphs 21, 30, both E2 and UF1 can be made of epoxy, thus an integral structure) are substantially coplanar with each other (Figs. 11, 12).
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of the various embodiments of Chen for the purpose of protection and electrical connection.
Chen does not specifically disclose a low density wiring including a core substrate.
KAO (Fig. 1 and associated text) discloses a low density wiring (item 3, paragraph 30) including a core substrate (item 30a).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of KAO for the purpose of an electrical connection and support.
As evidenced by Chen’264 (Figs. 2(d) and associated text), a solder (item 217, paragraph24) can be disposed under the bottom surface of the first electronic component (item 305), wherein the monolithic molding compound (item 113) encapsulates and directly contacts the solder (item 217).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Chen’264 for the purpose of an electrical connection and protection.
As evidenced by Lin (Fig. 2F and associated text), conductive connectors (items 118, 117) can be on the top, bottom or both surfaces of an electrical component (item 110) and surrounded by a monolithic molding compound (item 240) which directly contacts the conductive connectors (items 118, 117).
In regards to claim 11, Chen (Figs. 4-6, 7B, 7D, 7E, 7F, 7G, 9, 12, 14 and associated text and items) discloses an electronic device (Figs. 12, 14), comprising: a low density wiring structure (first layer of multilayer item 102, paragraph 15); a high density wiring structure (second or more layers of multilayer items 102 with more items 104, paragraph 15) disposed on and electrically connected to the low density wiring structure (first layer of multilayer item 102, paragraph 15); wherein the high density structure (second or more layers of multilayer items 102 with more items 104, paragraph 15) includes a protrusion pad (item 103) protruding from a top surface of the high density wiring structure (second or more layers of multilayer items 102 with more items 104, paragraph 15); a first electronic component (items 100, 101, 100’, 101’) including a conductive via (items TSV1 or TSV2) extending through the first electronic component (items 100, 101, 100’, 101’) and a bump pad (item 100e) disposed on a bottom surface of the first electronic component (items 100, 101, 100’, 101’), wherein the conductive via (items TSV1 or TSV2) vertically overlaps the bump pad (item 100e); a first solder (item 501) contacting the protrusion pad (item 103) of the high density wiring structure (second or more layers of multilayer items 102 with more items 104, paragraph 15) and the bump pad (item 100e) of the first electronic component; and a second electronic component (items 300a or 300) disposed over the first electronic component (items 100, 101, 100’, 101’), wherein the first electronic component (items 100, 101, 100’, 101’) is disposed within a vertical projection of the second electronic component (items 300a or 300) in a cross-sectional view; a third electronic component (items 400a or 400) disposed adjacent to the second electronic component (items 300a or 300); a bridge die (item 150) disposed under a gap between the second electronic component (items 300a or 300) and the third electronic component (items 400a or 400) and electrically connected to the high density wiring structure (second or more layers of multilayer items 102 with more items 104, paragraph 15) through a second solder (item 501); and a first monolithic encapsulant (item E1) encapsulating the first electronic component (items 100, 101, 100’, 101’) and the bridge die (item 150), and contacting the first solder (item 501), the protrusion pad (item 103) of the high density wiring structure (second or more layers of multilayer items 102 with more items 104, paragraph 15), the bump pad (item 100e) of the first electronic component (items 100, 101, 100’, 101’) and the second solder (item 501), but does not specifically disclose a low density wiring structure including core substrate.
KAO (Fig. 1 and associated text) discloses a low density wiring (item 3, paragraph 30) including a core substrate (item 30a).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of KAO for the purpose of an electrical connection and support.
As evidenced by Chen’264 (Figs. 2(d) and associated text), a solder (item 217, paragraph24) can be disposed under the bottom surface of the first electronic component (item 305), wherein the monolithic molding compound (item 113) encapsulates and directly contacts the solder (item 217).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Chen’264 for the purpose of an electrical connection and protection.
As evidenced by Lin (Fig. 2F and associated text), conductive connectors (items 118, 117) can be on the top, bottom or both surfaces of an electrical component (item 110) and surrounded by a monolithic molding compound (item 240) which directly contacts the conductive connectors (items 118, 117).
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Claim(s) 1, 11, 38, 57-59 and 68-80 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (Chen) (US 20190131273 A1) in view of We et al. (We) (US 9,443,824 B1) as evidenced by or in view of Chen et al. (Chen’264) (US 2014/0185264 A1) and/or Lin et al. (Lin) (US 2020/0328161 A1).
In regards to claim 1, Chen (Figs. 4-6, 7D, 7F, 7G, 9, 12 and associated text and items) discloses an electronic device (Figs. 1-6, 7G, 12, 14), comprising: a low density wiring structure (first layer of multilayer item 102, paragraph 15); a high density wiring structure (RDL 1 or second or more layers of multilayer items 102 with more items 104, paragraph 15) disposed on and electrically connected to the low density wiring structure (first layer of multilayer item 102, paragraph 15); a first electronic component (items 100 or 200, 101 or 201) including a first conductive via (items TSV1 or TSV2) extending through the first electronic component (items 100 or 200, 101 or 201); a bridge die (item 150) disposed adjacent to the first electronic component (items 100 or 200, 101 or 201) and including a second through via (paragraph 65) extending through the bridge die (item 150) a solder (item 501) electrically connecting the first conductive via (items TSV1 or TSV2) of the first electronic component (items 100 or 200, 101 or 201) and the high density wiring structure (RDL1 or second or more layers of multilayer items 102 with more items 104, paragraph 15); a first monolithic molding compound (items E1 or E1 plus UF2, paragraphs 21, 30, both E1 and UF2 can be made of epoxy, thus an integral structure) encapsulating the first electronic component (items 100 or 200) and directly contacting the first electronic component (items 100 or 200, 101 or 201) and the solder (item 501); a conductive element (item TIV) extending through the first monolithic molding compound (items E1 or E1 plus UF2, paragraphs 21, 30, both E1 and UF2 can be made of epoxy, thus an integral structure); a second wiring structure (item RDL2) disposed on the first monolithic molding compound (items E1 or E1 plus UF2, paragraphs 21, 30, both E1 and UF2 can be made of epoxy, thus an integral structure); wherein both the first monolithic molding compound (items E1 or E1 plus UF2, paragraphs 21, 30, both E1 and UF2 can be made of epoxy, thus an integral structure) and the conductive element (item TIV) are in direct contact with the high density wiring structure (RDL1 or second or more layers of multilayer items 102 with more items 104, paragraph 15) and the second wiring structure (item RDL2), the first conductive (items TSV1 or TSV2) via of the first electronic component (items 100 or 200, 101 or 201) and the second through via (paragraph 65) of the bridge die (item 150) are electrically connected to the second wiring structure (item RDL2), and the second pad (shown but not labeled in Fig. 12) of the bridge die (item 150) is in direct contact with the second wiring structure (item RDL2); a second electronic component (items 300 or 400) disposed on and electrically connected to the second wiring structure (item RDL2), wherein the first electronic component (items 100 or 200, 101 or 201) is within a vertical projection of the second electronic component (items 300 or 400) in a cross-sectional view; and a second monolithic molding compound (items E2 or E2 plus UF1, paragraphs 21, 30, both E2 and UF1 can be made of epoxy, thus an integral structure) encapsulating the second electronic component (items 300 or 400) and in direct contact with the second wiring structure (item RDL2), wherein a lateral surface of the low density wiring structure (first layer of multilayer item 102, paragraph 15), a lateral surface of the high density wiring structure (RDL1 or second or more layers of multilayer items 102 with more items 104, paragraph 15), a lateral surface of the first monolithic molding compound (items E1 or E1 plus UF2, paragraphs 21, 30, both E1 and UF2 can be made of epoxy, thus an integral structure), a lateral surface of the second wiring structure (item RDL2) and a lateral surface of the second monolithic molding compound (items E2 or E2 plus UF1, paragraphs 21, 30, both E2 and UF1 can be made of epoxy, thus an integral structure) are coplanar with each other (Figs. 11, 12), but does not specifically disclose a low density wiring including a core substrate, a first through via, a first dielectric layer and a second dielectric layer, wherein the first through via extends through the core substrate and is direct contact with the core substrate and the dielectric layer, the core substrate has a first surface and a second surface opposite to the first surface, the first dielectric layer and the second dielectric layer are respectively disposed on the first surface and the second surface of the core substrate.
We (Figs. 3, 4A, 4B, 5N, 5O and associated text and items) discloses a low density wiring (items 370 plus 310 plus 320 plus 312, 470 plus 410 plus 420 plus 412, 570 plus 510 plus 520 plus 512) including a core substrate (items 310, 410, 510), a first through via (items 312, 412, 512), a first dielectric layer (items 320 or 370, 420 or 470 520 or 570) and a second dielectric layer (items 320 or 370, 420 or 470 520 or 570), wherein the first through via (items 312, 412, 512) extends through the core substrate (items 310, 410, 510) and is direct contact with the core substrate (items 310, 410, 510) and the (first or second?) dielectric layer (items 320 or 370, 420 or 470 520 or 570), the core substrate (items 310, 410, 510) has a first surface (top or bottom surface items 310, 410, 510) and a second surface (top or bottom surface items 310, 410, 510) opposite to the first surface, the first dielectric layer (items 320 or 370, 420 or 470 520 or 570) and the second dielectric layer (items 320 or 370, 420 or 470 520 or 570) are respectively disposed on the first surface (top or bottom surface items 310, 410, 510) and the second surface (top or bottom surface items 310, 410, 510) of the core substrate (items 310, 410, 510).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of We for the purpose of an electrical connection, support and insulation/protection.
Therefore, Chen (Figs. 4-6, 7D, 7F, 7G, 9, 12 and associated text and items) as modified by We (Figs. 3, 4A, 4B, 5N, 5O and associated text and items) discloses wherein the high density wiring structure (item RDL1 or second or more layers of multilayer items 102 with more items 104, paragraph 15, Chen) is in direct contact with the first though via (items 312, 412, 512) and the first dielectric layer (items 320, 420, 520, We) of the low density wiring structure items 370 plus 310 plus 320 plus 312, 470 plus 410 plus 420 plus 412, 570 plus 510 plus 520 plus 512).
As evidenced by Chen’264 (Figs. 2(d) and associated text), a solder (item 217, paragraph24) can be disposed under the bottom surface of the first electronic component (item 305), wherein the monolithic molding compound (item 113) encapsulates and directly contacts the solder (item 217).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Chen’264 for the purpose of an electrical connection and protection.
As evidenced by Lin (Fig. 2F and associated text), conductive connectors (items 118, 117) can be on the top, bottom or both surfaces of an electrical component (item 110) and surrounded by a monolithic molding compound (item 240) which directly contacts the conductive connectors (items 118, 117) and solder (shown but not labeled).
Therefore Chen as modified by We, Chen’264 and/or Lin discloses a bridge die (item 150, Chen) disposed adjacent to the first electronic component (items 100 or 200, 101 or 201, Chen) and including a second through via (paragraph 65, Chen) extending through the bridge die (item 150), and a first conductive pad (item 219, Chen’264, items 117 or 118, Lin) and a second conductive pad (Chen’264, items 117 or 118, Lin) respectively in contact with a first end and a second end of the second through via (paragraph 65, Chen, item 115, Lin); a solder (shown but not labeled, Lin, Fig. 2F) electrically connecting the first conductive via (items TSV1 or TSV2, Chen) of the first electronic component (items 100 or 200, 101 or 201) and the high density wiring structure (RDL1 or second or more layers of multilayer items 102 with more items 104, paragraph 15).
In regards to claim 11, Chen (Figs. 4-6, 7B, 7D, 7E, 7F, 7G, 9, 12, 14 and associated text and items) discloses an electronic device (Figs. 12, 14), comprising: a low density wiring structure (first layer of multilayer item 102, paragraph 15); a high density wiring structure (RDL1 or second or more layers of multilayer items 102 with more items 104, paragraph 15) disposed on and electrically connected to the low density wiring structure (first layer of multilayer item 102, paragraph 15); wherein the high density structure (RDL1 or second or more layers of multilayer items 102 with more items 104, paragraph 15) includes a protrusion pad (item 103) protruding from a top surface of the high density wiring structure (RDL1 or second or more layers of multilayer items 102 with more items 104, paragraph 15); a first electronic component (items 100, 101, 100’, 101’) including a conductive via (items TSV1 or TSV2) extending through the first electronic component (items 100, 101, 100’, 101’) and a bump pad (item 100e) disposed on a bottom surface of the first electronic component (items 100, 101, 100’, 101’), wherein the conductive via (items TSV1 or TSV2) vertically overlaps the bump pad (item 100e); the first electronic component (items 100, 101, 100’, 101’) has a top surface (top surface of items 100, 101, 100’, 101’), a bottom surface (bottom surface of items 100, 101, 100’, 101’) opposite to the top surface (top surface of items 100, 101, 100’, 101’), and a lateral surface (lateral surface of items 100, 101, 100’, 101’) extending between the top surface (top surface of items 100, 101, 100’, 101’) and the bottom surface (bottom surface of items 100, 101, 100’, 101’); a first solder (item 501) contacting the protrusion pad (item 103) of the high density wiring structure (RDL1 or second or more layers of multilayer items 102 with more items 104, paragraph 15) and the bump pad (item 100e) of the first electronic component (items 100, 101, 100’, 101’); and a second electronic component (items 300a or 300) disposed over the first electronic component (items 100, 101, 100’, 101’), wherein the first electronic component (items 100, 101, 100’, 101’) is disposed within a vertical projection of the second electronic component (items 300a or 300) in a cross-sectional view; a third electronic component (items 400a or 400) disposed adjacent to the second electronic component (items 300a or 300); a bridge die (item 150) disposed under a gap between the second electronic component (items 300a or 300) and the third electronic component (items 400a or 400) and electrically connected to the high density wiring structure (second or more layers of multilayer items 102 with more items 104, paragraph 15) through a second solder (item 501); and including a through via (paragraph 65) extending through the bridge die (item 150); a first monolithic molding compound (items E1 or E1 plus UF2, paragraphs 21, 30, both E1 and UF2 can be made of epoxy, thus an integral structure) encapsulating the first electronic component (items 100, 101, 100’, 101’) and the bridge die (item 150), and contacting the first solder (item 501), the protrusion pad (item 103) of the high density wiring structure (RDL1 or second or more layers of multilayer items 102 with more items 104, paragraph 15), the bump pad (item 100e) of the first electronic component (items 100, 101, 100’, 101’) and the second solder (item 501), but does not specifically disclose a low density wiring structure including core substrate having a first surface and a second surface opposite the first surface, the low density wiring structure including a first dielectric disposed on the first surface and a second dielectric layer disposed on the second surface;
We (Figs. 3, 4A, 4B, 5N, 5O and associated text and items) discloses a low density wiring structure (items 370 plus 310 plus 320 plus 312, 470 plus 410 plus 420 plus 412, 570 plus 510 plus 520 plus 512) including a core substrate (items 310, 410, 510) having a first surface (top or bottom surface items 310, 410, 510) and a second surface (top or bottom surface items 310, 410, 510) opposite to the first surface (top or bottom surface items 310, 410, 510), a first through via (items 312, 412, 512), a first dielectric layer (items 320 or 370, 420 or 470 520 or 570) disposed on the first surface and a second dielectric layer (items 320 or 370, 420 or 470 520 or 570) disposed on the second surface; wherein the first through via (items 312, 412, 512) extends through the core substrate (items 310, 410, 510) and is direct contact with the core substrate (items 310, 410, 510).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of We for the purpose of an electrical connection, support and insulation/protection.
As evidenced by Chen’264 (Figs. 2(d) and associated text), a solder (item 217, paragraph24) can be disposed under the bottom surface of the first electronic component (item 305), wherein the monolithic molding compound (item 113) encapsulates and directly contacts the solder (item 217).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Chen’264 for the purpose of an electrical connection and protection.
As evidenced by Lin (Fig. 2F and associated text), conductive connectors (items 118, 117) can be on the top, bottom or both surfaces of an electrical component (item 110) and surrounded by a monolithic molding compound (item 240) which directly contacts the conductive connectors (items 118, 117).
Chen (Figs. 4-6, 7B, 7D, 7E, 7F, 7G, 9, 12, 14 and associated text and items) as modified by We (Figs. 3, 4A, 4B, 5N, 5O and associated text and items), Chen’264 (Figs. 2(d) and associated text) and Lin (Fig. 2F and associated text) discloses wherein the first monolithic molding compound (items E1 or E1 plus UF2, paragraphs 21, 30, both E1 and UF2 can be made of epoxy, thus an integral structure, Chen, item 240, Lin) continuously extends along from the lateral surface of the first electronic component (items 100, 101, 100’, 101’, Chen, item 110, Lin) to the bottom surface of the first electronic component (items 100, 101, 100’, 101’, Chen, item 110, Lin) and continuously extends to the top surface of the first electronic component (items 100, 101, 100’, 101’, Chen, item 110, Lin), and the first monolithic (molding compound) encapsulant (items E1 or E1 plus UF2, paragraphs 21, 30, both E1 and UF2 can be made of epoxy, thus an integral structure, Chen, item 240, Lin) is in direct contact with the top surface, the bottom surface and the lateral surface of the first electronic component (items 100, 101, 100’, 101’, Chen, item 110, Lin), a second wiring structure (item RDL2, Chen, item 170, Lin) disposed on and in direct contact with the first monolithic molding compound (items E1 or E1 plus UF2, paragraphs 21, 30, both E1 and UF2 can be made of epoxy, thus an integral structure, Chen, item 240, Lin), wherein the second electronic component (items 300a or 300) and the third electronic component (items 400a or 400) are electrically connected to the second wiring structure (item RDL2, Chen, item 170, Lin), the first conductive via (items TSV1 or TSV2, Chen) of the first electronic component (items 100, 101, 100’, 101’, Chen, item 110, Lin) and the through via (paragraph 65, Chen) of the bridge die (item 150, Chen) are electrically connected to the second wiring structure (item RDL2, Chen, item 170, Lin), and the second conductive pad (shown but not labeled, Chen, item 118, Lin) of the bridge die (item 150, Chen, item 110, Lin) is in direct contact with the second wiring structure (item RDL2, Chen, item 170, Lin); and a second monolithic molding compound (items E2 or E2 plus UF1, paragraphs 21, 30, both E2 and UF1 can be made of epoxy, thus an integral structure) encapsulating the second electronic component (items 300a or 300) and the third electronic component (items 400a or 400), wherein a lateral surface of the low density wiring structure ((first layer of multilayer item 102, paragraph 15, Chen, items 370 plus 310 plus 320 plus 312, 470 plus 410 plus 420 plus 412, 570 plus 510 plus 520 plus 512, We), a lateral surface of the high density wiring structure (RDL1 or second or more layers of multilayer items 102 with more items 104, paragraph 15), a lateral surface of the first monolithic molding compound (items E1 or E1 plus UF2, paragraphs 21, 30, both E1 and UF2 can be made of epoxy, thus an integral structure, Chen, item 240, Lin), a lateral surface of the second wiring structure (item RDL2, Chen, item 170, Lin) and a lateral surface of the second monolithic molding compound (items E2 or E2 plus UF1, paragraphs 21, 30, both E2 and UF1 can be made of epoxy, thus an integral structure) are coplanar with each other.
In regards to claim 38, Chen (Figs. 4-6, 7B, 7D, 7E, 7F, 7G, 9, 12, 14 and associated text and items) as modified by We (Figs. 3, 4A, 4B, 5N, 5O and associated text and items), and evidenced by or modified by Chen’264 (Figs. 2(d) and associated text) and/or Lin (Fig. 2F) discloses wherein the first electronic component (items 100 or 200, 101 or 201, Chen, item 305, Chen’264) comprises a first bump (item 100e, Chen, item 217, Chen’264, item 117, Lin) and a second bump (item 100e, Chen, item 217, Chen’264, item 117, Lin) disposing (disposed) on the bottom surface of the first electronic component (items 100 or 200, 101 or 201, Chen, item 305, Chen’264, item 117, Lin), and the (first) monolithic molding compound ((items E1 or E1 plus UF2, paragraphs 21, 30, both E1 and UF2 can be made of epoxy, thus an integral structure, Chen, item 113, Chen’264, item 240, Lin) further extends to a space between the first bump (item 100e, Chen, item 217, Chen’264, item 117, Lin) and the second bump (item 100e, Chen, item 217, Chen’264, item 117, Lin), wherein the first bump (item 100e, Chen, item 217, Chen’264, item 117, Lin) is next to the second bump (item 100e, Chen, item 217, Chen’264, item 117, Lin), wherein the solder bump (item 501, Chen) includes a plurality of solders (item 501, Chen), and two of the plurality of solders (item 501, Chen) contact each of the first bump (item 100e, Chen, item 217, Chen’264, item 117, Lin) and a second bump (item 100e, Chen, item 217, Chen’264, item 117, Lin).
In regards to claim 39, Chen does not specifically disclose wherein the first electronic component further comprises a third bump on the bottom surface of the first electronic component, wherein the second bump is next to the third bump, and a first pitch between the first bump and the second bump is different from a second pitch between the second bump and the third bump.
We (Figs. 3-4B, 5J-5L, 5O and associated text) discloses a first electronic component (items 302B, 402B, 502B) further comprises a third bump (items 564 to the far right or far left, not labeled in some figures) on the bottom surface of the first electronic component (items 302B, 402B, 502B), and a first pitch between the first bump (one of items 564 in the middle) and the second bump (the other one of items 564 in the middle) is different from a second pitch between the second bump (the other one of items 564 in the middle) and the third bump (items 564 to the far right or far left ).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of We for the purpose of an electrical connection.
In regards to claim 57, Chen (Figs. 4-6, 7B, 7D, 7E, 7F, 7G, 9, 12, 14 and associated text and items) as modified by We (Figs. 3, 4A, 4B, 5N, 5O and associated text and items), as evidenced by and/or modified by Chen’264 (Figs. 2(d) and associated text) or Lin (Fig. 2F) discloses wherein in a cross-sectional view, the first electronic component (items 100 or 200, 101 or 201) is close to a top surface of the first monolithic molding compound ((items E1 or E1 plus UF2, paragraphs 21, 30, both E1 and UF2 can be made of epoxy, thus an integral structure, Chen, item 113, Chen’264, item 240, Lin), and is far away from a bottom surface of the monolithic molding compound (item E1, Chen, item 113, Chen’264, item 240, Lin), wherein the top surface of the first monolithic molding compound ((items E1 or E1 plus UF2, paragraphs 21, 30, both E1 and UF2 can be made of epoxy, thus an integral structure, Chen, item 113, Chen’264, item 240, Lin) faces the second electronic component (items 300a or 300, 400a or 400), wherein the bottom surface of the first monolithic molding compound ((items E1 or E1 plus UF2, paragraphs 21, 30, both E1 and UF2 can be made of epoxy, thus an integral structure, Chen, item 113, Chen’264, item 240, Lin) is opposite to the top surface of the (first) monolithic molding ((items E1 or E1 plus UF2, paragraphs 21, 30, both E1 and UF2 can be made of epoxy, thus an integral structure, Chen, item 113, Chen’264, item 240, Lin).
In regards to claim 58, Chen (Figs. 4-6, 7B, 7D, 7E, 7F, 7G, 9, 12, 14 and associated text and items) as modified by We (Figs. 3, 4A, 4B, 5N, 5O and associated text and items), as evidenced by and/or modified by Chen’264 (Figs. 2(d) and associated text) or Lin (Fig. 2F) discloses wherein the first monolithic molding compound ((items E1 or E1 plus UF2, paragraphs 21, 30, both E1 and UF2 can be made of epoxy, thus an integral structure, Chen, item 113, Chen’264, item 240, Lin) includes a first portion disposed over the top surface of the first electronic component (items 100 or 200, 101 or 201, Chen, item 305, Chen’264, item 117, Lin) and a second portion disposed under the bottom surface of the first electronic component (items 100 or 200, 101 or 201, Chen, item 305, Chen’264, item 117, Lin), wherein a thickness of the first portion of the first monolithic molding compound ((items E1 or E1 plus UF2, paragraphs 21, 30, both E1 and UF2 can be made of epoxy, thus an integral structure, Chen, item 113, Chen’264, item 240, Lin) is less than a thickness of the first lower portion of the first monolithic molding compound ((items E1 or E1 plus UF2, paragraphs 21, 30, both E1 and UF2 can be made of epoxy, thus an integral structure, Chen, item 113, Chen’264, item 240, Lin).
In regards to claim 59, Chen (Figs. 4-6, 7B, 7D, 7E, 7F, 7G, 9, 12, 14 and associated text and items) as modified by We (Figs. 3, 4A, 4B, 5N, 5O and associated text and items), as evidenced by and/or modified by Chen’264 (Figs. 2(d) and associated text) or Lin (Fig. 2F) discloses a third electronic component (items 300a or 300 or items 400a or 400) disposed side by side with the second electronic component (items 300a or 300 or items 400a or 400); and a bridge die (item 150, Chen, item 110, Lin) disposed under a gap between the second electronic component (items 300a or 300 or items 400a or 400) and the third electronic component (items 300a or 300 or items 400a or 400), and encapsulated by the first monolithic molding compound ((items E1 or E1 plus UF2, paragraphs 21, 30, both E1 and UF2 can be made of epoxy, thus an integral structure, Chen, item 113, Chen’264, item 240, Lin), wherein the first monolithic molding compound ((items E1 or E1 plus UF2, paragraphs 21, 30, both E1 and UF2 can be made of epoxy, thus an integral structure, Chen, item 113, Chen’264, item 240, Lin) further includes a third portion disposed over a top surface of the bridge die (item 150, Chen, item 110, Lin), wherein the top surface of the bridge die (item 150, Chen, item 110, Lin) faces the second electronic component (items 300a or 300 or items 400a or 400), wherein a thickness of the third portion of the first monolithic molding compound ((items E1 or E1 plus UF2, paragraphs 21, 30, both E1 and UF2 can be made of epoxy, thus an integral structure, Chen, item 113, Chen’264, item 240, Lin)is less than the thickness of the second portion of the first monolithic molding compound (item E1, Chen, item 113, Chen’264, item 240, Lin).
In regards to claim 68, Chen (Figs. 4-6, 7B, 7D, 7E, 7F, 7G, 9, 12, 14 and associated text and items) as modified by We (Figs. 3, 4A, 4B, 5N, 5O and associated text and items), as evidenced by and/or modified by Chen’264 (Figs. 2(d) and associated text) or Lin (Fig. 2F) discloses wherein the first electronic component (items 100 or 200, 101 or 201, Chen) has a top surface, a bottom surface opposite to the top surface, and a lateral surface extending between the top surface and the bottom surface; wherein the first monolithic molding compound (items E1 or E1 plus UF2, paragraphs 21, 30, both E1 and UF2 can be made of epoxy, thus an integral structure, Chen, item 113, Chen’264, item 240, Lin) continuously extends along from the lateral surface of the first electronic component (items 100 or 200, 101 or 201, Chen) to the bottom surface of the first electronic component (items 100 or 200, 101 or 201, Chen) and continuously extends to the top surface of the first electronic component (items 100 or 200, 101 or 201, Chen).
In regards to claim 69, Chen (Figs. 4-6, 7B, 7D, 7E, 7F, 7G, 9, 12, 14 and associated text and items) as modified by We (Figs. 3, 4A, 4B, 5N, 5O and associated text and items), as evidenced by and/or modified by Chen’264 (Figs. 2(d) and associated text) or Lin (Fig. 2F) does not specifically disclose wherein a thickness of the core substrate (items 310, 410, 510) of the low density wiring structure (items 212 plus 210) is less than a thickness of the first electronic component (items 100 or 200, 101 or 201, Chen) and a thickness of the second electronic component (items 300 or 400).
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the invention to include a core substrate having a thickness less than the first and second electronic component for the device/package thickness/height, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)). Examiner notes that the Applicant has not given any criticality as to where the difference in thickness yields an advantage or unexpected result.
In regards to claim 70, Chen (Figs. 4-6, 7B, 7D, 7E, 7F, 7G, 9, 12, 14 and associated text and items) discloses as wherein the first electronic component (items 100 or 200, 101 or 201, Chen) further includes a deep trench capacitor (paragraph 20).
In regards to claim 71, Chen (Figs. 4-6, 7B, 7D, 7E, 7F, 7G, 9, 12, 14 and associated text and items) as modified by We (Figs. 3, 4A, 4B, 5N, 5O and associated text and items), Chen’264 and Lin discloses wherein a lateral surface of the solder (item 501, Chen, item 217, Chen’264, shown but not labeled in Lin) includes a convex curved surface.
In regards to claim 73, Chen (Figs. 4-6, 7B, 7D, 7E, 7F, 7G, 9, 12, 14 and associated text and items) as modified by We (Figs. 3, 4A, 4B, 5N, 5O and associated text and items), as evidenced by and/or modified by Chen’264 (Figs. 2(d) and associated text) or Lin (Fig. 2F) discloses wherein a width of the conductive element (item TIV, Chen) is greater than a width of the through via (item 115, Lin) of the bridge die (item 150, Chen, item 110, Lin), wherein the width of the second through via (item 115, Lin) of the bridge die (item 150, Chen, item 110, Lin) is greater than a width of the first conductive via (item TSV1 or TSV2) of the first electronic component (items 100 or 200, 101 or 201, Chen).
In regards to claim 74, Chen (Figs. 4-6, 7B, 7D, 7E, 7F, 7G, 9, 12, 14 and associated text and items) as modified by We (Figs. 3, 4A, 4B, 5N, 5O and associated text and items), as evidenced by and/or modified by Chen’264 (Figs. 2(d) and associated text) or Lin (Fig. 2F) discloses wherein a width of the through via of the low density wiring structure is less than the width of the conductive pillar, and is greater than the width of the through via of the bridge die.
In regards to claim 75, Chen (Figs. 4-6, 7B, 7D, 7E, 7F, 7G, 9, 12, 14 and associated text and items) as modified by We (Figs. 3, 4A, 4B, 5N, 5O and associated text and items), as evidenced by and/or modified by Chen’264 (Figs. 2(d) and associated text) or Lin (Fig. 2F) discloses wherein the first conductive via of the first electronic component vertically overlaps the first through via of the low density wiring structure.
In regards to claim 76, Chen (Figs. 4-6, 7B, 7D, 7E, 7F, 7G, 9, 12, 14 and associated text and items) as modified by We (Figs. 3, 4A, 4B, 5N, 5O and associated text and items), as evidenced by and/or modified by Chen’264 (Figs. 2(d) and associated text) or Lin (Fig. 2F) discloses wherein a thickness of the core substrate is less than a thickness of the bridge die and a thickness of the first electronic component.
In regards to claim 80, Chen (Figs. 4-6, 7B, 7D, 7E, 7F, 7G, 9, 12, 14 and associated text and items) as modified by We (Figs. 3, 4A, 4B, 5N, 5O and associated text and items), as evidenced by and/or modified by Chen’264 (Figs. 2(d) and associated text) or Lin (Fig. 2F) discloses wherein the first electronic component (items 100 or 200, 101 or 201, Chen) further includes a deep trench capacitor (paragraph 20), and wherein a lateral surface of the first solder (item 501) includes a convex curved surface.
In regards to claim 81, Chen (Figs. 4-6, 7B, 7D, 7E, 7F, 7G, 9, 12, 14 and associated text and items) as modified by We (Figs. 3, 4A, 4B, 5N, 5O and associated text and items), as evidenced by and/or modified by Chen’264 (Figs. 2(d) and associated text) or Lin (Fig. 2F) discloses wherein the first monolithic molding compound (items E1 or E1 plus UF2, paragraphs 21, 30, both E1 and UF2 can be made of epoxy, thus an integral structure, Chen, item 113, Chen’264, item 240, Lin) is in direct contact with the first conductive pad (item 117 or 118, Lin) and the second conductive pad (item 117 or 118, Lin) of the bridge die (item 150, Chen, item 110, Lin).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 November 17, 2025