DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification/Drawings
The amendment filed 11/03/2025 is objected to under 35 U.S.C. 132(a) because it introduces new matter into the disclosure. 35 U.S.C. 132(a) states that no amendment shall introduce new matter into the disclosure of the invention. The added material which is not supported by the original disclosure is as follows: the new sheet for Fig. 17 shows a fifth 500 and sixth 600 dielectric that were not previously described. Applicant’s original disclosure lacks a specificity commensurate with the new visual disclosure of Fig. 17. Where and with what the fifth and sixth dielectric layers contact, which underlying layers they overlap, and the presence or absence of intervening layers, all represent the introduction of new matter.
Applicant is required to cancel the new matter in the reply to this Office Action.
Drawings
In view of Applicant’s amendments, the prior drawing objection is withdrawn.
Claim Rejections - 35 USC § 112
In view of Applicant’s amendments, the prior 112(d) rejection is withdrawn.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 9, 12, and 15-17, and 31 are rejected under 35 U.S.C. 103 as being unpatentable over Ponoth et al. (US 2011/0101538), Chambers et al. (US 2004/0259378), Yang et al. (US 2007/0040276) of record, Liu et al. (US 2009/0137119) and Drizlikh et al. (US 7,504,304), all of record, and Ruan et al. (US 2008/0150131) and Dunn et al. (US 2011/0091815), both newly cited.
(Re Claim 9) Ponoth teaches a portion of an interconnect structure for an integrated circuit device, comprising a plurality of dielectric layers and copper metal interconnect features (see abstract, Fig. 5B, ¶42). However, hillocks and the subsequent dielectric and interconnect feature arrangements are not disclosed.
A person having ordinary skill in the art desiring to make or use the interconnect structure of Ponoth would be motivated to look to related art for possible metallization beneath the capping layer 510 and inside the semiconductor structure 501 of Ponoth (Fig. 5B, ¶42), and also for guidance regarding defects caused during the deposition of material layers.
Chambers teaches that when copper is conventionally used to form metal interconnect features in a multilayer dielectric interconnect structure, hillocks will naturally form (Figs. 1A-3D, ¶¶3, 29).
Yang teaches a first copper interconnect structure 201 (Fig. 9) that has a first dielectric layer 204 deposited on it, without planarization before a second dielectric layer 205 is deposited on the first dielectric layer 204 (Fig. 9; ¶¶30-32). A third dielectric layer 901 (Fig. 9, ¶44) is then deposited on the first and second dielectric layers after planarization of the second dielectric layer 205 (¶44). From Chambers, a PHOSITA would recognize that when using copper in the structure, hillocks will naturally form on the first interconnect structure 201 and will transfer the pattern into the first dielectric layer 204 and second dielectric layer 205 of Yang, as taught by Chambers, but because of the planarization step of just the top of 205, the pattern transferred into the second dielectric layer 205 is removed, and so does not transfer also into the third dielectric layer 901 of Yang.
As Ponoth teaches a capping layer 510 over a copper metallization layer (Fig. 5B, ¶42), a PHOSITA would find it obvious to planarize a dielectric layer (501; Fig. 5B) of Ponoth before depositing the layer 510, as taught by Yang, in order to prevent distortions on the surface of the device that would affect further lithographic processing, and so a hillock pattern is retained in the first dielectric layer, but is removed from the tops of subsequent dielectric layers deposited in sequence, allowing for the planar bottom surface of the second interconnect feature (Fig. 5B markup).
Additionally, a PHOSITA would find it obvious to use the metallization layer taught by Yang (Fig. 9) as the interconnect arrangement in the interconnect structure of Ponoth underneath the capping layer 510 in order to form electrical connections with other parts of a device. A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious that, when copper is used as the material for the first interconnect feature, according to Chambers, the first metal interconnect feature will naturally have hillocks, the first dielectric layer will have a localized elevated region overlying the hillock because of pattern transfer into the overlying dielectric layers, and the second metal interconnect feature having a planar bottom surface will overlie the localized elevated region of the first dielectric layer and the hillock of the first metal interconnect feature.
Additionally, Ponoth teaches removing parts of a capping layer (310; Fig. 3C, ¶¶36-37) that are either overlying metallization features (302; Fig. 3C) that are present in another dielectric layer (301; Fig. 3C) or overlying a region (a region overlapping with 313a; Fig. 3C) not having immediately underlying metallization features (Fig. 3C). A PHOSITA would find it obvious to form a second metal interconnect feature next to the metal interconnect feature (512) seen in Fig. 5B of Ponoth that does not overly a metallization feature such as 502 seen in Fig. 5B, as this is an alternative embodiment (compare the trenches and vias of Fig. 3C and 5B) of the openings formed within dielectric and etch stop layers disclosed by Ponoth, wherein a via and an adjacent multilevel trench are formed by etching through a capping layer (“However, selectivity to capping layer 310 is optional and may not be always necessary. For example, in one embodiment, the selective-etching process may etch capping layer 310 as well and therefore may expose conductive stud 302 underneath thereof.”; as the etching depth is determined by opening width, if the capping layer 310 is removed then openings having equal or greater width will have their corresponding portion of the capping layer 310 etched through as well; ¶¶35-37). A reference may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art, including nonpreferred embodiments. Merck & Co. v. Biocraft Labs., Inc. 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir. 1989), cert. denied, 493 U.S. 975 (1989).
Furthermore, Fig. 5B demonstrates etching into the second dielectric such that feature 512 is laterally surrounded by the fourth, third, and a portion of the second dielectric, a person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the second metal interconnect feature to the right of the via 512, as taught by the embodiment shown in Fig. 3C, such that the same or greater punch through is achieved, as the etch depth is determined by an opening width (Ponoth: ¶35). This results in the second metal interconnect feature being laterally surrounded by the fourth, third, and a portion of the second dielectric.
This achieves the predictable result of forming electrical routing within the overall device. See also Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
That modified Ponoth teaches a first, third, and the fifth dielectric layer comprising etch stop layers that are composed of the same material, and the vertical distance as claimed, has yet to be shown.
Liu teaches forming a dielectric layer (28; Fig. 3) using an undoped silicate glass (¶24), and an etch stop layer (26; Fig. 3) formed using silicon nitride (¶24).
A PHOSITA would find it obvious to form the second and fourth dielectric layer using undoped silicate glass as taught by Liu, due to its good thermal stability.
Furthermore, a PHOSITA would find it obvious to use silicon nitride to form the first dielectric layer (Fig. 5B markup of Ponoth), third dielectric layer (Fig. 5B markup of Ponoth), and fifth dielectric layer (520; Fig. 5B markup of Ponoth) using silicon nitride due to its suitability as an etch stop layer for layers of undoped silicate glass (Liu: ¶24).
Ponoth teaches that an etch depth in a material is dependent on the duration of the etch, and the width of the opening due to RIE lag (Fig. 1A, and 7, ¶¶21, 45).
Drizlikh teaches that the “magnitude of RIE lag for a given material can be determined empirically. In addition, for each type of material it is possible to establish a correlation that relates the contact diameter of a contact etch hole, the desired depth of the contact etch hole, and the etch rate through the material.” (col. 5 ln. 59-67 to col. 6 ln. 1-3).
Dunn teaches that an RIE based etch minimized for a smallest feature will cause overetching of all larger feature in feature size dependent degrees (¶30)
As a capping layer of modified Ponoth – corresponding to the third dielectric – may be removed to allow for connections to underlying metal features (Ponoth: ¶42), a PHOSITA would find it obvious to overetch the third dielectric of modified Ponoth in the area of the second and third metal interconnect feature, when the widths of the second and third metal interconnect features are larger than different metal interconnect features at the same depth, in order to ensure that the capping layer overlapping with different metal interconnect features at this depth having a smaller width at this lower level capping layer depth is sufficiently etched through, as due to RIE lag smaller width features will require a longer time to etch (Ponoth: Fig. 1A, 7, ¶22), and it is known that overetching naturally occurs when ensuring that material overlapping with the smallest features is completely removed (Dunn: ¶30, Abstract). Because the etch depth to form openings in the layer underlying the capping layer is the claimed vertical distance; the etchant, etch duration, and the width (Drizlikh: col. 5 ln. 59-67 to col. 6 ln. 1-3; Ponoth: Fig. 7, ¶¶21, 45) of each opening are result effective variables of the etch depth; the etch rate will be faster for wider openings on the lowest level of Ponoth; the openings used to form a second and third metal interconnect feature may be wider than most or all of the other openings formed at the depth of the capping layer (similar to the situation shown in Fig. 3C between 312b and the wider 313b of Ponoth); and the etch depth must be sufficient to etch through each capping layer portion where a connection is required, the claimed vertical distance between a planar bottom surface of the second metal interconnect feature and a bottom surface of the third dielectric layer would have been obvious to optimize and ascertainable through routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Ruan teaches a first width of a hillock (940; Fig. 9, ¶3) is 100 nm or less (the diameter represents either a height or a width; ¶39).
Ponoth teaches that a second width of a second metal interconnect feature may be between 300 nm and about 500 nm (Fig. 7, ¶35).
With Ruan and Ponoth’s width values available, the second width being greater than the first width is obvious in view of the prior art. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976).
With the aforementioned utilization of the structure of Yang by Ponoth, modified Ponoth teaches:
a first metal interconnect feature having a hillock (Yang: 201; Fig. 9, Chambers: hillocks), wherein the hillock has a first width (100 nm or less; Ruan: ¶39);
a first dielectric layer (Yang: 204; Fig. 9);
a second dielectric layer (Ponoth: 501; 205 of Yang, Fig. 9, corresponds with 501 of Ponoth, Fig. 5B) over the first metal interconnect feature (Fig. 5B markup), the first dielectric layer having a localized elevated region overlying the hillock (Fig. 5B markup);
a third dielectric layer (Ponoth: 510; 901 of Yang, Fig. 9, corresponds with 510 of Ponoth, Fig. 5B) over the second dielectric layer (Fig. 5B markup);
a fourth dielectric layer (Ponoth: 511; Fig. 5B markup);
a fifth dielectric layer (Ponoth: 520; Fig. 5B markup)) over the fourth dielectric layer, wherein the first dielectric layer, the third dielectric layer, and the fifth dielectric layer comprise etch stop layers that are composed of the same material (see the rejection above); and
a second metal interconnect feature (Fig. 5B markup) having a planar bottom surface overlying the localized elevated region of the first dielectric layer and the hillock of the first metal interconnect feature (Fig. 5B markup), the second metal interconnect feature laterally surrounded by the fourth dielectric layer, the third dielectric layer, and a portion of the second dielectric layer (Ponoth: Fig. 5B; Fig. 5B markup), and the second dielectric layer and the first dielectric layer extend continuously between the first metal interconnect feature and the planar bottom surface of the second metal interconnect feature (Ponoth: Fig. 5A and 5B; Fig. 5B markup),
such that the second dielectric layer contacts an entirety (Fig. 5B markup) of the planar bottom surface of the second metal interconnect feature overlying the first metal interconnect feature, and a vertical distance between the planar bottom surface of the second metal interconnect feature and a bottom surface of the third dielectric layer is 20% of a total thickness of the second dielectric layer and the third dielectric layer (see the optimization discussion above), wherein the second metal interconnect feature has a second width that is greater than the first width (Ponoth: Fig. 7, ¶35).
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(Re Claim 12) Modified Ponoth teaches the interconnect structure of claim 9, wherein the hillock has at least one of a height and a width dimension of at least 50 nm (Ruan: width of at least 100 nm or less, ¶39).
(Re Claim 15) Modified Ponoth teaches the interconnect structure of claim 9, further comprising a third metal interconnect feature overlying the first metal interconnect feature (522; see Fig. 5B markup). However, modified Ponoth has not explicitly taught the third metal interconnect feature laterally surrounded by the fourth dielectric layer, the third dielectric layer, and a portion of the second dielectric layer, and a conductive via extends between the third metal interconnect feature and the first metal interconnect feature, the conductive via laterally surrounded by the second dielectric layer and the first dielectric layer.
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to make further metal interconnect features extending into the second dielectric layer 501 of Ponoth in order to form more electrical connections with devices in the material. Therefore, a PHOSITA would find it obvious to form a third metal interconnect so as to connect with the underlying via (Leftmost 801+802 metal structure of Yang; Fig. 9) of the metallization of Yang. From Yang, the via 801+802 extends between the third metal interconnect feature (Ponoth: Fig. 5B markup) and the first metal interconnect feature 201 of Yang, and the conductive via is laterally surrounded by the second dielectric layer 501 of Ponoth and the first dielectric layer 204 of Yang (Yang: Fig. 9). Additionally, as the third metal interconnect feature is formed in the same manner as the second metal interconnect, the third metal interconnect feature overlies the first metal interconnect feature 201 of Yang, and is laterally surrounded by the fourth dielectric layer, the third dielectric, and a portion of the second dielectric layer (Fig. 5B markup). Modified Ponoth then teaches the limitations of claim 15 (see Fig. 5B markup).
(Re Claim 16) Modified Ponoth teaches the interconnect structure of claim 15, whereineach of the metal interconnect features comprise a barrier layer and a metallic fill material as is done in standard practice (¶42). Yang also teaches using a conventional barrier layer around each of the metal fill materials in the interconnect structures (e.g. 201 and 803, ¶¶ 25, 27, 42). A PHOSITA would recognize that barrier layers would be employed at each and every metal level throughout the interconnect structure to improve adhesion and prevent diffusion of the copper into the adjacent dielectric layers. This is well-known and standard practice in the art. Modified Ponoth therefore teaches the limitations of claim 16 (The barrier layer is the bold outline defining 512 of the second and third metal interconnect feature of the Fig. 5B markup).
(Re Claim 17) Modified Ponoth teaches the interconnect structure of claim 16, whereinthe barrier layer of the third metal interconnect feature extends over an upper surface of the conductive via (Fig. 5B markup), and wherein an upper surface of the barrier layer is located below a lower surface of the third dielectric layer (Fig. 5B markup).
(Re Claim 31) Modified Ponoth teaches the interconnect structure of claim 9, wherein the vertical distance between the planar bottom surface of the second metal interconnect feature and the bottom surface of the third dielectric layer is 35% or less of the total thickness of the second dielectric layer between the first dielectric layer and the third dielectric layer (see the discussion in the rejection of claim 9 based on optimization).
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Ponoth et al. (US 2011/0101538), Chambers et al. (US 2004/0259378), Yang et al. (US 2007/0040276) of record, Liu et al. (US 2009/0137119) and Drizlikh et al. (US 7,504,304), all of record, and Ruan et al. (US 2008/0150131) and Dunn et al. (US 2011/0091815), both newly cited, as applied to claim 9 above, and further in view of Shimabukuro et al. (US 2020/0006131) of record.
(Re Claim 13) Modified Ponoth teaches the interconnect structure of claim 9, but does not explicitly teach wherein the structure wherein the second dielectric layer and the fourth dielectric layer have a greater thickness than the first dielectric layer, the third dielectric layer, and the fifth dielectric layer.
Yang teaches a suitable thickness for an etch stop layer made of silicon nitride is from about 3 to about 100 nm (¶24). The first, third, and fifth dielectric layer are etch stops formed of silicon nitride.
Shimabukuro teaches forming a dielectric layer (690; Fig. 4) formed of undoped silicate glass with a thickness of 100 nm to 800 nm (¶¶37, 45). The second and fourth dielectric layers are formed of undoped silicate glass.
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form respective material layers having the dimensions found in Shimabukuro and Yang. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976).
(Re Claim 14) Modified Ponoth teaches the interconnect structure of claim 13, and wherein the first dielectric layer, the third dielectric layer, and the fifth dielectric layer comprise silicon nitride (Liu: ¶24), and the second dielectric layer and the fourth dielectric layer comprise undoped silicate glass (Liu: ¶24).
Claims 18-20 and 32 are rejected under 35 U.S.C. 103 as being unpatentable over Ponoth et al. (US 2011/0101538), Chambers et al. (US 2004/0259378), Yang et al. (US 2007/0040276) of record, Liu et al. (US 2009/0137119) and Drizlikh et al. (US 7,504,304), all of record, and Ruan et al. (US 2008/0150131) and Dunn et al. (US 2011/0091815), both newly cited.
(Re Claim 18) Ponoth teaches a portion of an interconnect structure for an integrated circuit device, comprising a plurality of dielectric layers and copper metal interconnect features (Abstract and Fig. 5B, ¶42). Ponoth also teaches each of the metal interconnect features comprise a barrier layer and a metallic fill material as is done in standard practice (¶42). However, hillocks and the subsequent dielectric and interconnect feature arrangements are not taught.
A person having ordinary skill in the art desiring to make or use the interconnect structure of Ponoth would be motivated to look towards related art for possible metallization beneath the capping layer 510 and inside the semiconductor structure 501 of Ponoth (Fig. 5B, ¶42), and also for guidance regarding defects caused during the deposition or etching of material layers.
Chambers teaches that when copper is conventionally used to form metal interconnect features in a multilayer dielectric interconnect structure, hillocks will naturally form (Figs. 1A-3D, ¶¶3, 29).
Yang teaches a first copper interconnect structure 201 that has a first dielectric layer 204 deposited on it, without planarization before a second dielectric layer 205 is deposited on the first dielectric layer 204 (Fig. 9; ¶¶30-32). A third dielectric layer 901 (Fig. 9, ¶44) is then deposited on the first and second dielectric layers after planarization of the second dielectric layer 205 (¶44). Yang also teaches using a conventional barrier layer around each of the metal fill materials in the interconnect structures (e.g. 201 and 803, ¶¶ 25, 27, 42). A PHOSITA would recognize that barrier layers would be employed at each and every metal level throughout the interconnect structure to improve adhesion and prevent diffusion of the copper into the adjacent dielectric layers. This is well-known and standard practice in the art. The barrier layer can be understood as the bold outline defining 512 of the third metal interconnect feature of the Fig. 5B markup. From Chambers, a PHOSITA would recognize that when using copper in the structure, hillocks will naturally form on the first interconnect structure 201 and will transfer the pattern into the first dielectric layer 204 and second dielectric layer 205 of Yang, as taught by Chambers, but because of the planarization step of just the top of 205, the pattern transferred into the second dielectric layer 205 is removed, and so does not transfer also into the third dielectric layer 901 of Yang.
As Ponoth teaches a capping layer 510 (Fig. 5B, ¶42) over a metallization layer 501 (¶42), a PHOSITA would find it obvious to planarize a dielectric layer (501; Fig. 5B) of Ponoth before depositing the layer 510, as taught by Yang, in order to prevent distortions on the surface of the device that would affect further lithographic processing, and so a hillock pattern is retained in the first dielectric layer, but is removed from the tops of subsequent dielectric layers deposited in sequence, allowing for the planar bottom surface of the second interconnect feature (Fig. 5B markup). Additionally, a PHOSITA would find it obvious to use the metallization layer taught by Yang (Fig. 9) as the interconnect arrangement in the interconnect structure of Ponoth underneath the capping layer 510 in order to form electrical connections with other parts of a device.
Additionally, Ponoth teaches removing parts of a capping layer (310; Fig. 3C, ¶¶36-37) that are either overlying metallization features (302; Fig. 3C) that are present in another dielectric layer (301; Fig. 3C) or overlying a region (a region overlapping with 313a; Fig. 3C) not having immediately underlying metallization features (Fig. 3C). A PHOSITA would find it obvious to form a second metal interconnect feature next to the metal interconnect feature (512) seen in Fig. 5B of Ponoth that does not overly a metallization feature such as 502 seen in Fig. 5B, as this is an alternative embodiment (compare the trenches and vias of Fig. 3C and 5B) of the openings formed within dielectric and etch stop layers disclosed by Ponoth, wherein a via and an adjacent multilevel trench are formed by etching through a capping layer (“However, selectivity to capping layer 310 is optional and may not be always necessary. For example, in one embodiment, the selective-etching process may etch capping layer 310 as well and therefore may expose conductive stud 302 underneath thereof.”; as the etching depth is determined by opening width, if the capping layer 310 is removed then openings having equal or greater width will have their corresponding portion of the capping layer 310 etched through as well; ¶¶35-37). A reference may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art, including nonpreferred embodiments. Merck & Co. v. Biocraft Labs., Inc. 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir. 1989), cert. denied, 493 U.S. 975 (1989).
Furthermore, Fig. 5B demonstrates etching into the second dielectric such that feature 512 is laterally surrounded by the fourth, third, and a portion of the second dielectric, a person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the second metal interconnect feature to the right of the via 512, as taught by the embodiment shown in Fig. 3C, such that the same or greater punch through is achieved, as the etch depth is determined by an opening width (Ponoth: ¶35). This results in the second metal interconnect feature being laterally surrounded by the fourth, third, and a portion of the second dielectric.
This achieves the predictable result of forming electrical routing within the overall device. See also Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
Furthermore, a person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to make further metal interconnect features extending into the second dielectric layer 501 of Ponoth in order to form more electrical connections with devices in the material. Therefore, a PHOSITA would find it obvious to form a third metal interconnect so as to connect with the underlying via (Leftmost 801+802 metal structure of Yang; Fig. 9) of the metallization of Yang. From Yang, the via 801+802 extends between the third metal interconnect feature (Ponoth: Fig. 5B markup) and the first metal interconnect feature 201 of Yang, and the conductive via is laterally surrounded by the second dielectric layer 501 of Ponoth and the first dielectric layer 204 of Yang (Yang: Fig. 9). Additionally, as the third metal interconnect feature is formed in the same manner as the second metal interconnect, the third metal interconnect feature overlies the first metal interconnect feature 201 of Yang, and is laterally surrounded by the fourth dielectric layer, the third dielectric, and a portion of the second dielectric layer (Fig. 5B markup).
Additionally, a person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious that, when copper is used as the material for the first interconnect feature, according to Chambers the first metal interconnect feature will naturally have hillocks, the first dielectric layer will have a localized elevated region overlying the hillock because of pattern transfer into the overlying dielectric layers, and the second metal interconnect feature having a planar bottom surface will overlie the localized elevated region of the first dielectric layer and the hillock of the first metal interconnect feature.
That modified Ponoth teaches a first, third, and the fifth dielectric layer comprising etch stop layers that are composed of the same material, the vertical distance, and the vertical offset distance, as claimed, has yet to be shown.
Ponoth teaches that an etch depth in a material is dependent on the duration of the etch, and the width of the opening due to RIE lag (Fig. 1A, and 7, ¶¶21, 45).
Drizlikh teaches that the “magnitude of RIE lag for a given material can be determined empirically. In addition, for each type of material it is possible to establish a correlation that relates the contact diameter of a contact etch hole, the desired depth of the contact etch hole, and the etch rate through the material.” (col. 5 ln. 59-67 to col. 6 ln. 1-3).
Dunn teaches that an RIE based etch minimized for a smallest feature will cause overetching of all larger feature in feature size dependent degrees (¶30)
As a capping layer of modified Ponoth – corresponding to the third dielectric – may be removed to allow for connections to underlying metal features (Ponoth: ¶42), a PHOSITA would find it obvious to overetch the third dielectric of modified Ponoth in the area of the second and third metal interconnect feature, when the widths of the second and third metal interconnect features are larger than different metal interconnect features at the same depth, in order to ensure that the capping layer overlapping with different metal interconnect features at this depth having a smaller width at this lower level capping layer depth is sufficiently etched through, as due to RIE lag smaller width features will require a longer time to etch (Ponoth: Fig. 1A, 7, ¶22), and it is known that overetching naturally occurs when ensuring that material overlapping with the smallest features is completely removed (Dunn: ¶30, Abstract). Because the etch depth to form openings in the layer underlying the capping layer is the claimed vertical distance; the vertical offset distance is the vertical distance less the thickness of the barrier layer; the etchant, etch duration, and the width (Drizlikh: col. 5 ln. 59-67 to col. 6 ln. 1-3; Ponoth: Fig. 7, ¶¶21, 45) of each opening are result effective variables of the etch depth; the etch rate will be faster for wider openings on the lowest level of Ponoth; the openings used to form a second and third metal interconnect feature may be wider than most or all of the other openings formed at the depth of the capping layer (similar to the situation shown in Fig. 3C between 312b and the wider 313b of Ponoth); and the etch depth must be sufficient to etch through each capping layer portion where a connection is required, the claimed vertical distance between a planar bottom surface of the second metal interconnect feature and a bottom surface of the third dielectric layer would have been obvious to optimize and ascertainable through routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Ruan teaches a first width of a hillock (940; Fig. 9, ¶3) is 100 nm or less (the diameter represents either a height or a width; ¶39).
Ponoth teaches that a second width of a second metal interconnect feature may be between 300 nm and about 500 nm (Fig. 7, ¶35).
With Ruan and Ponoth’s width values available, the second width being greater than the first width is obvious in view of the prior art. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976).
Therefore, modified Ponoth teaches:
a first metal interconnect feature having a hillock (Yang: 201; Fig. 9, Chambers: hillocks), wherein the hillock has a first width (100 nm or less; Ruan: ¶39);
a first dielectric layer over the first metal interconnect feature and the hillock (Yang: 204; Fig. 9);
a second dielectric layer over the first dielectric layer (Ponoth: 501; 205 of Yang, Fig. 9, corresponds with 501 of Ponoth, Fig. 5B);
a third dielectric layer (Ponoth: 510; 901 of Yang, Fig. 9, corresponds with 510 of Ponoth, Fig. 5B) over the second dielectric layer;
a fourth dielectric layer (Ponoth: 511; Fig. 5B markup) over the third dielectric layer (Fig. 5B markup);
a fifth dielectric layer (Ponoth: 520; Fig. 5B markup) over the fourth dielectric layer, wherein the first dielectric layer, the third dielectric layer, and the fifth dielectric layer comprise etch stop layers that are composed of the same material (see above discussion about their silicon nitride composition);
a second metal interconnect feature (Fig. 5B markup) above the first metal interconnect feature (Fig. 5B markup) having a planar bottom surface overlying the hillock of the first metal interconnect feature, the second metal interconnect feature laterally surrounded by the fourth dielectric layer, the third dielectric layer, and a portion of the second dielectric layer (Fig. 5B markup), and a portion (this portion is the part of the second dielectric layer that overlaps the part of the planar bottom edge, that does not overlap with 502 from a plan view, on the left as viewed from the Fig. 5B markup) of the second dielectric layer located above the first metal interconnect feature is continually in contact with the planar bottom surface of the second metal interconnect feature over an entire area (all of the lowest surface of the 512 of the second metal interconnect feature; Fig. 5B markup) of the planar bottom surface of the second metal interconnect feature that overlies the first metal interconnect feature and extends between a first edge (left edge as seen from Fig. 5A) and a second edge (right edge as seen from Fig. 5A) of the second metal interconnect feature (as 512 is shown to overhang 502, and 502 is described as a via, then continuous contact is achieved from the first edge to the second edge between the planar bottom surface of the second metal interconnect feature and a portion of the second dielectric layer; Fig. 5A and 5B, ¶42), and a vertical distance between the planar bottom surface of the second metal interconnect feature and a bottom surface of the third dielectric layer is at least 20% of a total thickness of the second dielectric layer between the first dielectric layer and the third dielectric layer (see optimization discussion above), wherein the second metal interconnect feature has a second width that is greater than the first width (Ponoth: Fig. 7, ¶35);
and a third metal interconnect feature (Fig. 5B markup) above the first metal interconnect feature (Fig. 5B markup) and electrically connected to the first metal interconnect feature by a conductive via extending through the first dielectric layer and the second dielectric layer (Yang: Fig. 9; Fig. 5B markup), the third metal interconnect feature laterally surrounded by the fourth dielectric layer, the third dielectric layer, and a portion of the second dielectric layer (The third metal interconnect feature is formed in the same manner as the second metal interconnect feature; Fig. 5B markup), wherein:
the third metal interconnect feature comprises a barrier layer and a metallic fill material (From Ponoth and Yang), a portion of the barrier layer extends between the metallic fill material and an upper surface of the conductive via (Fig. 5B markup), and a vertical offset distance between a bottom surface of the third dielectric layer and an upper surface of the portion of the barrier layer extending over the upper surface of the conductive via is at least about 20% of a total thickness of the second dielectric layer (optimization discussion above) between the first dielectric layer and the third dielectric layer.
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(Re Claim 19) Modified Ponoth teaches the interconnect structure of claim 18, whereinthe barrier layer and the metallic fill material are composed of different materials (¶42), and the barrier layer comprises at least one of TiN, TaN (¶42), W, Ti, and Ta and the metallic fill material comprises at least one Cu (¶42), W, Al, AlCu, AlSiCu, Co, Ru, Mo, Ta, and Ti (also see Yang ¶¶25, 27, 30, 39, 42).
(Re Claim 20) Modified Ponoth teaches the interconnect structure of claim 19, and wherein the first dielectric, the third dielectric layer, and the fifth dielectric layer comprise silicon nitride (Liu: ¶24), and the second dielectric layer and the fourth dielectric layer comprise undoped silicate glass (Liu: ¶24).
(Re Claim 32) Modified Ponoth teaches the interconnect structure of claim 18, wherein the vertical distance between the planar bottom surface of the second metal interconnect feature and the bottom surface of the third dielectric layer is 35% or less of the total thickness of the second dielectric layer between the first dielectric layer and the third dielectric layer (see the discussion in the rejection of claim 18 based on optimization).
Claims 21, 26-27, 29-30, and 33-34 are rejected under 35 U.S.C. 103 as being unpatentable over Ponoth et al. (US 2011/0101538), Chambers et al. (US 2004/0259378), Yang et al. (US 2007/0040276) of record, Liu et al. (US 2009/0137119) and Drizlikh et al. (US 7,504,304), all of record, and Ruan et al. (US 2008/0150131) and Dunn et al. (US 2011/0091815), both newly cited.
(Re Claim 21) Ponoth teaches a portion of an interconnect structure for an integrated circuit device, comprising a plurality of dielectric layers and copper metal interconnect features (see abstract, Fig. 5B, ¶42). However, hillocks and the subsequent dielectric and interconnect feature arrangements are not disclosed.
A person having ordinary skill in the art desiring to make or use the interconnect structure of Ponoth would be motivated to look to related art for possible metallization beneath the capping layer 510 and inside the semiconductor structure 501 of Ponoth (Fig. 5B, ¶42), and also for guidance regarding defects caused during the deposition of material layers.
Chambers teaches that when copper is conventionally used to form metal interconnect features in a multilayer dielectric interconnect structure, hillocks will naturally form (Figs. 1A-3D, ¶¶3, 29).
Yang teaches a first copper interconnect structure 201 (Fig. 9) that has a first dielectric layer 204 (Fig. 9) deposited on it, without planarization before a second dielectric layer 205 is deposited on the first dielectric layer 204 (Fig. 9; ¶¶30-32). A third dielectric layer 901 (Fig. 9, ¶44) is then deposited on the first and second dielectric layers after planarization of the second dielectric layer 205 (¶44). From Chambers, a PHOSITA would recognize that when using copper in the structure, hillocks will naturally form on the first interconnect structure 201 and will transfer the pattern into the first dielectric layer 204 and second dielectric layer 205 of Yang, as taught by Chambers, but because of the planarization step of just the top of 205, the pattern transferred into the second dielectric layer 205 is removed, and so does not transfer also into the third dielectric layer 901 of Yang.
As Ponoth teaches a capping layer 510 (Fig. 5B, ¶42) over a metallization layer 501 (¶42), a PHOSITA would find it obvious to planarize a dielectric layer (501; Fig. 5B) of Ponoth before depositing the layer 510, as taught by Yang, in order to prevent distortions on the surface of the device that would affect further lithographic processing, and so a hillock pattern is retained in the first dielectric layer, but is removed from the tops of subsequent dielectric layers deposited in sequence, allowing for the planar bottom surface of the second interconnect feature (Fig. 5B markup). Additionally, a PHOSITA would find it obvious to use the metallization layer taught by Yang (Fig. 9) as the interconnect arrangement in the interconnect structure of Ponoth underneath the capping layer 510 in order to form electrical connections with other parts of a device.
Additionally, Ponoth teaches removing parts of a capping layer (310; Fig. 3C, ¶¶36-37) that are either overlying metallization features (302; Fig. 3C) that are present in another dielectric layer (301; Fig. 3C) or overlying a region (a region overlapping with 313a; Fig. 3C) not having immediately underlying metallization features (Fig. 3C). A PHOSITA would find it obvious to form a second metal interconnect feature next to the metal interconnect feature (512) seen in Fig. 5B of Ponoth that does not overly a metallization feature such as 502 seen in Fig. 5B, as this is an alternative embodiment (compare the trenches and vias of Fig. 3C and 5B) of the openings formed within dielectric and etch stop layers disclosed by Ponoth, wherein a via and an adjacent multilevel trench are formed by etching through a capping layer (“However, selectivity to capping layer 310 is optional and may not be always necessary. For example, in one embodiment, the selective-etching process may etch capping layer 310 as well and therefore may expose conductive stud 302 underneath thereof.”; as the etching depth is determined by opening width, if the capping layer 310 is removed then openings having equal or greater width will have their corresponding portion of the capping layer 310 etched through as well; ¶¶35-37). A reference may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art, including nonpreferred embodiments. Merck & Co. v. Biocraft Labs., Inc. 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir. 1989), cert. denied, 493 U.S. 975 (1989).
Furthermore, Fig. 5B demonstrates etching into the second dielectric such that feature 512 is laterally surrounded by the fourth, third, and a portion of the second dielectric, a person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the second metal interconnect feature to the right of the via 512, as taught by the embodiment shown in Fig. 3C, such that the same or greater punch through is achieved, as the etch depth is determined by an opening width (Ponoth: ¶35). This results in the second metal interconnect feature being laterally surrounded by the fourth, third, and a portion of the second dielectric.
This achieves the predictable result of forming electrical routing within the overall device. See also Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
Additionally, a person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious that, when copper is used as the material for the first interconnect feature, according to Chambers the first metal interconnect feature will naturally have a hillock, the first dielectric layer will have a localized elevated region overlying the hillock because of pattern transfer into the overlying dielectric layers, and the second metal interconnect feature having a planar bottom surface will overlie the localized elevated region of the first dielectric layer and the hillock of the first metal interconnect feature.
That modified Ponoth teaches a first, third, and the fifth dielectric layer comprising etch stop layers that are composed of a first material that is different from a material of a second dielectric layer, fourth dielectric layer, and a sixth dielectric layer, and the vertical distance as claimed, has yet to be shown.
Liu teaches forming a dielectric layer (28; Fig. 3) using an undoped silicate glass (¶24), and an etch stop layer (26; Fig. 3) formed using silicon nitride (¶24).
A PHOSITA would find it obvious to form the second and fourth dielectric layer using undoped silicate glass as taught by Liu, due to its good thermal stability.
Furthermore, a PHOSITA would find it obvious to use silicon nitride to form the first dielectric layer (Fig. 5B markup of Ponoth), third dielectric layer (Fig. 5B markup of Ponoth), and fifth dielectric layer (520; Fig. 5B markup of Ponoth) using silicon nitride due to its suitability as an etch stop layer for layers of undoped silicate glass (Liu: ¶24).
Ponoth teaches that an etch depth in a material is dependent on the duration of the etch, and the width of the opening due to RIE lag (Fig. 1A, and 7, ¶¶21, 45).
Drizlikh teaches that the “magnitude of RIE lag for a given material can be determined empirically. In addition, for each type of material it is possible to establish a correlation that relates the contact diameter of a contact etch hole, the desired depth of the contact etch hole, and the etch rate through the material.” (col. 5 ln. 59-67 to col. 6 ln. 1-3).
Dunn teaches that an RIE based etch minimized for a smallest feature will cause overetching of all larger feature in feature size dependent degrees (¶30).
As a capping layer of modified Ponoth – corresponding to the third dielectric – may be removed to allow for connections to underlying metal features (Ponoth: ¶42), a PHOSITA would find it obvious to overetch the third dielectric of modified Ponoth in the area of the second and third metal interconnect feature, when the widths of the second and third metal interconnect features are larger than different metal interconnect features at the same depth, in order to ensure that the capping layer overlapping with different metal interconnect features at this depth having a smaller width at this lower level capping layer depth is sufficiently etched through, as due to RIE lag smaller width features will require a longer time to etch (Ponoth: Fig. 1A, 7, ¶22), and it is known that overetching naturally occurs when ensuring that material overlapping with the smallest features is completely removed (Dunn: ¶30, Abstract). Because the etch depth to form openings in the layer underlying the capping layer is the claimed vertical distance; the etchant, etch duration, and the width (Drizlikh: col. 5 ln. 59-67 to col. 6 ln. 1-3; Ponoth: Fig. 7, ¶¶21, 45) of each opening are result effective variables of the etch depth; the etch rate will be faster for wider openings on the lowest level of Ponoth; the openings used to form a second and third metal interconnect feature may be wider than most or all of the other openings formed at the depth of the capping layer (similar to the situation shown in Fig. 3C between 312b and the wider 313b of Ponoth); and the etch depth must be sufficient to etch through each capping layer portion where a connection is required, the claimed vertical distance between a planar bottom surface of the second metal interconnect feature and a bottom surface of the third dielectric layer would have been obvious to optimize and ascertainable through routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Ruan teaches a first width of a hillock (940; Fig. 9, ¶3) is 100 nm or less (the diameter represents either a height or a width; ¶39).
Ponoth teaches that a second width of a second metal interconnect feature may be between 300 nm and about 500 nm (Fig. 7, ¶35).
With Ruan and Ponoth’s width values available, the second width being greater than the first width is obvious in view of the prior art. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976).
Therefore, modified Ponoth teaches an interconnect structure for an integrated circuit device, comprising:
a first metal interconnect feature (Yang: 201; Fig. 9) having a hillock, wherein the hillock has a first width (Ruan: 100 nm or less; ¶39);a first dielectric layer (Yang: 204; Fig. 9) over the first metal interconnect feature, the first dielectric layer having a localized elevated region overlying the hillock;a second dielectric layer (Ponoth: 501; 205 of Yang, Fig. 9, corresponds with 501 of Ponoth, Fig. 5B; Fig. 5B markup) over the first dielectric layer;a third dielectric layer (Ponoth: 510; 901 of Yang, Fig. 9, corresponds with 510 of Ponoth, Fig. 5B) over the second dielectric layer;
a fourth dielectric (Ponoth: 511; Fig. 5B markup) layer over the third dielectric;
a fifth dielectric layer (Ponoth: 520; Fig. 5B markup) over the fourth dielectric layer;
a sixth dielectric layer (Ponoth: 521; Fig. 5B markup) over the fifth dielectric layer, wherein the first dielectric layer, the third dielectric layer, and the fifth dielectric layer comprise etch stop layers that are composed of a first material (silicon nitride; Liu: ¶24) that is different from a material (undoped silicate glass; Liu: ¶24) of the second dielectric layer, the fourth dielectric layer, and the sixth dielectric layer; anda second metal interconnect feature (Fig. 5B markup) having a planar bottom surface overlying the localized elevated region of the first dielectric layer and the hillock of the first metal interconnect feature, the second metal interconnect feature is laterally surrounded by the third dielectric layer and a portion of the second dielectric layer (Fig. 5B markup), and a vertical distance between the planar bottom surface of the second metal interconnect feature and a bottom surface of the third dielectric layer is at least about 20% of a total thickness of the second dielectric layer between the first dielectric layer and the third dielectric layer (optimization argument above), and the second dielectric layer continuously contacts the planar bottom surface of the second metal interconnect feature over an entirety (Fig. 5B mark) of the second metal interconnect feature that overlies the first metal interconnect feature, wherein the second metal interconnect feature has a second width that is greater than the first width (Ponoth: Fig. 7, ¶35).
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(Re Claim 26) Modified Ponoth teaches the interconnect structure of claim 21, further comprising:
a third metal interconnect feature (522; Fig. 5B) overlying the first metal interconnect feature (Fig. 5B markup). However, modified Ponoth has not explicitly taught the third metal interconnect feature laterally surrounded by the fourth dielectric layer, the third dielectric layer, and a portion of the second dielectric layer, and a conductive via extends between the third metal interconnect feature and the first metal interconnect feature, the conductive via laterally surrounded by the second dielectric layer and the first dielectric layer.
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to make further metal interconnect features extending into the second dielectric layer 501 of Ponoth in order to form more electrical connections with devices in the material. Therefore, a PHOSITA would find it obvious to form a third metal interconnect so as to connect with the underlying via (Leftmost 801+802 metal structure of Yang; Fig. 9) of the metallization of Yang. From Yang, the via 801+802 extends between the third metal interconnect feature (Ponoth: Fig. 5B markup) and the first metal interconnect feature 201 of Yang, and the conductive via is laterally surrounded by the second dielectric layer 501 of Ponoth and the first dielectric layer 204 of Yang (Yang: Fig. 9). Additionally, as the third metal interconnect feature is formed in the same manner as the second metal interconnect, the third metal interconnect feature overlies the first metal interconnect feature 201 of Yang, and is laterally surrounded by the fourth dielectric layer, the third dielectric, and a portion of the second dielectric layer (Fig. 5B markup). Modified Ponoth then teaches the limitations of claim 26 (see Fig. 5B markup).
(Re Claim 27) Modified Ponoth teaches the interconnect structure of claim 26, whereineach of the metal interconnect features comprise a barrier layer and a metallic fill material as is done in standard practice (¶42). Yang also teaches using a conventional barrier layer around each of the metal fill materials in the interconnect structures (e.g. 201 and 803, ¶¶ 25, 27, 42). A PHOSITA would recognize that barrier layers would be employed at each and every metal level throughout the interconnect structure to improve adhesion and prevent diffusion of the copper into the adjacent dielectric layers. This is well-known and standard practice in the art. Modified Ponoth therefore teaches the limitations of claim 16 (The barrier layer is the bold outline defining 512 of the second and third metal interconnect feature of the Fig. 5B markup).
(Re Claim 29) Modified Ponoth teaches the interconnect structure of claim 21, wherein the second dielectric layer continuously contacts the planar bottom surface of the second metal interconnect feature between a first edge edge (Left edge of 512 as seen in Fig. 5A) and a second edge (Right edge 512 as seen in Fig. 5A) of the second metal interconnect feature (Fig. 5B markup).
(Re Claim 30) Modified Ponoth teaches the interconnect structure of claim 21, wherein a thickness of a region of the second dielectric layer located between the first metal interconnect feature and the planar bottom surface of the second metal interconnect feature varies by at least 50 nm (Ruan: the height of the hillock is 100 nm or less; ¶39).
(Re Claim 33) Modified Ponoth teaches the interconnect structure of claim 21, wherein the vertical distance between the planar bottom surface of the second metal interconnect feature and the bottom surface of the third dielectric layer is 35% or less of the total thickness of the second dielectric layer between the first dielectric layer and the third dielectric layer (see the discussion in the rejection of claim 21 based on optimization).
(Re Claim 34) Modified Ponoth teaches the interconnect structure of claim 21, wherein the first dielectric layer, the third dielectric layer, and the fifth dielectric layer comprise silicon nitride (Liu: ¶24).
Claims 23 are rejected under 35 U.S.C. 103 as being unpatentable over Ponoth et al. (US 2011/0101538), Chambers et al. (US 2004/0259378), Yang et al. (US 2007/0040276) of record, Liu et al. (US 2009/0137119) and Drizlikh et al. (US 7,504,304), all of record, and Ruan et al. (US 2008/0150131) and Dunn et al. (US 2011/0091815), both newly cited, as applied to claim 21 above, and further in view of Shimabukuro et al. (US 2020/0006131) of record.
(Re Claim 23) Modified Ponoth teaches the interconnect structure of claim 22, but does not explicitly teach the interconnect structure whereinthe total thickness of the second dielectric layer is greater than a thickness of the first dielectric layer between the first metal interconnect feature and the second dielectric layer.
Yang teaches a suitable thickness for an etch stop layer made of silicon nitride is from about 3 to about 100 nm (¶24). The first dielectric layer is an etch stop layer formed of silicon nitride.
Shimabukuro teaches forming a dielectric layer (690; Fig. 4) formed of undoped silicate glass with a thickness of 100 nm to 800 nm (¶¶37, 45). The second dielectric layer is formed of undoped silicate glass.
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to have form respective material layers as found in Shimabukuro and Yang. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976).
Response to Arguments
Applicant’s arguments, filed 11/3/2025, have been fully considered but they are not persuasive.
Reply: Extending the Opening Through the Capping Layer to a Depth of 20% or More of the Total Thickness of the Underlying Layer Would Render Ponoth Unsuitable for its Intended Purpose When the Capping layer and the Etch-Stop Layer(s) are Composed of the same Material (remarks, p. 15).
Applicant interprets Ponoth as requiring significant punch-through into dielectric layers overlapping with openings have a small dimension whenever significant punch-through occurs for openings meant to go through the capping layer (remarks, p. 16). However, Ponoth explicitly teaches that the etch rate in a nonselective RIE process is determined by the opening width (Ponoth: Fig. 1A-4C, and 7, ¶¶21-22), and so it cannot be said that where punch-through occurs for openings having the largest widths, significant punch-through also occurs for those have the smallest, as any overetch of etch layers above the capping layer will necessarily be less than that through the capping layer (Ponoth: ¶¶21-22). The overetching of the proposed modification for Ponoth is performed only for openings that are larger than those above the etch stop 520 (Ponoth: Fig. 3C and 5B). Note that Ponoth provides a sample nonselective etch where the etch amount of the largest openings are about 37% greater than the smallest openings (Fig. 7).
Furthermore, the thickness of the underlying layer – 205 of Yang – is not necessarily so much larger than the capping layer of Ponoth that a considerable overetch of 20% or more of the thickness would result in substantial removal of etch stop layers at depths above the capping layer. Yang actually considers a dielectric layer beneath a capping layer that has a thickness of 50 nm (Yang: ¶24). This is less than the maximum thickness of 100 nm of the capping layer as disclosed by Ponoth (¶30), and the etch stop layers remain or else suffer an etch through that is acceptable during the normal course of removing the capping layer (Ponoth: ¶37), as these smaller openings have slower etch rates.
The difference in etch rate between openings of different sizes can be dramatically different (Ponoth: Fig. 7), and Ponoth’s disclosure brings every opening above a size threshold to the capping layer depth, while keeping every opening below a size threshold above an etch stop layer overlying the capping layer. This means that when the capping layer and the etch stop layers of Ponoth are the same material, the etch stop layers will be removed after full removal of the capping layer for every opening at the deeper capping layer depth, and significant over etch into the underlying second dielectric may occur in the regions of the openings of greatest width, while only a small amount of overetch may occur in other opening regions according to their different widths (Ponoth: ¶37).
Applicant has also not provided evidence that the smaller amount of etching within smaller openings will result in an unacceptable etch depth as understood by Ponoth.
Applicant also characterizes the depths as arbitrary (remarks, p. 17) but Ponoth (Fig. 1A and 7, e.g., ¶¶21, 25, 39, 45) and Drizlikh (e.g., col. 5 ln. 59-67 to col. 6 ln. 1-3) together teach that the etch depth in any material is a known function of the material etch rate, the size of openings, and the duration of the etch. As these factors are result-effective variables producing a known outcome, a person having ordinary skill in the art before the effective filing date of the claimed invention would be motivated to explore the etch depth of the openings of Ponoth when a suitable design need arises ( “after KSR, the presence of a known result-effective variable would be one, but not the only, motivation for a person of ordinary skill in the art to experiment to reach another workable product or process”; MPEP 2144.05(II)(B)). The existence of a result-effective variable is enough to motivate one of ordinary skill to form the interconnect structure with the claimed vertical distance.
That there are identified result effective variables known to be manipulated to achieve an overetch amount renders the claimed vertical distance as defined in the claims and discussed in the rejections above obvious to optimize and ascertainable through routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) After KSR, the presence of a known result-effective variable would be one motivation for a person of ordinary skill in the art to experiment to reach another workable product or process. See MPEP 2144.05(II)(B).
Applicant has yet to demonstrate the criticality of their claimed vertical distance (remarks, p. 19). No results are present in the disclosure or presented in arguments to show that the claimed vertical distance produces unexpected results. To establish unexpected results over a claimed range, applicants should compare a sufficient number of tests both inside and outside the claimed range to show the criticality of the claimed range. In re Hill, 284 F.2d 955, 128 USPQ 197 (CCPA 1960). Also, both the art and the Applicant recognize that an overetch is the result of performing an etch targeted to clear areas of slowest etch rate (Dunn: “a minimized etching process which is sufficient to complete etching of the smallest feature to be produced will cause overetching of all larger features in feature size dependent varying degrees.”; ¶30).
Ponoth discloses that a final etch to remove the capping layer may be performed to allow for electrical connections to be made with underlying devices (¶¶37, 42). However, when removal of the capping layer is required for openings having different widths, as disclosed by Ponoth and Drizlikh, etch rate will vary according to the width of each opening. With the RIE lag of Ponoth, wider openings will etch faster, resulting in an overetch into the underlying dielectric layer (in this case 501 of Fig. 5B of Ponoth that corresponds to 205 of Yang) when the capping layer is to be removed for openings having smaller widths present at the depth of the capping layer.
Even if an over etch that guarantees removal of the capping layer of Ponoth is so great as to ruin Ponoth’s purpose of bringing each via or trench to a predetermined level (¶43), Ponoth teaches that such devices are known in the art; they are just more difficult to work with, and require increased device thickness (¶25). Drizlikh explicitly teaches adjusting the location of interconnects within a dielectric layer to compensate for RIE lag (Fig. 3 and 4, col. 5 ln. 59-67 to col. 6 ln. 1-3).
Furthermore, it is not the case that such a configuration would necessarily break the operation of the device of modified Ponoth. Unsuitability is synonymous with inoperable, not less effective or changed (remarks, p. 18). That a proposed modification alters a reference to forego the benefits taught by it does not alone render a device unsuitable for purpose. See In re Urbanski, 809 F.3d 1237, 1244, 117 USPQ2d 1499, 1504 (Fed. Cir. 2016) (The patent claims were directed to a method of enzymatic hydrolysis of soy fiber to reduce water holding capacity, requiring reacting the soy fiber and enzyme in water for about 60-120 minutes. The claims were rejected over two prior art references, wherein the primary reference taught using a longer reaction time of 5 to 72 hours and the secondary reference taught using a reaction time of 100 to 240 minutes, preferably 120 minutes. The applicant argued that modifying the primary reference in the manner suggested by the secondary reference would forego the benefits taught by the primary reference, thereby teaching away from the combination. The court held that both prior art references "suggest[ed] that hydrolysis time may be adjusted to achieve different fiber properties. Nothing in the prior art teaches that the proposed modification would have resulted in an ‘inoperable’ process or a dietary fiber product with undesirable properties." (emphasis in original)).
Should the proposed modification of Ponoth result in greatly over etching through the etch stop layers of the narrowest openings in pursuit of fully etching through the capping layer in the region of the widest openings, thereby causing Ponoth to lack the full depth precision of the unmodified disclosure, the modification would still allow for greater depth control of the openings during the etch process leading up to capping layer removal, than if no etch stop layers were taken advantage of during the process at all. Compensation techniques for depth differences due to RIE lag is also known in the art as discussed above (Ponoth: ¶25; Drizlikh: Fig. 1 and Fig. 4, col. 5 ln. 43-46). Furthermore, the disclosure of desirable alternatives, in this case forming trenches and vias of Ponoth at discrete depths, does not necessarily negate a suggestion for modifying the prior art to arrive at the claimed invention. In In re Fulton, 391 F.3d 1195, 73 USPQ2d 1141 (Fed. Cir. 2004), the claims of a utility patent application were directed to a shoe sole with increased traction having hexagonal projections in a "facing orientation." 391 F.3d at 1196-97, 73 USPQ2d at 1142. The Board combined a design patent having hexagonal projections in a facing orientation with a utility patent having other limitations of the independent claim. 391 F.3d at 1199, 73 USPQ2d at 1144. Applicant argued that the combination was improper because (1) the prior art did not suggest having the hexagonal projections in a facing (as opposed to a "pointing") orientation was the "most desirable" configuration for the projections, and (2) the prior art "taught away" by showing desirability of the "pointing orientation." 391 F.3d at 1200-01, 73 USPQ2d at 1145-46. The court stated that "the prior art’s mere disclosure of more than one alternative does not constitute a teaching away from any of these alternatives because such disclosure does not criticize, discredit, or otherwise discourage the solution claimed…." Id. In affirming the Board’s obviousness rejection, the court held that the prior art as a whole suggested the desirability of the combination of shoe sole limitations claimed, thus providing a motivation to combine, which need not be supported by a finding that the prior art suggested that the combination claimed by the applicant was the preferred, or most desirable combination over the other alternatives. Id. See also In re Urbanski, 809 F.3d 1237, 1244, 117 USPQ2d 1499, 1504 (Fed. Cir. 2016)
Ponoth explicitly teaches removing a capping layer to provide for an electrical connection between device layers (Ponoth: ¶37). That this may also completely remove an etch stop layer above the capping layer during a nonselective etch is only possible if the nonselective etch on the capping layer is performed such that it overetches the capping layer before any other etch stop layers, as all openings which expose the capping layer are wider than those that do not (Ponoth: Fig. 5B, ¶43). A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to look to the art to determine a suitable overetch depth, or at least what parameters affect it. That an overetch occurs in Ponoth is a teaching of Ponoth. The question for one of ordinary skill in the art then is to what depth should the etch be made. As an over etch in Ponoth is accomplished to some end without modification (Fig. 5B), etching further to produce a vertical distance range as claimed is only a difference of degree between the art and the claimed invention, rather than in kind. The effect produced by etching longer is that a deeper opening is made. See In re Williams, 36 F.2d 436, 438, 4 USPQ 237 (CCPA 1929) ("It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions.").
Arguments relying on the relative depicted sizes of underlying dielectric layers are unpersuasive (remarks, p. 17) as neither Ponoth nor Yang have figures that can be relied upon to show accurate proportions (Ponoth: ¶18; Yang: ¶19).
The remainder of Applicant’s arguments are moot.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chao et al. (US 5,780,315) teaches that it is known to optimize the overetch time according to pattern density (col. 1 ln. 65-67 to col. 2 ln. 1-3, col. 2 ln. 65-67 to col. 3 ln. 1-10).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CHRISTOPHER A. SCHODDE/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898