DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1, 8-9, 11, 12, 27-32 amended and previously presented. Claims 10, 13, 14, 21-26 withdrawn. Claims 2-7,15-20 are canceled.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 27-28 are rejected under 35 U.S.C. 103 as being unpatentable over Han et al (U.S. 2021/0175253) and Choi (U.S. 2012/0045904).
Regarding claim 1. Han et al discloses A semiconductor memory structure (FIG. 1-3, item 1), comprising:
a first isolation layer (FIG. 1, item 132b) formed over a substrate (FIG. 1, item 101), a gate layer (FIG. 1, item 122b) formed over the first isolation layer (FIG. 1, item 132b) in a cross-sectional view (FIG. 1), and a second isolation layer (FIG. 1, item 132c) formed over the gate layer (FIG. 1, item 122b), wherein the cross-sectional view (FIG. 1 and 3, item Z) is along a plane (FIG. 1 and 3, item Z; [0048]) perpendicular to a top surface (FIG. 1 and 3, item X) of the substrate (FIG. 1, item 101);
a ferroelectric layer (FIG. 1 and 3, item 312) formed over (FIG. 1, item S1) the second isolation layer (FIG. 1 and 3, item 132c) and along a sidewall (FIG. 1, item S1) of the first isolation layer (FIG. 1 and 3, item 132b), the gate layer (FIG. 1 and 3, item 132b), and the second isolation layer (FIG. 1 and 3, item 132c) in the cross-sectional view (FIG. 1 and 3)
a channel layer (FIG. 1 and 3, item 322) disposed along a sidewall (FIG. 1, item S2) of the ferroelectric layer (FIG. 1 and 3, item 312);
a cap layer (FIG. 1 and 3, item 26) having a first sidewall (FIG. 1 and 2, item S3) interfacing ([0040]) and extending along a sidewall ([0040]) of the channel layer (FIG. 1 and 3, item 322) in the cross-sectional view (FIG. 1 and 3, item Z), wherein the first sidewall extends vertically ([0040], i.e. structure 26 extending in a first direction (i.e., the z-direction)) in the cross-sectional view (FIG. 1 and 3, item Z) and wherein in a top view (FIG. 1 and 2) the cap layer (FIG. 1 and 2, item 26) includes a first terminal end (FIG. 1 and 2, item 24), a second terminal end (FIG. 1 and 2, item 22), a first edge (FIG. 1 and 2, item S3) extending ([0053]) between the first terminal end (FIG. 1 and 2, item 24) and the second terminal end (FIG. 1 and 2, item 22) and a second edge (FIG. 1 and 2, item S4) extending between ([0057]) the first terminal (FIG. 1 and 2, item 24) end and the second terminal end (FIG. 1 and 2, item 22), the second edge (FIG. 1 and 2, item S4) opposing ([0053]; [0057]) the first edge (FIG. 1 and 2, item S3), wherein the first edge (FIG. 1 and 2, item S3) is an uppermost point ([0053]) of the first sidewall (FIG. 1 and 2, item S3) of the cap layer (FIG. 1 and 2, item 26), and wherein the top view (FIG. 1 and 2, item x and y) is along a plane (FIG. 1 and 2, item x and y) parallel to the top surface of the substrate (FIG. 1 and 3, item 101) and perpendicular (FIG. 1 and 3, item Z) to the to the cross-sectional view (FIG. 1 and 3, item Z).
a source structure (FIG. 1 and 2, item 22) and a drain structure (FIG. 1 and 2, item 24) along the channel layer (FIG. 1 and 2, item 322) in the top view (FIG. 1 and 2);
Han et al fails to explicitly disclose an isolation structure disposed between the source structure and the drain structure, wherein the isolation structure interfaces a first portion of the second edge of the cap layer, wherein a portion of the source structure interfaces a second portion of the second edge of the cap layer and the first terminal end of the cap layer.
However, Choi teaches an isolation structure (FIG. 1, item 112) disposed between ([0022]) the source structure (FIG. 1, item 110) and the drain structure (FIG. 1, item 110)
wherein the isolation structure (FIG. 1, item 112) interfaces a first portion (FIG. 1, item first portion) of the second edge (FIG. 1, item second sidewall) of the cap layer (FIG. 1, item 114)
wherein a portion (FIG. 1, item second portion) of the source structure (FIG. 1, item 110) interfaces a second portion (FIG. 1, item second portion) of the second edge (FIG. 1, item second sidewall) of the cap layer (FIG. 1, item 114) and the first terminal end (FIG. 1, item first terminal end) of the cap laver (FIG. 1, item 114).
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Since Both Han et al and Choi teach forming channel layers, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor memory structure as disclosed to modify Han et al with the teachings of the an isolation structure disposed between the source structure and the drain structure, wherein the isolation structure interfaces a first portion of the second edge of the cap layer, wherein a portion of the source structure interfaces a second portion of the second edge of the cap layer and the first terminal end of the cap layer as disclosed by Choi. The use of an etch stop layer formed on the active layer in provides for etching process is performed to form a channel in the source-drain metal electrode layer utilizing the underlying etch stop layer as a blocking layer for preventing over etching to the underlying active layer (Choi, [0022]).
Regarding claim 27. Han et al and Choi discloses all the limitations of the semiconductor memory structure of claim 1 above.
Choi et al further discloses wherein an entirety of the second edge (FIG. 1. Item second sidewall) extending between the first terminal end (FIG. 1, item first terminal end) and the second terminal end (FIG. 1, item second terminal end) of the cap layer (FIG. 1, item 114) is defined by the first portion (FIG. 1, item first portion) and the second portion (FIG. 1, item second portion).
Regarding claim 28. Han et al and Choi discloses all the limitations of the semiconductor memory structure of claim 1 above.
Choi further discloses wherein the second terminal end (FIG. 1, item second terminal end) of the cap layer (FIG. 1, item 114) interfaces the drain structure (FIG. 1, item 110).
Regarding claim 29. Han et al and Choi discloses all the limitations of the semiconductor memory structure of claim 28 above.
Choi further discloses wherein in the top view the second terminal end (FIG. 1, item first terminal end) of the cap layer (FIG. 1, item 114) is collinear ([0021], i.e. an etch stop layer 114 may be formed on the active layer 108; [0022], i.e. a passivation layer 112 is then formed over the source-drain metal electrode layer 110 covering the etch stop layer 114 to complete the process of forming the thin film transistor device 150) with the isolation structure (FIG. 1, item 112).
Claims 30-32 are rejected under 35 U.S.C. 103 as being unpatentable over Han et al (U.S. 2021/0175253) and Choi (U.S. 2012/0045904) as applied to claim 1 above, and further in view of Okumoto et al. (U.S. 2013/0328034)
Regarding claim 30. Han et al and Choi discloses all the limitations of the semiconductor memory structure of claim 1 above.
Han et al and Choi fail to explicitly disclose wherein a length of the source structure in a first direction in the top view is greater than a length of the drain structure in the first direction in the top view.
However, Okumoto teaches wherein a length (FIG. 10B, length of item 5514a) of the source structure (FIG. 10B, item 5514a) in a first direction (FIG. 10B, item Y) in the top view (FIG. 10B, [0232], i.e. a source electrode 5514a and a drain electrode 5514c are disposed) is greater (FIG. 10 shows a length of item 5514a is greater than a length of item 5514c) than a length (FIG. 10B, length of item 5514c) of the drain structure (FIG. 10B, item 5514c) in the first direction (FIG. 10B, item Y) in the top view (FIG. 10B, [0232]).
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Since Han et al, Choi and Okumoto et al teach source structures, it would have been obvious to one having ordinary skill in the art of semiconductors art at the time of the effective filling date of the effective filing date of the claimed invention to have combined the source structure as disclosed to modify Han et al and Choi with the teachings of the wherein a length of the source structure in a first direction in the top view is greater than a length of the drain structure in the first direction in the top view as disclosed by Okumoto et al. The use of the shape of a surface of semiconductor ink applied with respect to the aperture is controlled in Okumoto et al provides for preventing of blending of semiconductor ink with respect to an adjacent aperture (Okumoto et al, [0233]).
Regarding claim 31. Han et al, Choi and Okumoto discloses all the limitations of the semiconductor memory structure of claim 30 above.
Okumoto et al further discloses wherein a width (FIG. 10B, width at first point) of the source structure (FIG. 10B, item 5514a) in the top view (FIG. 10B, [0232]) at a first point (FIG. 10B, item first point) is less than (FIG. 10B shows a width at first point is less than width at the second point) a width (FIG. 10B, width at second point) of the source structure (FIG. 10B, item 5514a) in the top view at a second point (FIG. 10B, second point), the widths (FIG. 10B, width at first and second point) measured in a second direction (FIG. 10B, item X) perpendicular to the first direction (FIG. 10B, item Y).
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Regarding claim 32. Han et al, Choi, and Okumoto et al discloses all the limitations of the semiconductor memory structure of claim 31 above.
Okumoto et al further discloses wherein a width (FIG. 10B, width at second point) of the drain structure (FIG. 10B, item 5514c) measured in the top view (FIG. 10B, [0232]) in the second direction (FIG. 10B, item X) is approximately equal (FIG. 10B shows a width of item 5514c is approximately equal to the width of item 5514a at the second point) to the width (FIG. 10B, width at second point) of the source structure (FIG. 10B, item 5514a) at the second point (FIG. 10B, width at second point).
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Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Han et al (U.S. 2021/0175253), Tseng et al (U.S. 2014/0252477) and Okumoto et al. (U.S. 2013/0334513).
Regarding claim 8. Han et al discloses an semiconductor memory structure (FIG. 1, item 1), comprising: a first gate layer (FIG. 1, item 122a-d) and a second gate layer (FIG. 1, item 124a-d) disposed over a substrate (FIG. 1, item 101), wherein each of the first gate layer (FIG. 1, item S1 of item 122a-d) and second gate layer (FIG. 1, item S6 of item 124a-d) have a sidewall facing one another (FIG. 1, items S1 and S6 face one another);
a ferroelectric layer (FIG. 1, item 312 and 314) wherein the ferroelectric layer (FIG. 1, item 312 and 314) includes a ferroelectric layer portion (FIG. 1, item 312) disposed along each of the sidewall (FIG. 1, item S1) of the first gate layer (FIG. 1, item 122a-d) and a second ferroelectric portion (FIG. 1, item 314) disposed along the sidewall (FIG. 1, item S6) of the second gate layer (FIG. 1, item 124a-d);
a channel layer (FIG. 1, item 322 and 324), wherein the channel layer (FIG. 1, item 322 and 324) includes a first portion (FIG. 1, item 322) of the channel layer (FIG. 1, item 322 and 324) formed along a sidewall (FIG. 1, item S2) of the first ferroelectric layer portion (FIG. 1, item 312) and a second portion (FIG. 1, item 324) of the channel layer (FIG. 1, item 322 and 324) formed along a sidewall (FIG. 1, item S5) of the second ferroelectric portion (FIG. 1, item 314)
an isolation layer (FIG. 1, item 26 isolation structure) disposed between (FIG. 1, item S3 and S4) the first portion (FIG. 1, item 322) of the channel layer (FIG. 1, item 322 and 324) and the second portion (FIG. 1, item 324) of the channel layers (FIG. 1, item 322 and 324) in a top view (FIG. 1) wherein the isolation layer (FIG. 1, item 26 isolation structure) extends from a first end (FIG. 1, item S3) adjacent the first portion (FIG. 1, item 322) of the channel layer (FIG. 1, item 322 and 324) to a second end (FIG. 1, item S4) adjacent the second portion (FIG. 1, item 324) of the channel layer (FIG. 1, item 322 and 324) formed; and
a source structure (FIG. 1, item 22) and a drain structure (FIG. 1, item 24) disposed on opposite lateral sides (FIG. 1, item 22 and 24 on opposite lateral sides of item 26 which extend from S3 to S4) of the isolation layer (FIG. 1, item 26 isolation structure), wherein the opposite lateral sides (FIG. 1, opposite lateral sides of item 26 which extend from S3 to S4) of the isolation layer (FIG. 1, item 26 isolation structure) extend (FIG. 1, item 26 extends from item S3 to S4 on each side that are connected to item 22 and 24) from the first end (FIG. 1, item S3) to the second end (FIG. 1, item S4) of the isolation layer (FIG. 1, item 26 isolation structure), and
wherein an area (FIG. 1, area of item 22) of the source structure (FIG. 1, item 22), in a top view (FIG. 1), has an first shape (FIG. 1, side of item 22, annotated first shape, closest to item 24) having a first width (annotated FIG. 1, first width) and a second shape (FIG., 1 side of item 22, annotated second shape, farthest from item 24) having a second width (annotated FIG. 1, second width), and wherein an area (FIG. 1, area of item 24) of the drain structure (FIG. 1, item 24) has a shape (FIG. 1, item 24) in the top view (FIG. 1) having the second width (annotated FIG. 1, item second width), wherein the first (FIG. 1, side of item 22, annotated first shape, closest to item 24) and second (FIG. 1, side of item 22, annotated second shape, farthest from item 24) shapes are contiguous (FIG. 1, area of item 22), the first shape (FIG. 1, side of item 22, annotated first shape, closest to item 24) being disposed between (FIG 1 shows first shape is between second shape and drain structure) the second shape (FIG. 1, side of item 22, annotated second shape, farthest from item 24) and the drain structure (FIG. 1, item 24) in the top view (FIG. 1),
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FIG. 1 shows an area of the source structure (FIG. 1, area of item 22) and an area of the drain structure (FIG. 1, area of item 24).
Han et al fails to explicitly disclose, wherein the second width is greater than the first width, wherein the area of the source structure is greater than the area of the drain structure when measured in the top view.
However, Tseng et al teaches wherein the area (FIG. 1A, item 50) of the source structure (FIG. 1A, item 50) is greater ([0013], i.e. the source regions 40 and the source contacts 50 wider than the drain regions 42 and the drain contacts 52) than the area (FIG. 1A, item 52) of the drain structure (FIG. 1A, item 52) when measured in the top view (Fig 1A)
Since Han et al and Tseng et al teach source structures, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor memory structure as disclosed to modify Han et al with the teachings of wherein the area of the source structure is greater than the area of the drain structure when measured in the top view as disclosed by Tseng et al. The use of the source regions and the source contacts wider than the drain regions and the drain contacts in Tseng et al provides for the parasitic resistance of the source structure may be reduced which may increase the speed of the FinFET device (Tseng et al, [0013]).
Han et al and Tseng et al fails to explicitly disclose, wherein the second width is greater than the first width.
However, Okumoto et al teaches wherein the second width (FIG. 10B, item second width of item 3114a) is greater (FIG. 10B shows the second width is greater than the first width; [0240], i.e. the areas of the electrodes facing the corresponding electrode increase) than the first width (FIG. 10B, item first width of item 3114a),
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Since Han et al, Tseng et al, and Okumoto et al teach source structures and drain structures, it would have been obvious to one having ordinary skill in the art of semiconductors art at the time of the effective filling date of the effective filing date of the claimed invention to have combined the source structure as disclosed to modify Han et al and Tseng et al with the teachings of the wherein the second width is greater than the first width, wherein an area of the source structure is greater than an area of the drain structure when measured in the top view as disclosed by Okumoto et al. The use of the areas of the electrodes facing the corresponding electrode increase in Okumoto et al provides for an improvement in transistor characteristics (Okumoto et al, [0240]).
“[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05 II. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); Smith v. Nichols, 88 U.S. 112, 118-19 (1874); In re Williams, 36 F.2d 436, 438 (CCPA 1929). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007). See MPEP 2144.05 II
Regarding claim 9. Han et al, and Okumoto et al discloses all the limitations of the semiconductor memory structure of claim 8 above.
Han et al further discloses wherein the isolation layer (FIG. 1, item 26 isolation structure) is a first isolation layer (FIG. 1, item 26 isolation structure), the semiconductor memory structure further comprising second isolation layers (FIG. 1, item 132a-e and 134a-e) disposed over the substrate (FIG. 1, item 101), wherein the first gate layer (FIG. 1, item 122a-d) and the second gate layer (FIG. 1, item 124a-d) are each sandwiched between the second isolation layers (FIG. 1, item 132a-e and 134a-e).
Claims 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Han et al (U.S. 2021/0175253), and Okumoto et al. (U.S. 2013/0328034) as applied to claim 8 above, and further in view of Lee et al (U.S. 2020/0194451).
Regarding claim 11. Han et al, and Okumoto et al discloses all the limitations of the semiconductor memory structure of claim 8 above.
Han et al further discloses further comprising a sidewall (FIG. 1, item S3 and S4) of the first portion (FIG. 1, item 322) of the channel layers (FIG. 1, item 322 and 324) a sidewall (FIG. 1, item S4) of the second portion (FIG. 1, item 324) of the channel layer (FIG. 1, item 322 and 324), wherein the isolation layer extends between
Han et al, and Okumoto et al fail to explicitly disclose comprising a cap layer having a first portion disposed over a sidewall of the first portion of the channel layer and a second portion disposed over a sidewall of the second portion of the channel layer, wherein the isolation layer extends between sidewalls of the cap layers.
However, Lee et al teaches comprising a cap layer (FIG. 4, item 118a) having a first portion (FIG. 4, item 118a on the left) disposed over sidewall ([0051], i.e. the channel pattern 116a, the etch stop layer pattern 118a, and the first insulation layer 120 may be sequentially stacked on the sidewalls of the trench 112 for forming the memory cell) of the first portion (FIG. 4, item 116a on the left) of the channel layer (FIG. 4, item 116a) and a second portion (FIG. 4, item 118a on the right) disposed over a sidewall ([0051]) of the second portion (FIG. 4, item 116a on the right) of the channel layer (FIG. 4, item 116a), wherein the isolation layer (FIG. 4, item 120) extends between sidewalls (FIG. 4, sidewall of item 118a next to item 120) of the first portion (FIG. 4, item 118a on left) and second portion (FIG. 4, item 118a on right side) of the cap layer (FIG. 4, item 118a)
Since Han et al, Okumoto et al and Lee et al teach channel layers, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor memory structure as disclosed to modify Han et al and Su with the teachings of the comprising a cap layer having a first portion disposed over a sidewall of the first portion of the channel layer and a second portion disposed over a sidewall of the second portion of the channel layer, wherein the isolation layer extends between sidewalls of the cap layers as disclosed by Lee et al. The use of the channel pattern, the etch stop layer pattern, and the first insulation layer may be sequentially stacked on the sidewalls of the trench for forming the memory cell in Lee et al provides for the charge storage layers in the neighboring memory cells may be spaced from each other, a disturbance or interference between data stored in the neighboring memory cells may decrease (Lee et al, [0051]).
Regarding claim 12. Han et al, Okumoto et al and Lee et al discloses all the limitations of the semiconductor memory structure of claim 11 above.
Lee et al further discloses wherein a length (FIG. 4, length of item 118a) of the first portion (FIG. 4, item 118a on the left) of the cap layer (FIG. 4, item 118a) in a first direction (FIG. 4, First direction) in a top view (FIG. 4) is less (Annotated FIG. 4, shows length of cap layer is less than a length of channel layers) than a length FIG. 4, length of item 116a) of the first portion (FIG. 4, item 116a on the left) of the channel layers (FIG. 4, item 116a) a first direction (FIG. 4, First direction) in a top view (FIG. 4), wherein a distance (FIG. 4, a distance) between the first end and the second end of isolation layer (FIG. 4, item 120) extends in a second direction (FIG. 4, second direction) in the top view (FIG. 4), the second direction (FIG. 4, second direction) perpendicular (FIG. 4, second direction if perpendicular to first direction) to the first direction (FIG. 4, first direction)
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Response to Arguments
Applicant's arguments filed Jan 5, 2025 have been fully considered but they are not persuasive.
Regarding election/restriction on page 7 of applicant’s remarks appears to argue that the cap layer 114 is formed abutting a sidewall of the channel layer 112; a first isolation structure 116 interfacing a first region of a sidewall of the cap layer 114 along a first plane, the first plane parallel a top surface of the substrate, (e.g., the top surface of the structure of FIG. 1M-1 is a first plane parallel a top surface of the substrate 102).
Examiner respectfully disagrees and points out that the claim language states a first isolation structure 116 interfacing a first region of a sidewall of the cap layer 114 along a first plane, the first plane parallel a top surface of the substrate. Applicant’s elected FIG. 1M-1 shows the isolation structure (FIG. 1M-1, item 116) interfaces (perpendicular to surface of substrate) the cap layer (FIG. 1M-1, item 114) in a perpendicular direction (Not parallel) to the top surface of the substrate (FIG. 1M-1, item 102), i.e. the interface is perpendicular, not parallel to the surface of the substrate. Restriction maintained.
Regarding applicant first point of claim 8: On page 9 of applicant’s remarks, applicant appears to argue Okumoto et al FIG. 10C does not show the first and second shapes are contiguous, the first shape being disposed between the second shape and the drains structure in the top view, wherein the second width is greater than the first width, wherein an area of the source structure is greater than an area of the drain structure when measured in the top view.
Examiner respectfully further points out that FIG. 10C was not used in the rejection, FIG. 10D of Okumoto et al was used.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
On page 10 of applicant’s remarks, Applicant argues that there is no reason that the source electrode of Okumoto would apply to the source electrode of Han et al which are performing different functions.
Examiner respectfully that applicant has not claimed any function of the device, applicant has only claimed a structure of the device. Han et al and Okumoto et al teach source structures and drain structures.
It would have been obvious to one having ordinary skill in the art of semiconductors art at the time of the effective filling date of the effective filing date of the claimed invention to have combined the source structure as disclosed to modify Han et al with the teachings of the wherein the second width is greater than the first width, wherein an area of the source structure is greater than an area of the drain structure when measured in the top view as disclosed by Okumoto et al. The use of the shape of a surface of semiconductor ink applied with respect to the aperture is controlled in Okumoto et al provides for preventing of blending of semiconductor ink with respect to an adjacent aperture (Okumoto et al, [0233]).
In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
Regarding dependent claims:
On page 11 of applicant’s remarks, applicant appears to argue claims 9-14 and 27-32 are allowable for same analogous reasons as claims 1 and 8 above.
Examiner respectfully points out that claims 10, 13 and 14 have been withdrawn due being directed to non-elected species on April 8, 2024. Examiner respectfully disagrees with applicant. Claims 9, 11, 12 and 27-32 are rejected for the same analogous reasons as claims 1 and 8 above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chien et al (U.S. 2022/0223622) discloses a memory structure and method of forming the same.
Lin et al (U.S. 2022/0037362) discloses a three dimensional memory device and method.
Sun et al (U.S. 2021/0399017) discloses a memory device and method of forming the same.
Lu et al (U.S. 2021/0375930) discloses a ferroelectric memory device and method of forming the same.
Lu et al (U.S. 2021/0375931) discloses a ferroelectric memory device and method of forming the same.
Lu et al (U.S. 2021/0375933) discloses a ferroelectric memory device and method of forming the same.
Lu et al (U.S. 2021/0375934) discloses a ferroelectric memory device and method of forming the same.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SCOTT E BAUMAN whose telephone number is (469)295-9045. The examiner can normally be reached M-F, 9-5 CST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S.E.B./ Examiner, Art Unit 2815
/JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815
Prosecution Insights