DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, lines 8-9 and 13-14 recite “a first liner layer comprising a semiconductor material different from the oxide material of the isolation feature” and “a second liner layer comprising a semiconductor material different from the oxide material of the isolation feature”. Since “a semiconductor material different from the oxide material of the isolation feature” is in the first and second limitations, it is not clear if they are intended to be the same material or different materials. This issue renders the claim indefinite.
Note that dependent claims necessarily inherit any indefiniteness from the claims on which they depend.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 6, 10-13, 21, 24 and 27 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by LEE (US 20200091007).
Regarding claim 1, as best as the examiner is able to ascertain the claimed invention, LEE discloses a device, comprising:
a substrate (substrate 100, see fig 13, para 13);
a first semiconductor channel over the substrate (rightmost fin 101a, see fig 13, para 19);
a second semiconductor channel over the substrate and laterally offset from the first semiconductor channel (middle fin 101b, see fig 13, para 19);
an isolation feature (the insulator feature comprising 120 and 130, see fig 13, para 36) embedded in the substrate and laterally between the first and second semiconductor channels (120 and 130 are between 101a and 102b, see fig 13, para 36), the isolation feature comprising an oxide material (130 can be AlON, see fig 13, para 34);
a first liner layer comprising a semiconductor material different from the oxide material of the isolation feature and comprising silicon or silicon germanium (liner layer 106 can be made of SiO which comprises semiconductor Si and is a different material from the AlON of 130, see fig 13, para 22) and laterally surrounding the isolation feature between the isolation feature and the first semiconductor channel (106 surrounds 101a and is between 101a and 120, see fig 13), wherein the first liner layer extends along an X-direction and is in direct contact with the first semiconductor channel on two opposing sides that face the +Y - and -Y - directions (106 extends along the fin longitudinal direction of 101a, which can be the x-direction and is in direct contact with the side faces of 101a, which can be the y-direction, see fig 10); and
a second liner layer comprising a semiconductor material different from the oxide material of the isolation feature and comprising silicon or silicon germanium (liner 110 can be SiON which comprises semiconductor Si and is a different material from the AlON of 130, see fig 13, para 25) and laterally surrounding the first liner layer between the first liner layer and the isolation feature (110 surrounds 106 and is between 106 and 120/130, see fig 13, para 25), wherein the second liner layer is in direct contact with of the first semiconductor channel on two different opposing sidewalls that face the +X- and -X- directions without the first liner layer disposed therebetween (110 is in direct contact with end surfaces of 101a without 106 in between, see fig 13), the two X-facing sidewalls being different from the two Y-facing sidewalls contacted by the first liner layer (106 is in direct contact with the large side faces of 101a, and 110 is in direct contact with the small end surfaces of 101a, see fig 13).
Regarding claim 2, as best as the examiner is able to ascertain the claimed invention, LEE discloses the device of claim 1, wherein the first liner layer has different etch selectivity than the isolation feature (106 can be SiO and 130 can be AlON, which are different materials that have different etch selectivity to some etches, see fig 13, para 34 and 22).
Regarding claim 6, as best as the examiner is able to ascertain the claimed invention, LEE discloses the device of claim 1, wherein the isolation feature comprises silicon oxide (120 can be SiO, see fig 13, para 27).
Regarding claim 10, LEE discloses a device comprising:
a substrate (substrate 100, see fig 13, para 13);
a first isolation region (the region of isolation layers 120 and 130 between 101a and 101b, see fig 13, para 27 and 34) in the substrate;
a second isolation region in the substrate (the region of isolation layers 120 and 130 between the portions of 101b along the longitudinal fin direction, see fig 13, para 33) and laterally offset from the first isolation region in a first direction (the region of 120 and 130 between 101a and 101b is laterally offset from the region of 120 and 130 between the two portions of 101b in the longitudinal direction of the fin 101b, see fig 13);
a first inactive fin structure on the first isolation region (the first part of 136 over the regions of 120 between 101a and 101b, see fig 13, para 55);
a second inactive fin structure on the second isolation region (the second part of 136 over the regions of 120 between the two portions of 101b, see fig 13, para 55);
a vertical transistor between the first isolation region and the second isolation region (the transistor with the fin channel 101b to the left and front of 120, see fig 13, para 19);
a first liner layer in contact with a semiconductor fin of the vertical transistor and the substrate (liner 106 is in direct contact with the fin 101b and the substrate 100, see fig 13, para 22), wherein the first liner layer is in contact with two opposing sides of the vertical transistor (106 is in direct contact with the large side surfaces of 101b, see fig 13); and
a second liner layer in contact with the first liner layer and the first isolation region (liner 110 is in direct contact with 106 and 120, see fig 13, para 26), wherein the second liner layer is in contact with two different opposing sides of the vertical transistor (110 is in direct contact with the small end surfaces of the fins 101b, see fig 13, para 26), and
wherein the first and second isolation regions comprise an oxide material (130 can be AlON, see fig 13, para 34), and the first and second liner layers comprise a semiconductor material different from the oxide material of the first and second isolation regions and comprising silicon or silicon germanium (106 can be SiO and 110 can be SiON, both of which comprise the semiconductor material Si which is not included in AlON layer 130).
Regarding claim 11, LEE discloses the device of claim 10, wherein the first liner layer has different etch selectivity than the first isolation region (106 can be SiO and 130 can be AlON, which are different materials that have different etch selectivity to some etches, see fig 13, para 34 and 22).
Regarding claim 12, LEE discloses the device of claim 10, further comprising: a second vertical transistor (the transistor that has as a channel the part of 101b behind 120 in fig 13, see para 19) laterally offset from the vertical transistor in a second direction orthogonal to the first direction (the two parts of 101b are separated in the longitudinal direction of the fin 101b, see fig 13).
Regarding claim 13, LEE discloses the device of claim 12, wherein the second liner layer is in contact with the substrate between the vertical transistor and the second vertical transistor (110 is in direct contact with 110 between the portions of the fins 101, see fig 13).
Regarding claim 21, LEE discloses a device, comprising:
a first fin stack (the right fin 101a, see fig 13, para 19) including a first nanostructure (the fin 101a, see fig 13, para 19), and a first sidewall (the left sidewall of 101a, see fig 13, para 19);
a second fin stack (the middle fin 101b, see fig 13, para 19) including a second nanostructure (the middle fin 101b, see fig 13, para 19), wherein the first sidewall is facing the second fin stack (the left sidewall of 101a faces 101b, see fig 13);
a first liner layer in contact with two opposing sides of the first fin stack (the liner 106 which is in direct contact with the large sidewalls of 101a, see fig 13, para 21); and
a second liner layer on the first liner layer (second liner 110, see fig 13, para 24), the second liner layer including a first recess between the first fin stack and the second fin stack (the trench in 110 in which 120 and 130 are disposed, see fig 13, para 24), wherein the second liner layer is in contact with two different opposing sides of the first fin stack (110 is in direct contact with the small end surfaces of 101a, see fig 13); and
an isolation region in the first recess (insulators 120 and 130, see fig 13, para 26 and 34),
wherein the isolation region comprises an oxide material (130 can be AlON, see fig 13, para 34), and the first and second liner layers comprise a semiconductor material different from the oxide material of the isolation region and comprising silicon or silicon germanium (106 can be SiO and 110 can be SiON, both of which comprise the semiconductor material Si which is not included in AlON layer 130).
Regarding claim 24, LEE discloses the device of claim 21, wherein the isolation region has different etch selectivity than the second liner layer (106 can be SiO and 130 can be AlON, which are different materials that have different etch selectivity to some etches, see fig 13, para 34 and 22).
Regarding claim 27, LEE discloses the device of claim 21, wherein the first fin stack further includes:
a second sidewall facing a first direction transverse to a second direction (the small sidewall on the longitudinal end of 101a, see fig 13), the first fin stack and the second fin stack being on the second direction, wherein the second liner layer is in contact with the second sidewall (110 is directly in contact with the longitudinal end surface of 101a).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3, 5, 7, 9 and 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over LEE (US 20200091007) in view of PENG (US 20170104061).
Regarding claim 3, as best as the examiner is able to ascertain the claimed invention, LEE discloses the device of claim 2.
LEE fails to explicitly disclose a device, wherein the second liner layer has substantially the same etch selectivity as the first liner layer.
PENG teaches a device, wherein the second liner layer has substantially the same etch selectivity as the first liner layer (414a and 412 can both be SiO, and so will have the same selectivity to some etches, see para 29-30).
LEE and PENG are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of LEE with the materials of PENG because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of LEE with the materials of PENG in order to improve the finFET performance (see PENG para 19).
Regarding claim 5, as best as the examiner is able to ascertain the claimed invention, LEE discloses the device of claim 1.
LEE fails to explicitly disclose a device, wherein the first liner layer and the second liner layer each has thickness in a range of about 1 nanometer to about 5 nanometers.
PENG teaches a device, wherein the first liner layer and the second liner layer each has thickness in a range of about 1 nanometer to about 5 nanometers (414a and 414b can each be 2 nm thick, see para 29).
LEE and PENG are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of LEE with the materials of PENG because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of LEE with the materials of PENG in order to improve the finFET performance (see PENG para 19).
Regarding claim 7, as best as the examiner is able to ascertain the claimed invention, LEE discloses the device of claim 1.
LEE fails to explicitly disclose a device, wherein upper surfaces of the first liner layer and the second liner layer are substantially coplanar with an upper surface of the isolation feature.
PENG teaches a device, wherein upper surfaces of the first liner layer and the second liner layer are substantially coplanar with an upper surface of the isolation feature (upper surfaces of 414a, 414b and 412 are coplanar, see fig 24B).
LEE and PENG are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of LEE with the materials of PENG because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of LEE with the materials of PENG in order to improve the finFET performance (see PENG para 19).
Regarding claim 9, as best as the examiner is able to ascertain the claimed invention, LEE discloses the device of claim 1.
LEE further disclose a device, further comprising an inactive fin structure over the isolation feature and laterally between the first semiconductor channel and the second semiconductor channel (fig 13, 136, para 53).
LEE fails to explicitly disclose a device further comprising a gate structure wrapping around the first semiconductor channel such that the gate structure surrounds the first semiconductor channel on all sides.
PENG teaches a device further comprising a gate structure wrapping around the first semiconductor channel such that the gate structure surrounds the first semiconductor channel on all sides (gate structure 2470 surrounds channel 2264 on all sides, see fig 24, para 60).
LEE and PENG are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of LEE with the materials of PENG because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of LEE with the materials of PENG in order to improve the finFET performance (see PENG para 19).
Regarding claim 26, LEE discloses the device of claim 21.
LEE further disclose a device, further comprising:
an inactive fin structure over the isolation region (insulating fin 140, see fig 9, para 31); and
a gate structure (gate comprising 170, 171 and 173, see fig 9, para 45 and 49) over the first and second fin stacks and the inactive fin structure.
LEE fails to explicitly disclose a device wherein the gate structure wraps around the first nanostructure and the second nanostructure such that the device is a gate-all-around transistor.
PENG teaches a device wherein the gate structure wraps around the first nanostructure and the second nanostructure such that the device is a gate-all-around transistor (gate structure 2470 surrounds channel 2264 on all sides, see fig 24, para 60).
LEE and PENG are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of LEE with the materials of PENG because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of LEE with the materials of PENG in order to improve the finFET performance (see PENG para 19).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over LEE (US 20200091007) in view of LI (US 20200066718).
Regarding claim 8, as best as the examiner is able to ascertain the claimed invention, LEE discloses the device of claim 1.
LEE fails to explicitly disclose a device, wherein the isolation feature includes: a liner layer in physical contact with the second liner layer; and a fill layer laterally surrounded by the liner layer.
LI teaches a device, wherein the isolation feature includes: a liner layer (fig 18B, 120, para 14) in physical contact with the second liner layer; and a fill layer (fig 18B, 130, para 15) laterally surrounded by the liner layer.
LEE and LI are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of LEE with the liner structure of LI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of LEE with the liner structure of LI in order to reduce the AC penalty, the height loss of dummy fin at FEOL, and improve the issue of S/D EPI merge (see LI para 37).
Claim(s) 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over LEE (US 20200091007) in view of CHING (US 20170372969).
Regarding claim 25, LEE discloses the device of claim 21.
LEE fails to explicitly disclose a device, wherein the second liner layer has substantially the same etch selectivity as the first liner layer.
CHING teaches a device, wherein the second liner layer has substantially the same etch selectivity as the first liner layer (210 and 260 can both be SiON, see para 24 and 26).
LEE and CHING are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of LEE with the liner properties of CHING because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of LEE with the liner properties of CHING in order to improve device performance (see CHING para 55).
Allowable Subject Matter
Claims 22-23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record does not teach or suggest, singularly or in combination, at least a device comprising “a first fin stack including a first nanostructure, and a first sidewall; a second fin stack including a second nanostructure, wherein the first sidewall is facing the second fin stack; a first liner layer in contact with two opposing sides of the first fin stack; and a second liner layer on the first liner layer, the second liner layer including a first recess between the first fin stack and the second fin stack, wherein the second liner layer is in contact with two different opposing sides of the first fin stack; and an isolation region in the first recess, wherein the isolation region comprises an oxide material, and the first and second liner layers comprise a semiconductor material different from the oxide material of the isolation region and comprising silicon or silicon germanium” and further “wherein the first liner layer and the second liner layer each comprise silicon germanium” as required by claim 22. Particularly, the requirement that both liner layers comprise silicon germanium in addition to the other requirements for the liner layers are not found in the cited prior art. This represents the main difference between the prior art of record and the invention of claim 22. Claim 23 depends on claim 22.
Response to Arguments
Applicant's arguments filed 12/22/2025 have been fully considered but they are not persuasive.
The applicant argues, regarding claims 1, 10 and 21, that LEE does not disclose a device wherein the isolation region comprises an oxide material and the first and second liners comprise a semiconductor material different from the oxide material of the isolation regions and comprising silicon or silicon germanium. This argument is unpersuasive. LEE discloses, in its figure 13, a device with an isolation feature comprising layers 120 and 130, first liner 106 and second liner 110. 130 can be AlON (see para 34). 106 can be SiO and 110 can be SiON (see para 22 and 25), both of which comprise silicon which is a semiconductor material that is not included in AlON. For at least these reasons, and those given in the rejection above, claims 1, 10 and 21 are not patentable over LEE.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAS TYLER BEARDSLEY whose telephone number is (571)272-3227. The examiner can normally be reached 930-600 M-F.
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/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811