DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant' s Amendment filed on 03/03/2026. Claims 1, 11 and 21 have been amended. Claims 6-7, 15, 17, and 19- 20 were previously canceled. No claims have been added. Currently, claims 1-5, 8-14, 16, 18, and 21-26 are pending.
Response to Arguments
Applicant’s arguments with respect to claims 1, 11 and 21 have been considered but they are not persuasive. The reason is set forth below,
Regarding Claim 1, 11 & 21, pages 8-9, of the applicant’s arguments recited that “As amended, claim 1 recites that the vertically extending portion of the first insulation layer is in direct contact with the one via structure. The foregoing features (the one via structure, the first insulation layer) are non-limiting implementations of elements 914 and 912 of the present application, respectively. Such a direct contact relationship between the first insulation layer and the one via structure is illustrated and annotated below in reproduced FIG. 9J of the present application. In Won, however, none of the portions of the element 65 is in direct contact with the element 69a.” However, the original specification ¶ [0182] mention “first dielectric film 910” while describing the “MIM capacitor 300A” and the first dielectric layer 910 in not in contact with the top electrode. The disclosure does not ever show an embodiment where top electrode is in direct contact with first dielectric layer 910, but it does show top electrode in direct contact with 912. Therefore, it introduces new matter which is not covered by the original specification filed with the application.
For examination purpose, examiner will interpret "first insulation layer" to mean both 910 and 912.
Furthermore, Wang et al. and Won et al. both show the vertical portion of the insulation layer is in direct contact with the top electrode/via. Therefore, rejection is made over Wang, Ming-Tsong (US 20080012138 A1) “Wang et al.” in view of Won, Seok-Jun (US 20050087879 A1) “Won et al.”.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL. —The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 1-5, 8-14, 16, 18, and 21-26 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Amended Claims 1 recites " each of the plurality of via structures is in direct contact with the vertically extending portions of the corresponding insulation layer". However, the original specification ¶ [0182] mention “first dielectric film 910” while describing the “MIM capacitor 300A” and the first dielectric layer 910 in not in contact with the top electrode. The disclosure does not ever show an embodiment where top electrode is in direct contact with first dielectric layer 910, but it does show top electrode in direct contact with 912. Therefore, it introduces new matter which is not covered by the original specification filed with the application.
Claims 2-5, 8-10 inherit the deficiencies of the independent claim 1.
Amended Claims 11 and 21 recites " the vertically extending portion of the first insulation layer is in direct contact with the one via structure". However, the original specification ¶ [0182] mention “first dielectric film 910” while describing the “MIM capacitor 300A” and the first dielectric layer 910 in not in contact with the top electrode. The disclosure does not ever show an embodiment where top electrode is in direct contact with first dielectric layer 910, but it does show top electrode in direct contact with 912. Therefore, it introduces new matter which is not covered by the original specification filed with the application.
Claims 12-14, 16, 18, inherit the deficiencies of the independent claim 11 and claims 22-26 inherit the deficiencies of the independent claim 21.
Appropriate corrections are required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed
invention is not identically disclosed as set forth in section 102, if the differences between the
claimed invention and the prior art are such that the claimed invention as a whole would have
been obvious before the effective filing date of the claimed invention to a person having
ordinary skill in the art to which the claimed invention pertains. Patentability shall not be
negated by the manner in which the invention was made.
Claims 1-2, 11-13, 21-22 and 24-25 is rejected under 35 U.S.C. 103 as being unpatentable over Wang, Ming-Tsong () “Wang” in view of Won, Seok-Jun (US 20050087879 A1) “Won”.
With Regard to Independent Claim 1, Wang Figs. 1-8 and 15 discloses a memory device, comprising:
a first transistor 154 (“a transistor 154” ¶ [0050]); and
a first capacitor 150 (“cell 150” ¶ [0050]) electrically coupled (“transistor 154 is connected so that the selection of the anti-fuse cell 150” ¶ [0050]) to the first transistor 154, the first transistor 154 and the first capacitor 150 forming a first one-time-programmable (OTP) memory cell (“When a voltage V.sub.SG greater than the threshold voltage of the transistor 154 is applied, the OTP anti-fuse cell 150 is selected” ¶ [0050]);
wherein the first capacitor 150 has a first bottom metal terminal 102 (“metal line 102 and diffusion barrier layer 132 form the other electrode” ¶ [0040]), a first top metal terminal (142, 140 & 138) (“metal line 142, via 140 and diffusion barrier layer 138 form one electrode” ¶ [0040]), and a first insulation layer (“Insulation layer 134” ¶ [0040]) interposed between (“Insulation layer 134 electrically insulates the two electrodes” ¶ [0040]) the first bottom metal terminal 102 and first top metal terminal (142, 140 &138);
and wherein the first insulation layer 134 comprises a lateral portion, a vertically extending portion, and is configured with step-like profiles (Stepped 134) (Fig. 8 shows the upper horizontal portion, lower horizontal portion and middle vertical portion connecting the upper and lower horizontal portions and creating a step like profile);
and the first top metal terminal (142, 140 & 138) includes a plurality of via structures (140 &138) (Fig.8 shows 138 of the via structure (140 &138) is in contact with the insulation layer 134), one of which is in direct contact with the first insulation layer 134,
the vertically extending portion of the first insulation layer is in direct contact with the one via structure (Fig.8 shows 138 of the via structure (140 &138) is in contact with the vertically extending portion of the insulation layer 134).
and the first bottom metal terminal 102 includes a first interconnect structure (“the via structure comprise lower-level metal lines …. interconnected by vias.” ¶ [0025]) extending in a first lateral direction (Fig. 15 shows the bottom terminal is extending in a first direction) and disposed in a first metallization layer (“metallization layer m includes a dielectric layer 22, a lower-level metal feature 102 in region 100” ¶ [0025]).
However, Wang does not disclose a top surface of the lateral portion of the first insulation layer and a top surface of the one via structure are laterally aligned with each other.
In the similar field of endeavor of MIM capacitor Won Figs. 9-15 discloses a top surface of the lateral portion of the first insulation layer (“dielectric layers 65 have extension portions (or extension layers) 65e” ¶ [0038]) and a top surface of the one via structure (“plug 69a” ¶ [0039]) are laterally aligned with each other (Figs. 9-15 shows top surface of 65e and 69a are aligned).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify lateral portion first insulation layer and via structure of Wang with the top aligned lateral portion first insulation layer and via structure of won in order to improve leakage current characteristics (Won, ¶ [0043]).
With Regard to Claim 2, Wang as modified by Hall discloses the limitations of claim 1, as discussed above. Wang further discloses wherein the first insulation layer 134 (“remaining portion of the insulation layer 34 is denoted as dielectric layer 134” ¶ [0033]) has a dielectric material (“insulation layer 34 includes a low-k dielectric material” ¶ [0030]) selected from the group consisting of: silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, and tantalum oxide (“such as HfO.sub.2, Ta.sub.2O.sub.5” ¶ [0030]).
With Regard to Independent Claim 11, Wang Fig. 1, Fig. 8 & Fig. 18 discloses a memory device, comprising: a substrate 20 (“substrate 20” ¶ [0025]); a memory array (1601 through 160n) (“a series of parallel anti-fuses 160.sub.1 through 160.sub.n” ¶ [0054]), disposed over the substrate 20, that comprises a plurality of onetime-programmable (OTP) memory cells (1601 through 160n) (“a series of parallel anti-fuses 160.sub.1 through 160.sub.n” ¶ [0054]);
wherein the plurality of OTP memory cells are formed based on a plurality of first interconnect structures 102 (“metal line 102 and diffusion barrier layer 132 form the other electrode” ¶ [0040]), a plurality of insulation layers 134 (“Insulation layer 134 electrically insulates the two electrodes” ¶ [0040]), and a plurality of via structures (142, 140 & 138) (“metal line 142, via 140 and diffusion barrier layer 138 form one electrode” ¶ [0040]), and wherein each of the plurality of insulation layers 134 comprises a step-like profile (Stepped 134) (Fig. 8 shows the upper horizontal portion horizontal, lower horizontal portion and middle vertical portion connecting the upper and lower horizontal portions and creating a step like profile) with vertically extending portions (Fig. 8 shows middle vertical portion connecting the upper and lower horizontal portions) and laterally extending portions (Fig. 8 shows the upper horizontal portion horizontal, lower horizontal portion and middle vertical portion connecting the upper and lower horizontal portions and creating a step like profile).
and wherein the plurality of first interconnect structures 102 extends (Fig. 8 shows 102 extending from left to right) in a first lateral direction (left to right or X-direction),
and the plurality of via structure (142, 140 & 138) are each integrated within a step-like profile configuration (Fig.8 shows 138 of the via structure (142, 140 &138) is integrated within a step like profile and in contact with the insulation layer 134) in direct contact with a corresponding one of the plurality of insulation layers 134, and
each of the plurality of via structures is in direct contact with the vertically extending portions of the corresponding insulation layer (Fig.8 shows 138 of the via structure (140 &138) is in contact with the vertically extending portion of the insulation layer 134).
However, Wang does not disclose a top surface of each of the plurality of via structures are laterally aligned with a top surface of the laterally extending portions of the corresponding insulation layer.
In the similar field of endeavor of MIM capacitor Won Figs. 9-15 discloses a top surface of each of the plurality of via structures (“plug 69a” ¶ [0039]) are laterally aligned (Figs. 9-15 shows top surface of 65e and 69a are aligned) with a top surface of the laterally extending portions of the corresponding insulation layer (“dielectric layers 65 have extension portions (or extension layers) 65e” ¶ [0038]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify lateral portion first insulation layer and via structure of Wang with the top aligned lateral portion first insulation layer and via structure of won in order to improve leakage current characteristics (Won, ¶ [0043]).
With Regard to Claim 12, Wang discloses the limitations of claim 11, as discussed above. Wang Fig. 8 further discloses the step-like profile (Stepped 134) comprises at least one vertical portion (Portion 3) (middle vertical portion of 134 in Fig. 8)) and two lateral portions (Portion 1 and Portion 2) (lower horizontal portion of 134 (Portion 2) and upper horizontal portion (Portion 2) of in Fig. 8) and wherein the at least one vertical portion (Portion 3), with its two ends respectively connected to the lateral portions (Fig. 8 shows the middle portion is vertically extending between the upper and lower horizontal portions of 134), is configured to be broken down by a voltage applied through a corresponding one of the via structures (“a voltage may be applied between the two electrodes, causing a breakdown in insulation layer 134” ¶ [0040]).
With Regard to Claim 13, Wang discloses the limitations of claim 11, as discussed above. Wang Fig. 1, 8 and 18 further discloses
the plurality of first interconnect structures (102 and 132) (“metal line 102 and diffusion barrier layer 132” ¶ [0040]), are disposed in a first metallization layer (“metallization layer m includes a dielectric layer 22, a lower-level metal feature 102” ¶ [0025]);
the plurality of via structures (142, 140 & 138) (“metal line 142, via 140 and diffusion barrier layer 138 form one electrode” ¶ [0040]), are disposed between a second metallization layer (“through trench IMD layer 26 and via IME layer 24 and stops at the metal lines 102” ¶ [0028]) and the first metallization layer (“formed between layers 22, 24 and 26” ¶ [0027]).
With Regard to Independent Claim 21, Wang Fig. 1, Fig. 8 & Fig. 18 discloses a memory device, comprising:
a substrate 20 (“substrate 20” ¶ [0025]);
a memory array comprising a plurality of one-time-programmable (OTP) memory
cells (1601 through 160n) (“a series of parallel anti-fuses 160.sub.1 through 160.sub.n” ¶ [0054]);
wherein the plurality of OTP memory cells is each formed by a corresponding
one of a plurality of transistors 162 (“MOS device 162” ¶ [0054]) formed along a major surface (the upper surface of substrate 20 where the transistor 162 is formed) of the substrate 20 and a
corresponding one of a plurality of capacitors (1601 through 160n) formed above the major surface (Fig. 18 shows 160 is formed above the upper surface of substrate 20); and
wherein the capacitors 160 are formed by a plurality of first interconnect structures 102 (“metal line 102 and diffusion barrier layer 132 form the other electrode” ¶ [0040]),
a plurality of insulation layers 134 (“Insulation layer 134 electrically insulates the two electrodes” ¶ [0040]) with step-like profiles and vertically extending portions (Fig. 8 shows middle vertical portion connecting the upper and lower horizontal portions), and laterally extending portions (Fig. 8 shows the upper horizontal portion horizontal, lower horizontal portion and middle vertical portion connecting the upper and lower horizontal portions and creating a step like profile).
a plurality of via structures (142,140 & 138) (“metal line 142, via 140 and diffusion barrier layer 138 form one electrode” ¶ [0040]),
the plurality of first interconnect structures 102 extends (Fig. 8 shows 102 extending from left to right) in a first lateral direction (left to right or X-direction), and
the plurality of via structure (142, 140 & 138) are each integrated within a step-like profile configuration (Fig.8 shows 138 of the via structure (142, 140 &138) is integrated within a step like profile and in contact with the insulation layer 134) ensuring unique contact points which is in direct contact (Fig. 8 shows 138 of contacting 134 diretly) with a corresponding one of the plurality of insulation layers 134, and
each of the plurality of via structures is in direct contact with the vertically extending portions of the corresponding insulation layer (Fig.8 shows 138 of the via structure (140 &138) is in contact with the vertically extending portion of the insulation layer 134).
However, Wang does not disclose a top surface of each of the plurality of via structures are laterally aligned with a top surface of the laterally extending portions of the corresponding insulation layer.
In the similar field of endeavor of MIM capacitor Won Figs. 9-15 discloses a top surface of each of the plurality of via structures (“plug 69a” ¶ [0039]) are laterally aligned (Figs. 9-15 shows top surface of 65e and 69a are aligned) with a top surface of the laterally extending portions of the corresponding insulation layer (“dielectric layers 65 have extension portions (or extension layers) 65e” ¶ [0038]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify lateral portion first insulation layer and via structure of Wang with the top aligned lateral portion first insulation layer and via structure of won in order to improve leakage current characteristics (Won, ¶ [0043]).
With Regard to Claim 22, Wang discloses the limitations of claim 21, as discussed above. Wang further discloses wherein each of the plurality of insulation layers 134 has a step-like profile (Stepped 134) (Fig. 8 shows the upper horizontal portion horizontal, lower horizontal portion and middle vertical portion connecting the upper and lower horizontal portions and creating a step like profile).
With Regard to Claim 24, Wang discloses the limitations of claim 13, as discussed above. Wang Figs. 1-8 and 15 further discloses wherein the second metallization layer is disposed vertically higher the first metallization layer (Figs. 1-8 and 15 shows the second metallization is vertically higher than first metallization).
With Regard to Claim 25, Wang discloses the limitations of claim 21, as discussed above. Wang Figs. 1-8 and 18 further discloses wherein the plurality of first interconnect structures are disposed in a first metallization layer; and the plurality of via structures are disposed between a second metallization layer and the first metallization layer (Figs. 1-8 and 18 shows the first interconnect structures in first metallization layer and via structures are disposed between first and second metallization layers).
Claims 3 is rejected under 35 U.S.C. 103 as being unpatentable over Wang, Ming-Tsong (US 20080012138 A1) “Wang” in view of Won, Seok-Jun (US 20050087879 A1) “Won” further in view of Tu, Kuo-Chi (US 20180226340 A1) “Tu” further in view of HALL, Jefferson W. (US 20180025982 A1) “Hall”.
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With Regard to Claim 3, Wang discloses the limitations of claim 1, as discussed above. Wang Fig. 8 and 15 further discloses,
a second interconnect (104, “barrier layers 104” ¶ [0026]) structure disposed in a second metallization layer (“a metallization layer m” ¶ [0025]) and coupled to a source/drain terminal (Fig. 15 shows interconnect 104 of 150 is coupled to a source/drain region of transistor 154) of the first transistor (154);
a third interconnect structure (Fig. 15 shows the second interconnect line under VSG) disposed in a third metallization layer (“Metallization layer m may be any of the metallization layers” ¶ [0025]) and coupled to a gate terminal (Fig. 15 shows the third interconnect line under VSG is coupled to the gate of the transistor 154) of the first transistor 154; and
a fourth interconnect structure (Fig. 15 shows the third interconnect line under VBL) disposed in a fourth metallization layer (“Metallization layer m may be any of the metallization layers” ¶ [0025]) and coupled to the via structure of the first capacitor (Fig. 15 shows the fourth interconnect line under VBL is coupled to the top of capacitor 150),
However, Wang does not disclose wherein the second interconnect structure extends along the second lateral direction; wherein the third interconnect structure extends along the first lateral direction; and wherein the fourth interconnect structure extends along one of the first or second lateral direction.
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In the similar field of endeavor of MIM capacitor Tu, Fig. 7 discloses wherein the second interconnect structure 704c in 701b (“the lower metal wire layer 704c, which is further connected to a first source/drain region 717a of an underlying transistor device 716 by way of one or more metal layers (e.g., a conductive contact 718” ¶ [0051]) extends along the second lateral direction (It is understood that there is an “into the page” or Y-direction associated with this device and any three-dimensional object, however clearly Wang does not supply any second lateral or Y directional views in the drawings, so the “second lateral direction” is not shown by Wang and Tu);
wherein the third interconnect structure 716g (“A word line (WL) for addressing the plurality of RRAM cells 706c-706d is coupled to a gate electrode 716g of the transistor device 716” ¶ [0051]) extends along the first lateral direction (towards the outward of the page) (Fig. 7, shows the WL); and
wherein the fourth interconnect structure 704d (“an upper metal wire layer 704d and/or a via layer 714c” ¶ [0047]) extends along one of the first or second lateral direction (Fig. 7 shows 704d is same direction as 704c “the lower metal interconnect layer 106 and the upper metal interconnect layer 116 may comprise metal wire layers configured to provide for an interconnection in a lateral direction” ¶ [0017]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to arrange the interconnect layers of Wang with lateral directions of Tu in order to fabricate the desired memory device. Doing so would allow the lower and upper metal interconnect structures electrically couple the plurality of MIM structures in a series connection between a first voltage potential and a second voltage potential. By placing the plurality of MIM structures in a series connection, dissipation of the first voltage potential (e.g., a supply voltage) is spread out over the plurality of MIM structures, thereby reducing the voltage potential difference between electrodes of any one of the MIM structures (Tu, ¶ [0014]).
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However, Wang and Tu does not show the “second lateral direction” due to the lack of Y-direction cross sectional views or plan views that disclose all three dimensions of the devices. However, it is known that memory devices of interest are objects that exist in three dimensions.
In the similar field of endeavor of OTP memory devices, Hall annotated Figs. 8 and 9, discloses the “vertical one-time-programmable fuse” devices (240, 242, 244, 246 and their associated upper and lower electrodes), which have all three dimensions shown. In Fig. 9, the “into the page” or Y direction, is equivalent to the top to bottom or Y direction in Fig. 8. Hall shows that each of the memory devices and their respective top and bottom electrodes have a depth dimension into the Y-direction. This teaching essentially is used to expand the understanding of the Wang reference, which is that the cross sections views of the memory devices would also inherently include dimensions in the “into the page” or Y direction. So the limitation of “the first interconnect structure extends along the second lateral direction; wherein the second interconnect structure extends along the first lateral direction; and wherein the third interconnect structure extends along one of the first or second lateral direction” is then taught by Wang, because we would understand that Wang’s first interconnect structure’s X direction would cross the inherently present second interconnect structure’s Y-direction dimension, and the two noted directions would then cross in a perpendicular manner.
It would have been obvious to person having ordinary skill in the art before the effective filling date to use the limitation of, “the first interconnect structure extends along the second lateral direction; wherein the second interconnect structure extends along the first lateral direction; and wherein the third interconnect structure extends along one of the first or second lateral direction”, as disclosed by Hall in the system of Wang, for the purpose of disclosing all aspects of the three dimensions of the memory device, so as to understand the basic function and electrical wiring aspects and needs of the memory devices.
Claims 4-5, and 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Wang, Ming-Tsong (US 20080012138 A1) “Wang” in view of Won, Seok-Jun (US 20050087879 A1) “Won” further in view of Tu, Kuo-Chi (US 20180226340 A1) “Tu” further in view of HALL, Jefferson W. (US 20180025982 A1) “Hall” further in view of Kurth, Casey (US 20040008534 A1) “Kurth”.
With Regard to Claim 4, Wang as modified by Tu and Hall discloses the limitations of claim 3, as discussed above. However, Wang does not disclose a second transistor; and a second capacitor electrically coupled to the second transistor, the second transistor and the second capacitor forming a second OTP memory cell; wherein the second capacitor has a second bottom metal terminal, a second top metal terminal, and a second insulation layer interposed between the second bottom and second top metal terminals; and the second top metal terminal includes another via structure in direct contact with the second insulation layer, and the second bottom metal terminal includes a fifth interconnect structure extending in the first lateral direction and disposed in the first metallization layer.
In the similar field of endeavor of memory cells Kurth Fig. 3 and Fig. 4 discloses a second transistor (Fig. 4 shows word line 2202 is connected to the second transistor); and a second capacitor 2142 (“2142” ¶ [0039]) electrically coupled (Fig. 4 shows 2142 and the (second transistor) are connected) to the second transistor (second transistor) (Fig. 4 shows, second transistor is the transistor that the word line 2202 is connected to), the second transistor (second transistor) and the second capacitor 2142 forming a second OTP memory cell (“Memory cells” ¶ [0039]; “ROM cells are programmed to one logic state” ¶ [0042]);
wherein the second capacitor 2142 (Fig. 3 shows the capacitor structure of 2142) has a second bottom metal terminal 152 (“152 (lower electrode)” ¶ [0034]), a second top metal terminal 156 (“conductive node 156” ¶ [0035]), and a second insulation layer 154 (“dielectric layer 154” ¶ [0035]) interposed between the second bottom and second top metal terminals (Fig. 3 shows dielectric layer 154 is in between the nodes 152 and 156); the second top metal terminal 156 includes another via structure (“second conductive node 156 also forms the interconnection lines between the second plates of capacitors” ¶ [0035]) in direct contact (Fig. 3 shows 156 is in direct contact with 154) with the second insulation layer 154, and the second bottom metal terminal 152 includes a fifth interconnect structure extending in the first lateral direction and disposed in the first metallization layer (Fig. 3 shows interconnect structure including 152 in a lateral direction).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the memory system of Wang as modified by Tu with the second transistor and second capacitor of Kurth in order to fabricate the memory array. Doing so would enhance a leakage current from the active area to the substrate, and forming a cell capacitor having a storage plate electrically coupled to the active area. (Kurth, ¶ [0014]]).
With Regard to Claim 5, Wang as modified by Hall further modified by Tu further modified by Kurth discloses the limitations of claim 4, as discussed above. However, Wang does not disclose the fourth metallization layer is disposed over the first metallization layer, the first metallization layer is disposed over the third metallization layer, and the third metallization layer is disposed over the second metallization layer.
In the similar field of endeavor of memory device, Tu Fig. 7 discloses the fourth metallization layer 704d (“metal wire layer 704d” ¶ [0047]) is disposed over the first metallization layer (metallization layer where the electrode 708 is formed), the first metallization layer (metallization layer where the electrode 708 is formed) is disposed over the third metallization layer 716g (“A word line (WL) for addressing the plurality of RRAM cells 706c-706d is coupled to a gate electrode 716g of the transistor device 716” ¶ [0051]) and the third metallization layer 716g is disposed over the second metallization layer (metallization layer where the contact touches the source/drain).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the memory system of Wang as modified by Tu further modified by Kurth with the interconnect and capacitor stricture of Tu in order to couple the plurality of MIM structures in a series connection between a first voltage potential and a second voltage potential electrically by the lower and upper metal interconnect structures. By placing the plurality of MIM structures in a series connection, dissipation of the first voltage potential (e.g., a supply voltage) is spread out over the plurality of MIM structures, thereby reducing the voltage potential difference between electrodes of any one of the MIM structures. Reducing the voltage potential difference, allows for the voltage potential across a MIM structure to be held below the reliability voltage limit (e.g., time dependent dielectric breakdown voltage, etc.), thereby allowing the MIM structures to be used as a decoupling capacitor in a system having a supply voltage greater than the reliability voltage limit (Tu, ¶ [0014]]).
With Regard to Claim 8, Wang as modified by Hall, Tu, Kurth discloses the limitations of claim 4, as discussed above. However, Wang does not disclose the fourth interconnect structure is also coupled to the another via structure of the second capacitor.
In the similar field of endeavor of memory device, Tu Fig. 7 discloses the fourth interconnect structure 704d is also coupled to the another via structure 712 (“an upper electrode 712” ¶ [0051]) of the second capacitor 706d (“706d” ¶ [0051]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the memory system of Wang as modified by Tu further modified by Kurth with the interconnect and capacitor stricture of Tu in order to couple the plurality of MIM structures in a series connection between a first voltage potential and a second voltage potential electrically by the lower and upper metal interconnect structures. By placing the plurality of MIM structures in a series connection, dissipation of the first voltage potential (e.g., a supply voltage) is spread out over the plurality of MIM structures, thereby reducing the voltage potential difference between electrodes of any one of the MIM structures. Reducing the voltage potential difference, allows for the voltage potential across a MIM structure to be held below the reliability voltage limit (e.g., time dependent dielectric breakdown voltage, etc.), thereby allowing the MIM structures to be used as a decoupling capacitor in a system having a supply voltage greater than the reliability voltage limit (Tu, ¶ [0014]]).
With Regard to Claim 9, Wang as modified by Hall, Tu, Kurth discloses the limitations of claim 8, as discussed above. However, Wang does not disclose the first and second insulation layers are physically separated from each other.
In the similar field of endeavor of memory device, Tu Fig. 7 discloses the first and second insulation layers 710 (“dielectric layer 710” ¶ [0052]) are physically separated from each other (Fig. 7 shows dielectric layers are separated from each other).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the memory system of Wang as modified by Tu further modified by Kurth with the interconnect and capacitor stricture of Tu in order to couple the plurality of MIM structures in a series connection between a first voltage potential and a second voltage potential electrically by the lower and upper metal interconnect structures. By placing the plurality of MIM structures in a series connection, dissipation of the first voltage potential (e.g., a supply voltage) is spread out over the plurality of MIM structures, thereby reducing the voltage potential difference between electrodes of any one of the MIM structures. Reducing the voltage potential difference, allows for the voltage potential across a MIM structure to be held below the reliability voltage limit (e.g., time dependent dielectric breakdown voltage, etc.), thereby allowing the MIM structures to be used as a decoupling capacitor in a system having a supply voltage greater than the reliability voltage limit (Tu, ¶ [0014]]).
With Regard to Claim 10, Wang as modified by Hall, Tu, Kurth discloses the limitations of claim 8, as discussed above. However, Wang does not disclose wherein, the first and second insulation layers are formed as a one-piece structure.
In the similar field of endeavor of memory device TU Fig. 7 discloses the first insulation layer 710 extends to the second insulation layer 710 to form a one-piece structure (Fig. 7 shows dielectric layers are one piece structure).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the memory system of Wang as modified by Tu further modified by Kurth with the interconnect and capacitor stricture of Tu in order to couple the plurality of MIM structures in a series connection between a first voltage potential and a second voltage potential electrically by the lower and upper metal interconnect structures. By placing the plurality of MIM structures in a series connection, dissipation of the first voltage potential (e.g., a supply voltage) is spread out over the plurality of MIM structures, thereby reducing the voltage potential difference between electrodes of any one of the MIM structures. Reducing the voltage potential difference, allows for the voltage potential across a MIM structure to be held below the reliability voltage limit (e.g., time dependent dielectric breakdown voltage, etc.), thereby allowing the MIM structures to be used as a decoupling capacitor in a system having a supply voltage greater than the reliability voltage limit (Tu, ¶ [0014]]).
Claims 14, 18, 23 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Wang, Ming-Tsong (US 20080012138 A1) “Wang” in view of Won, Seok-Jun (US 20050087879 A1) “Won” further in view of LIM, Han-jin (US 20150171159 A1) “LIM”.
With Regard to Claim 14, Wang discloses the limitations of claim 13, as discussed above. However, Wang does not disclose a subset of the memory cells arranged along the second lateral direction, share a second interconnect structure disposed in the second metallization layer, each of the subset of memory cells includes a respective one of the insulation layers and a respective one of the first interconnect structures.
In the similar field of endeavor of memory devices LIM, Figs. 6 & 7 discloses a subset of the memory cells (“a first region I and a second region II” ¶ [0075]) arranged along the second lateral direction (It is understood that there is an “into the page” or Y-direction associated with this device and any three-dimensional object, however clearly Wang or LIM do not supply any second lateral or Y directional views in the drawings, so the “second lateral direction” is not shown by Wang and LIM), share a second interconnect structure 600 (“an upper electrode 600” ¶ [0039]) disposed in the second metallization layer (Fig. 7 shows layer 600 is shared across First Region and Second region), each of the subset of memory cells includes a respective one of the insulation layers 500 (“a dielectric layer 500” ¶ [0039]) and a respective one of the first interconnect structures 300 (“a first lower electrode 300” ¶ [0039]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the memory system of Wang with the interconnect and capacitor stricture of LIM in order to mitigate stress of the lower electrodes. Doing so would prevent the collapsing of a capacitor due to stress, if a capacitor in one region collapses or is damaged, and thus does not operate normally, a capacitor in another region can be used to increase redundancy. That is, the first lower electrode 300 in the first region I is advantageous in enduring the stress in the lateral direction, and the second lower electrode 301 in the second region II can prevent the lifting phenomenon. Accordingly, when the adjacent cells undergo the same or similar stress level, all the capacitors can be prevented from collapsing (LIM, ¶ [0080]).
However, Wang and LIM do not show the “second lateral direction” due to the lack of Y-direction cross sectional views or plan views that disclose all three dimensions of the devices. However, it is known that memory devices of interest are objects that exist in three dimensions.
In the similar field of endeavor of OTP memory devices, Hall annotated Figs. 8 and 9, discloses the “vertical one-time-programmable fuse” devices (240, 242, 244, 246 and their associated upper and lower electrodes), which have all three dimensions shown. In Fig. 9, the “into the page” or Y direction, is equivalent to the top to bottom or Y direction in Fig. 8. Hall shows that each of the memory devices and their respective top and bottom electrodes have a depth dimension into the Y-direction. This teaching essentially is used to expand the understanding of the Wang reference, which is that the cross sections views of the memory devices would also inherently include dimensions in the “into the page” or Y direction. So the limitation of “second interconnect structures is operatively shared by a subset of the memory cells arranged along the second lateral direction” is then taught by Wang, because we would understand that Wang’s first interconnect structure’s X direction would cross the inherently present second interconnect structure’s Y-direction dimension, and the two noted directions would then cross in a perpendicular manner.
It would have been obvious to person having ordinary skill in the art before the effective filling date to use the limitation of, “second interconnect structure is operatively shared by a subset of the memory cells arranged along the second lateral direction”, as disclosed by Hall in the system of Wang, for the purpose of disclosing all aspects of the three dimensions of the memory device, so as to understand the basic function and electrical wiring aspects and needs of the memory devices.
With Regard to Claim 18, Wang discloses the limitations of claim 13, as discussed above. However, Wang does not disclose a subset of the memory cells arranged along a second lateral direction, share a second interconnect structure disposed in the second metallization layer, each of the subset of memory cells includes a respective one of the first interconnect structures, and the subset of memory cells share one of the insulation layers.
In the similar field of endeavor of memory devices LIM, Figs. 6 & 7 discloses a subset of the memory cells (“a first region I and a second region II” ¶ [0075]) arranged along the second lateral direction (It is understood that there is an “into the page” or Y-direction associated with this device and any three-dimensional object, however clearly Wang or LIM do not supply any second lateral or Y directional views in the drawings, so the “second lateral direction” is not shown by Wang and LIM), share a second interconnect structure 600 (“an upper electrode 600” ¶ [0039]) disposed in the second metallization layer (Fig. 7 shows layer 600 is shared across First Region and Second region),each of the subset of memory cells includes a respective one of the first interconnect structures 300 (“a first lower electrode 300” ¶ [0039]), and the subset of memory cells share (Fig. 7 shows insulation layer 500 is shared across region I and region II ) one of the insulation layers 500 (“a dielectric layer 500” ¶ [0039]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the memory system of Wang with the interconnect and capacitor stricture of LIM in order to mitigate stress of the lower electrodes. Doing so would prevent the collapsing of a capacitor due to stress, if a capacitor in one region collapses or is damaged, and thus does not operate normally, a capacitor in another region can be used to increase redundancy. That is, the first lower electrode 300 in the first region I is advantageous in enduring the stress in the lateral direction, and the second lower electrode 301 in the second region II can prevent the lifting phenomenon. Accordingly, when the adjacent cells undergo the same or similar stress level, all the capacitors can be prevented from collapsing (LIM, ¶ [0080]).
However, Wang and LIM do not show the “second lateral direction” due to the lack of Y-direction cross sectional views or plan views that disclose all three dimensions of the devices. However, it is known that memory devices of interest are objects that exist in three dimensions.
In the similar field of endeavor of OTP memory devices, Hall annotated Figs. 8 and 9, discloses the “vertical one-time-programmable fuse” devices (240, 242, 244, 246 and their associated upper and lower electrodes), which have all three dimensions shown. In Fig. 9, the “into the page” or Y direction, is equivalent to the top to bottom or Y direction in Fig. 8. Hall shows that each of the memory devices and their respective top and bottom electrodes have a depth dimension into the Y-direction. This teaching essentially is used to expand the understanding of the Wang reference, which is that the cross sections views of the memory devices would also inherently include dimensions in the “into the page” or Y direction. So, the limitation of “each of the second interconnect structures is operatively shared by a subset of the memory cells arranged along the second lateral direction” is then taught by Wang, because we would understand that Wang’s first interconnect structure’s X direction would cross the inherently present second interconnect structure’s Y-direction dimension, and the two noted directions would then cross in a perpendicular manner.
It would have been obvious to person having ordinary skill in the art before the effective filling date to use the limitation of, “each of the second interconnect structures is operatively shared by a subset of the memory cells arranged along the second lateral direction”, as disclosed by Hall in the system of Wang, for the purpose of disclosing all aspects of the three dimensions of the memory device, so as to understand the basic function and electrical wiring aspects and needs of the memory devices.
With Regard to Claim 23, Wang discloses the limitations of claim 13, as discussed above. However, Wang does not disclose wherein a subset of the memory cells arranged along the first lateral direction share a second interconnect structure disposed in the second metallization layer, each of the subset of memory cells includes a respective one of the first interconnect structures, and the subset of memory cells share one of the insulation layers.
In the similar field of endeavor of memory devices LIM, Figs. 6 & 7 discloses wherein a subset of the memory cells (“a first region I and a second region II” ¶ [0075]) arranged along the first lateral direction (Fig. 7 shows the memory cells are in the X direction), share a second interconnect structure 600 (“an upper electrode 600” ¶ [0039]) disposed in the second metallization layer (Fig. 7 shows layer 600 is shared across First Region and Second region), each of the subset of memory cells includes a respective one of the first interconnect structures 300 (“a first lower electrode 300” ¶ [0039]), and the subset of memory cells share one of the insulation layers 500 (“a dielectric layer 500” ¶ [0039]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the memory system of Wang with the interconnect and capacitor stricture of LIM in order to mitigate stress of the lower electrodes. Doing so would prevent the collapsing of a capacitor due to stress, if a capacitor in one region collapses or is damaged, and thus does not operate normally, a capacitor in another region can be used to increase redundancy. That is, the first lower electrode 300 in the first region I is advantageous in enduring the stress in the lateral direction, and the second lower electrode 301 in the second region II can prevent the lifting phenomenon. Accordingly, when the adjacent cells undergo the same or similar stress level, all the capacitors can be prevented from collapsing (LIM, ¶ [0080]).
With Regard to Claim 26, Wang discloses the limitations of claim 25, as discussed above. However, Wang does not disclose wherein a subset of the memory cells share a second interconnect structure disposed in the second metallization layer.
In the similar field of endeavor of memory devices LIM, Figs. 6 & 7 discloses a subset of the memory cells (“a first region I and a second region II” ¶ [0075]) share a second interconnect structure 600 (“an upper electrode 600” ¶ [0039]) disposed in the second metallization layer (Fig. 7 shows layer 600 is shared across First Region and Second region).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the memory system of Wang with the interconnect and capacitor stricture of LIM in order to mitigate stress of the lower electrodes. Doing so would prevent the collapsing of a capacitor due to stress, if a capacitor in one region collapses or is damaged, and thus does not operate normally, a capacitor in another region can be used to increase redundancy. That is, the first lower electrode 300 in the first region I is advantageous in enduring the stress in the lateral direction, and the second lower electrode 301 in the second region II can prevent the lifting phenomenon. Accordingly, when the adjacent cells undergo the same or similar stress level, all the capacitors can be prevented from collapsing (LIM, ¶ [0080]).
Claims 16 is rejected under 35 U.S.C. 103 as being unpatentable over Wang, Ming-Tsong Wang, Ming-Tsong (US 20080012138 A1) “Wang” in view of Won, Seok-Jun (US 20050087879 A1) “Won” further in view of LIM, Han-jin (US 20150171159 A1) “LIM” further in view of Wang, Zhongze (US 20140210043 A1) “Zhongze”.
With Regard to Claim 16, Wang discloses the limitations of claim 13, as discussed above. However, Wang does not disclose a subset of the memory cells arranged along the first lateral direction, share a second interconnect structure disposed in the second metallization layer, each of the subset of memory cells includes a respective one of the insulation layers and a respective one of the first interconnect structures.
In the similar field of endeavor of memory cells Zhongze Fig. 13 and Fig. 14 discloses a subset of the memory cells 1402 and 1404 (“a plurality of programmable memory cells 1402, 1404” ¶ [0082]) arranged along the first lateral direction (vertical direction) (Fig. 14 shows the memory cells 1402 and 1404 are in vertical direction), share a second interconnect structure (“a bit line BL2” ¶ [0083]) disposed in the second metallization layer ML1, each of the subset of memory cells 1402 and 1404 includes a respective one of the insulation layers 136 (“dielectric used within the antifuse 1412, 1422” ¶ [0088]; “dielectric 136” ¶ [0089]) and a respective one of the first interconnect structures 304 (“electrode 304” ¶ [0089]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to arrange the interconnect layers of Wang as modified by Tu with the memory cells array of Zhongze in order to fabricate the desired memory array. Doing so would satisfy a need for integrated circuits having antifuse that can transition from open circuit states to closed circuit states at lower programming voltages. (Zhongze, ¶ [0010]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/AKHEE SARKER-NAG/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893