DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 08, 2026 has been entered.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed January 08, 2026. Claims 1, 6-and 7 have been amended. No new claims have been added. Claim 15 has been withdrawn. Claim 11 has been canceled. Currently, claims 1-10, 12-14 and 16-20 are pending.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot as applied to the newly added claim limitations because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 2010/0102301 A1; hereafter Yang) in view of Lee (US 2021/0200365 A1; hereafter Lee), Kurokawa et al. (US 2011/0205209 A1; hereafter Kurokawa), Nho (US 2015/0331508 A1; hereafter Nho) and Liu et al. (US 2021/0335251 A1; hereafter Liu).
Regarding claim 1, Yang teaches a display panel (see e.g., Figure 1 shows a cross-sectional view of an organic light emitting display device) comprising:
Yang shows a single pixel region in Figure 1 however, it is understood that the display device inherently will have a plurality of emission areas and a plurality of sensor areas in the display device (see general description of the display device with a plurality of pixels as discussed in the “Summary of the Invention” section, Para [0011]).
a base layer comprising a plurality of emission areas and plurality of sensor areas (see e.g., a substrate 100 of organic light emitting device 10 includes a pixel region 101 in which pixels are formed and a non-pixel region 102. The pixel region 101 includes an organic light emitting diode 160 and a capacitor 120 and a thin film transistor (TFT) 130 that are driving devices. The non-pixel region 102 includes a light sensor 140 formed of photodiodes, Para [0022], Figure 1. Further evidence of plurality of emission areas is in the disclosure of Yang in Para [0011], where the display device is disclosed to have plural pixels, thus satisfying the plural emission areas. Last, Yang shows a sensor with an emission device in Fig. 1, but is silent explicitly stating a “plurality” of “sensor areas”, but it is strongly suggested and examiner’s understanding is that there would be plural sensors for the plural emission areas. What common sense purpose would there be to have only one sensor for an entire array of pixels? This arrangement of one sensor to an entire array of pixels is not taught as well. This feature of a plurality of sensor areas, will be further addressed below with the secondary reference of Nho, who clearly shows this limitation of plural sensors in Figs. 8C and 9A.);
pixel circuits disposed on the base layer (see e.g., pixel circuit including a capacitor 120 and TFT 130 formed on the substrate 100, Para [0022], Figure 1);
light emitting elements respectively disposed on and connected to the pixel circuits, each of the light emitting elements comprising a light emitting layer defining the corresponding one of emission areas (see e.g., organic light emitting diode 160 disposed and connected to the pixel circuit including the capacitor 120 and the TFT 130. The organic light emitting diode 160 comprises a light emitting layer 160b overlapping the pixel region 101, Para [0029], Figure 1);
illuminance sensors respectively disposed on the sensor areas of the base layer, each of the illuminance sensors comprising a light receiving element defining a corresponding one of the sensor areas, the light receiving elements disposed to be adjacent to neighboring ones of the pixel circuits (see e.g., light sensor 140 disposed on the substrate 100 adjacent to the pixel circuit including the capacitor 120 and the TFT 130, Figure 1);
a bank layer having openings partitioning adjacent ones of emission areas (see e.g., pixel defining layer 170 disposed on the insulating film 150 and the first electrode 160a. The pixel defining layer 170 has openings over the central area of the first electrodes 160a, Para [0029], Figure 1).
Yang does not explicitly show the bank layer partitioning adjacent emission areas as Yang shows a single pixel, however, it is understood that the adjacent emission area would be partitioned by the pixel defining layer 170 at the edges of the pixel region.
Yang does not explicitly teach
“a black matrix disposed above the light emitting elements and having a plurality of openings respectively overlapping the light emitting layers of the light emitting elements and a first illuminance sensor among the illuminance sensors; and
a color filter disposed above the light emitting elements and … the black matrix, the color filter comprising a first color filter overlapping a light receiving element of the first illuminance sensor and a second color filter overlapping a first light emitting element among the light emitting elements”,
In a similar field of endeavor Kurokawa teaches
a black matrix disposed above the light emitting elements and having a plurality of openings respectively overlapping the light emitting layers of the light emitting elements and a first illuminance sensor among the illuminance sensors; and (see e.g., the shielding film 1015 has openings overlapping the display element portion 105 and the photodiode 1002. Although the display element portion 105 described includes the liquid crystal element 1005, the display element portion 105 may include other elements such as a light-emitting element. The light-emitting element is an element in which the luminance is controlled by current or voltage. Specifically, a light-emitting diode (LED), an organic light-emitting diode (OLED), Paras [0047], [0135], [0144], Figure 13)
a color filter disposed above the light emitting elements and … the black matrix, the color filter comprising a first color filter overlapping a light receiving element of the first illuminance sensor and a second color filter overlapping a first light emitting element among the light emitting elements (see e.g., display device with a plurality of photosensors are provided with color filters with colors R (red), G (green), and B (blue) in a pixel to form a color sensor, so that a color image sensor function can be provided. The photosensor consists of a photodiode 1002. External light to be detected by the photodiode 1002 enters the counter substrate 1013 in a direction indicated by an arrow 2025 to reach the photodiode 1002. A color filter 1014 overlaps the photodiode 1002 and the display element portion 105, Paras [0047], [01444], [0151], Figures 2 and 13).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Kurokawa’s teachings of a black matrix disposed above the light emitting elements and having a plurality of openings respectively overlapping the light emitting layers of the light emitting elements and a first illuminance sensor among the illuminance sensors; and
a color filter disposed above the light emitting elements and … the black matrix, the color filter comprising a first color filter overlapping a light receiving element of the first illuminance sensor and a second color filter overlapping a first light emitting element among the light emitting elements in the device of Yang in order to improve imaging accuracy.
Yang does not explicitly teach
“a color filter disposed …… on the black matrix…. wherein the bank layer overlaps the black matrix”,
In a similar field of endeavor Lee teaches
a color filter disposed … on the black matrix (see e.g., Color filter, CF, disposed above the light emitting elements 210 and the black matrix BM, Para [0051], Figure 6)… wherein the bank layer overlaps the black matrix (see e.g., bank 250 overlaps the black matrix BM, Figure 6)
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Lee’s teachings of a color filter disposed … on the black matrix)… wherein the bank layer overlaps the black matrix in the device of Yang as this modification enables the color filters to emit the required light while utilizing the black matrix to optimally partition adjacent pixels. The configuration improves display quality by preventing backlight bleeding between pixels, reducing the reflection of external light and achieving a clearer image with improved contrast.
Yang does not explicitly teach (italicized and bolded portions highlighting the pluralized version of the claim language which Yang does not explicitly disclose),
“a base layer comprising a plurality of … plurality of sensor areas;
illuminance sensors respectively disposed on the sensor areas … (this portion merely stating the general lack of teaching of plurality of sensor areas and consequently lack of teaching of plurality of illuminance sensors.)
wherein at least one of the illuminance sensors has ones of the pixel circuits adjacent thereto in both a first direction and a second direction crossing the first direction in a plan view”.
In a similar field of endeavor Nho teaches
a base layer comprising a plurality of … plurality of sensor areas (see e.g., plurality of sensor areas disposed on the substrate as shown in Figures 8C and 9A);
illuminance sensors respectively disposed on the sensor areas …(see e.g., the plurality of sensor areas include photodiodes as shown in Figures 8C and 9A)
wherein at least one of the illuminance sensors has ones of the pixel circuits adjacent thereto in both a first direction and a second direction crossing the first direction in a plan view (see e.g., it appears that Nho shows the photodiodes 908 are adjacent to the TFTs 909 in Figure 9A, but for the rejection Yang has already placed the photodiode 140 immediately adjacent to the TFTs. So, Yang is used to teach that. Nho is used to show FIRST that each pixel has it's own TFT below it in Figure 9A. Nho is second used to disclose the arrangement in Figure 8C where each photodiode P is adjacent to plural color pixels in both the first direction and the second direction, where each color pixel has a TFT that would then be adjacent to where the photosensors are located).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Nho’s teachings of,
“a base layer comprising a plurality of … plurality of sensor areas;
illuminance sensors respectively disposed on the sensor areas … (this portion merely stating the general lack of teaching of plurality of sensor areas and consequently lack of teaching of plurality of illuminance sensors.)
wherein at least one of the illuminance sensors has ones of the pixel circuits adjacent thereto in both a first direction and a second direction crossing the first direction in a plan view”,
in the device of Yang in order to increase the sensing capacitance and enhance the touch sensitivity.
Yang does not explicitly teach
“wherein the black matrix and the bank layer cover a light receiving element of a second illuminance sensor among the illuminance sensors to block external light and to generate dark reference current”
In a similar field of endeavor Liu teaches generic concept of having a photosensor S2 used to detect variations in external environment that are not caused by variations in ambient light.
Liu teaches wherein the black matrix and the bank layer cover a light receiving element of a second illuminance sensor among the illuminance sensors to block external light and to generate dark reference current (see e.g., each unit sensor 3 includes a photosensor S2. The ambient light is blocked by the black matrix and the pixel defining layer as shown in Figure 8. As a result, the second photosensor S2 is configured to detect environmental variations unrelated to changes in ambient light such as thermal noise, to generate a dark reference current/second signal. The second signal is explicitly used as a correction factor for the first photosensor S1, allowing for the removal of distortions and noises that are unrelated to external ambient light changes. Changes in ambient light will not be included in the signals generated by the second photosensor S2, Paras [0039], [0040], [0042], Figure 8).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Liu’s teachings of wherein the black matrix covers a light receiving element of a second illuminance sensor among the illuminance sensors to block external light and to generate dark reference current in the device of Yang in order to improve accuracy and reliability through real-time correction of dark current noise.
Regarding claim 20, Yang, as modified by Lee, Kurokawa, Nho and Liu, teaches the limitations of claim 1 as mentioned above. Yang does not explicitly teach
“further comprising a touch sensor layer disposed between the light emitting elements and the black matrix”.
In a similar field of endeavor Lee teaches further comprising a touch sensor layer disposed between the light emitting elements and the black matrix (see e.g., touch sensor unit 400 disposed between the light emitting elements 210 and the black matrix BM, Para [0046], Figure 6).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Lee’s teachings of a touch sensor layer disposed between the light emitting elements and the black matrix in the device of Yang in order to provide touch sensing functions.
Claims 2-7, 14 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Lee, Kurokawa, Nho and Liu and further in view of Wang (US 2021/0335917 A1).
Regarding claim 2, Yang, as modified by Lee, Kurokawa, Nho and Liu, teaches the limitations of claim 1 as mentioned above. Yang does not explicitly teach
“wherein each of the illuminance sensors further comprises: a sensor transistor connected to the light receiving element; and a capacitor connected to the light receiving element and configured to store a detection value of the light receiving element”.
In a similar field of endeavor Wang teaches
wherein each of the illuminance sensors further comprises: a sensor transistor connected to the light receiving element; and a capacitor connected to the light receiving element and configured to store a detection value of the light receiving element (see e.g., photodetector 300 comprises a photo-detecting device 310, a first capacitor corresponding to capacitor CO and a fourth switch transistor 330. The photo-detecting device 310 is thus configured to convert a light signal corresponding to the intensity of the emitted light into an electrical signal, and store the electrical signal in the capacitor CO, Paras [0049], [0065], [0103], Figure 1A).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Wang’s teachings of each of the illuminance sensors further comprises: a sensor transistor connected to the light receiving element; and a capacitor connected to the light receiving element and configured to store a detection value of the light receiving element in the device of Yang in order to provide control signals.
Regarding claim 3, Yang, as modified by Lee, Kurokawa, Nho, Liu and Wang, teaches the limitations of claim 2 as mentioned above. Yang does not explicitly teach wherein the sensor transistor comprises:
“a first active pattern disposed on the base layer;
a first gate electrode overlapping the first active pattern with a gate insulating layer there between; and
a first source electrode and a first drain electrode disposed on a first insulating layer and an interlayer insulating layer on the first gate electrode,
the interlayer insulating layer being between the first gate electrode and the first insulating layer,
wherein the first source electrode and the first drain electrode contact the first active pattern through contact holes penetrating the first insulating layer, the interlayer insulating layer, and the gate insulating layer”.
In a similar field of endeavor Wang teaches
a first active pattern disposed on the base layer (see e.g., the switch transistor 330 having an active pattern as shown in modified Figure 1B);
a first gate electrode overlapping the first active pattern with a gate insulating layer there between; and (see e.g., the gate electrode of the switch transistor 330 as shown in modified Figure 1B)
a first source electrode and a first drain electrode disposed on a first insulating layer and an interlayer insulating layer on the first gate electrode (see e.g., the source and drain electrodes of the switch transistor 330 disposed on interlayer insulating layer and the first insulating layer as shown in modified Figure 1B),
the interlaver insulating layer being between the first gate electrode and the first insulating layer (see e.g., the interlayer insulating layer and the first insulating layer as shown in modified Figure 1B; Examiner’s interpretation: the Applicant does not distinguish between the interlayer insulating film and the first insulating layer therefore, top part of insulating may be considered as the interlayer insulating layer and the part below it and above the gate electrode may be considered to be the first insulating layer),
wherein the first source electrode and the first drain electrode contact the first active pattern through contact holes penetrating the first insulating layer, the interlayer insulating layer, (see e.g., as shown in modified Figure 1B the source and drain electrodes contact the active layer through contact holes penetrating the insulating layer comprising the interlayer insulating layer and the first insulting layer).
Wang does not show the gate insulating film to be a continuous layer rather as a patterned layer. However, Yang’s gate insulating film 122 is continuous which allows multiple transistors to be fabricated with reduced fabrication time and cost. If Wang’s gate insulating film is continuous like Yang’s then the source/drain electrodes would penetrate the insulating layers and the gate insulting film.
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Modified Figure 1B, Wang
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Wang’s teachings of to form multiple insulating layers extending throughout the pixel area, functioning for example, as gate insulating layer etc., when fabricating multiple transistors in a pixel area in the device of Yang in order to reduce fabrication time and cost.
Regarding claim 4, Yang, as modified by Lee, Kurokawa, Nho, Liu and Wang, teaches the limitations of claim 3 as mentioned above. Yang further teaches
wherein the pixel circuit further comprises:
a pixel transistor connected to each of the light emitting elements, and (see e.g., driving thin-film transistor 130 connected to the light emitting device 160, Para [0022], Figure 1)
wherein the pixel transistor comprises:
a second active pattern disposed on a same level, (see e.g., semiconductor layer 130a disposed on the substrate 100, Para [0024], Figure 1);
a second gate electrode; and (see e.g., gate metal 130b, Para [0024], Figure 1)
a second source electrode and a second drain electrode disposed on a same level, and contacting the second active pattern through contact holes penetrating the first insulating layer, the interlayer insulating layer, and the gate insulating layer (see e.g., source/drain metal 130c disposed on the interlayer insulating film 124 and the gate insulating film 122. Source/drain metal 130c is electrically connected to semiconductor layer 130a through a contact hole 131 which pass through the gate insulating film 122 and the interlayer insulating film 124, Figure 1; Examiner’s interpretation: the Applicant does not distinguish between the interlayer insulating film and the first insulating layer therefore, top part of 124 may be considered as the interlayer insulating layer and the bottom part to be the first insulating layer).
Yang does not explicitly teach
“a second active pattern disposed on a same level, on which the first active pattern is disposed
a second source electrode and a second drain electrode disposed on a same level, on which the first source electrode is disposed
a second gate electrode disposed on a same level, on which the first gate electrode disposed”
In a similar field of endeavor Wang teaches
a second active pattern disposed on a same level, on which the first active pattern is disposed (see e.g., as shown in modified Figure 1B, the active layers for the transistors 220 and 330 are disposed at the same level)
a second source electrode and a second drain electrode disposed on a same level, on which the first source electrode is disposed (see e.g., as shown in modified Figure 1B, the source/drain electrodes of transistors 220 and 330 are disposed at the same level)
a second gate electrode disposed on a same level, on which the first gate electrode disposed (see e.g., as shown in modified Figure 1B, the gate electrodes of transistors 220 and 330 are disposed at the same level)
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Wang’s teachings of a second active pattern disposed on a same level, on which the first active pattern is disposed a second source electrode and a second drain electrode disposed on a same level, on which the first source electrode is disposed a second gate electrode disposed on a same level, on which the first gate electrode disposed in the device of Yang in order to form gate electrodes of multiple transistors in a pixel area at the same level in order to reduce fabrication cost and time.
Regarding claim 5, Yang, as modified by Lee, Kurokawa, Nho, Liu and Wang, teaches the limitations of claim 3 as mentioned above. Yang further teaches
wherein each of the light emitting elements further comprises a first electrode (see e.g., the light emitting element 160 comprises a first electrode 160a, Para [0027], Figure 1) and a second electrode (see e.g., light emitting element 160 comprises a second electrode 160, Para [0030], Figure 1), the first electrode and the second electrode being disposed on a second insulating layer (see e.g., the insulating film 150, Para [0027], Figure 1), the second insulating layer being on the pixel circuit (see e.g., the insulating film 150 disposed on the driving circuitry including capacitor 120 and the transistor 130), wherein the light emitting layer is interposed between the first electrode and the second electrode (see e.g., the light emitting element 160 comprises a organic light emitting layer 160b interposed between the first electrode 1160a and the second electrode 160b, Para [0029], Figure 1).
Regarding claim 6, Yang, as modified by Lee, Kurokawa, Nho, Liu and Wang, teaches the limitations of claim 5 as mentioned above. Yang further teaches
Wherein the bank layer is disposed on the second insulating layer and on an upper surface of the first electrode (see e.g., pixel defining layer 170 disposed on the insulating film 150 and the first electrode 160a), the bank layer having openings over a central region of the first electrodes (see e.g., pixel defining layer 170 has openings over the central area of the first electrodes 160a, Para [0029], Figure 1).
Yang does not explicitly show the bank layer partitioning adjacent emission areas as Yang shows a single pixel, however, it is understood that the adjacent emission area would be partitioned by the pixel defining layer 170 at the edges of the pixel region.
Regarding claim 7, Yang, as modified by Lee, Kurokawa, Nho, Liu and Wang, teaches the limitations of claim 6 as mentioned above. Yang further teaches
wherein the bank layer is disposed between adjacent ones of the emission areas and the sensor areas in the plan view (see e.g., pixel defining layer 170 is disposed between the pixel region 101 and the non-pixel region 102, Figure 1).
Regarding claim 14, Yang, as modified by Lee, Kurokawa, Nho, Liu and Wang, teaches the limitations of claim 5 as mentioned above. Yang further teaches
wherein the second electrode extends to overlap the sensor area (see e.g., the second electrode 160c overlaps the non-pixel region 102, Para [0030], Figure 1).
Regarding claim 16, Yang, as modified by Lee, Kurokawa, Nho, Liu and Wang, teaches the limitations of claim 3 as mentioned above. Yang does not explicitly teach
“wherein the light receiving element comprises:
a conductive layer disposed on the interlayer insulating layer;
a semiconductor layer disposed on the conductive layer; and
a transparent conductive layer disposed on the semiconductor layer and overlapping the sensor area”.
In a similar field of endeavor Wang teaches
wherein the light receiving element comprises (see e.g., the photodetector 300, Para [0049], Figure 1A):
a conductive layer disposed on the interlayer insulating layer (see e.g., first electrode 313 disposed on an insulating layer, Para [0079], Figure 1A);
a semiconductor layer disposed on the conductive layer; and (see e.g., light sensitive layer 311 comprises a PIN junction, Para [0011], Figure 1)
a transparent conductive layer disposed on the semiconductor layer and overlapping the sensor area (see e.g., the second electrode 314 disposed on the light sensitive layer 311 and is transparent, Para [0094], Figure 1A).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Wang’s teachings of a light receiving element comprising a semiconductor layer in between conductive layers in the device of Yang in order to improve display functions of the display substrate.
Regarding claim 17, Yang, as modified by Lee, Kurokawa, Nho, Liu and Wang, teaches the limitations of claim 16 as mentioned above. Yang does not explicitly teach
“wherein each of the illuminance sensors further comprises a bias electrode disposed on the first insulating layer, the bias electrode connected to the transparent conductive layer by passing through the first insulating layer”.
In a similar field of endeavor Wang teaches
wherein each of the illuminance sensors further comprises a bias electrode disposed on the first insulating layer, the bias electrode connected to the transparent conductive layer by passing through the first insulating layer (see e.g., signal line 350 disposed on an insulating layer and connected to the second electrode 314 via a contact passing through the insulating layer. The signal line 350 may be configured to supply the second electrode 314 with a constant voltage, Para [0123], Figure 1A).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Wang’s teachings of a bias electrode connected to the sensor electrode in the device of Yang in order to provide a constant voltage.
Claims 8-9 and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Lee, Kurokawa, Nho, Liu and Wang and further in view of Chang et al. (US 2010/0315377 A1; hereafter Chang).
Regarding claim 8, Yang, as modified by Lee, Kurokawa, Nho, Liu and Wang, teaches the limitations of claim 6 as mentioned above. Yang does not explicitly teach
“the first light emitting element adjacent to one side of the first illuminance sensor in the first direction in the plan view, and the first color filter is different from the second color filter”.
In a similar field of endeavor Chang teaches
wherein: the first light emitting element adjacent to one side of the first illuminance sensor in a first direction, and the first color filter is different from the second color filter (see e.g., pixel 40 includes the first sub pixel 41, the second sub pixel 42 and the third sub pixel 43. The first sub pixel 41 has a light sensing region 26a and a display region 28 unlike the second sub pixel 42 and the third sub pixel 43 which only have display region 28.
A first color filter film 30a is arranged in the first sub pixel 41 of the light sensing region 26a of the light sensor and the second color filter 32 which comprises first, second and third different color filters 32a, 32b and 32c respectively is arranged in the first subpixel 41, the second sub pixel 42 and the third sub pixel 43 of the effective display region 28.
If the color filter 30a in the sensing region 26a is for example, red then the color filter 32c maybe blue, 32b green and 32a red in the display region 28.
Similarly, color filter 30b on the sensing region 26b maybe green and color filter 30c on the sensing region 26c maybe blue that is, the color filters 30a, 30b and 30c are different, Paras [0030] – [0032], Figures 2A-2D, 7, 5A-5B, and 8A-8B).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Chang’s teachings of wherein: the first light emitting element adjacent to one side of the first illuminance sensor in a first direction, and the first color filter is different from the second color filter in the device of Yang in order to increase the aperture ration and reduce the misjudgment.
Regarding claim 9, Yang, as modified by Lee, Kurokawa, Nho, Liu, Wang and Chang, teaches the limitations of claim 8 as mentioned above. Yang does not explicitly teach
“wherein: the color filter further comprises a third color filter overlapping a light receiving
element of a third illuminance sensor among the illuminance sensors and a fourth color filter overlapping a second light emitting element among the light emitting elements, the second light emitting element adjacent to one side of the third illuminance sensor in the first direction in the plan view, and the third color filter is same as the fourth color filter”.
In a similar field of endeavor Chang teaches
wherein: the color filter further comprises a third color filter overlapping a light receiving
element of a third illuminance sensor among the illuminance sensors and a fourth color filter overlapping a second light emitting element among the light emitting elements, the second light emitting element adjacent to one side of the third illuminance sensor in the first direction in the plan view, and the third color filter is same as the fourth color filter (see e.g., Figure 2A shows for example, color filter 30b in the sub pixel 41 of the sensing region 26b to be the same as color filter 32b of the sub pixel 42 of the display region in the horizontal direction. Similarly, color filter 30c in the sub pixel 41 of the sensing region 26c is the same as the color filter 32c in the sub pixel 41 of the display region 28 in the vertical direction, Figures 2A-2D, 7, 5A-5B, and 8A-8B).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Chang’s teachings of wherein: the color filter further comprises a third color filter overlapping a light receiving element of a third illuminance sensor among the illuminance sensors and a fourth color filter overlapping a second light emitting element among the light emitting elements, the second light emitting element adjacent to one side of the third illuminance sensor in the first direction in the plan view, and the third color filter is same as the fourth color filter in the device of Yang in order to increase the aperture ration and reduce the misjudgment.
Regarding claim 12, Yang, as modified by Lee, Kurokawa, Nho, Liu, Wang and Chang, teaches the limitations of claim 8 as mentioned above. Yang does not explicitly teach
“wherein a size of the emission area of the first light emitting element is smaller than a size of the emission area of a second light emitting element that emits light in a same color as that of light emitted by the first light emitting element and is not adjacent to the illuminance sensors”.
In a similar field of endeavor Chang teaches
wherein a size of the emission area of the first light emitting element is smaller than a size of the emission area of a second light emitting element that emits light in a same color as that of light emitted by the first light emitting element and is not adjacent to the illuminance sensors (see e.g., in Figure 2A for example, sub-pixel 41 of the display region 28 is smaller in size than sub-pixels 42 and 43 of the display region 28. The display regions 41, 42 and 43 however have different color filters 32a, 32b and 32c.
Chang shows in Figures 5A-5C arrangements of M*N sub pixels in each pixel. Other sub-pixel amount may be used, for example two, four, five, six, eight or nine sub-pixels etc. Each pixel has at least m sub-pixels, for example one sub-pixel 41, contains at least one photo sensitive area 26a and at least one effective display area 28, and the others at least n sub-pixels of each pixel, for example each two sub-pixels 42 and 43, only contain at least one effective display area 28.
If for example, there are nine sub-pixels; sub-pixel 41 of the display region (sub-pixel 41 has both sensing region and display region) has a color filter for example green, then among the other sub-pixels (having only display regions) there will be at least one sub-pixel having the same color filter as sub-pixel 41 of the display region that is, green and this pixel may not be adjacent to the sensing region, Para [0029], Figures 2A-2D and 5A-5C).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Chang’s teachings of a size of the emission area of the first light emitting element is smaller than a size of the emission area of a second light emitting element that emits light in a same color as that of light emitted by the first light emitting element and is not adjacent to the illuminance sensors in the device of Yang in order to increase the aperture ration and reduce the misjudgment.
Regarding claim 13, Yang, as modified by Lee, Kurokawa, Nho, Liu, Wang and Chang, teaches the limitations of claim 8 as mentioned above. Yang does not explicitly teach
“further comprising a plurality of scan lines, wherein a same one of the scan lines is connected to the pixel circuit connected to the first light emitting element and to the first illuminance sensor”.
In a similar field of endeavor Wang teaches
further comprising a plurality of scan lines, wherein one of the scan lines is connected to the pixel circuit connected to the first light emitting element and to the first illuminance sensor (see e.g., Figures 3A and 3B show the pixel unit 200 with a pixel circuit receiving the first scan signal G1. Figures 4A and 4B show the photodetector 300 with the transistor T4 which receives a second scan signal G2, Figures Paras [061] – [0066]).
Wang does not explicitly teach a same scan signal for both the pixel circuit and the illuminance sensor however; it would have been obvious to one skilled in the art at the time the invention was effectively filed to connect the pixel circuit and the illuminance sensor to the same scan line in order to reduce device dimensions.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Wang’s teachings of a scan signal for the pixel circuit and the illuminance sensor in order to control the transistors.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Lee, Kurokawa, Nho, Liu, Wang, Chang and further in view of Xu et al. (US 2016/0364037 A1; hereafter Xu).
Regarding claim 10, Yang, as modified by Lee, Kurokawa, Nho, Liu, Wang and Chang, teaches the limitations of claim 9 as mentioned above. Yang does not explicitly teach
“further comprising a transparent insulating layer overlapping a light receiving element of a fourth illuminance sensor among the illuminance sensors and covering a portion of the black matrix”.
In a similar field of endeavor Xu teaches
further comprising a transparent insulating layer overlapping a light receiving element of a third illuminance sensor among the illuminance sensors and covering a portion of the black matrix (see e.g., glass substrate 1 and black matrix 3 overlapping the light sensing elements 4, Para [0036], Figure 3).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Xu’s teachings of a transparent insulating layer overlapping a light receiving element of a third illuminance sensor among the illuminance sensors and covering a portion of the black matrix in the device of Yang in order to reduce structural complexity and high costs of optical type touch panels.
Claims 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Lee, Kurokawa, Nho, Liu, Wang and further in view of Kang et al. (US 2019/0252479 A1; hereafter Kang).
Regarding claim 18, Yang, as modified by Lee, Kurokawa, Nho, Liu and Wang, teaches the limitations of claim 17 as mentioned above. Yang does not explicitly teach
“wherein the capacitor comprises a capacitor electrode pattern disposed on a same level, on which the first gate electrode is disposed and overlaps the first active pattern”.
A rearrangement or parts is held to be an obvious matter of design choice. See In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950) (Claims to a hydraulic power press which read on the prior art except with regard to the position of the starting switch were held unpatentable because shifting the position of the starting switch would not have modified the operation of the device.); See also In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975) (the particular placement of a contact in a conductivity measuring device was held to be an obvious matter of design choice).
In a similar field of endeavor Kang teaches
wherein the capacitor comprises a capacitor electrode pattern disposed on a same level, on which the first gate electrode is disposed and overlaps the first active pattern (see e.g., the second capacitor includes the lower electrode Cb1 and the upper electrode Cb2. The lower electrode Cb1 of the second capacitor Cb is at the same level as the gate electrode G1 of the TFT T1 and overlaps the upper electrode Cb2 which is an extension of the active layer of TFT T4, Para [0071], Figure 4)
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Kang’s teachings of the capacitor comprises a capacitor electrode pattern disposed on a same level, on which the first gate electrode is disposed and overlaps the first active pattern in the device of Yang as this would be obvious as a mere arrangement of parts in order to simplify wiring and reduce the footprint of the pixel, manufacturing time and cost.
Regarding claim 19, Yang, as modified by Lee, Kurokawa, Nho, Liu, Wang and Kang, teaches the limitations of claim 18 as mentioned above. Yang does not explicitly teach
“wherein the bias electrode passes through the interlayer insulating layer and the first insulating layer, and is connected to the capacitor electrode pattern”.
In a similar field of endeavor Wang teaches
wherein the bias electrode passes through the interlayer insulating layer and the first insulating layer, and is connected to the capacitor electrode pattern.
Wang shows in Figures 4A and 4B the signal line (equivalent to 350 of Figure 1B) with the constant voltage VO connected to the photo-detecting device 310 and also to the electrode of capacitor 320.
Wang’s Figure 4A/B is equivalent to Applicant’s sensor circuitry shown in Figure 3.
Wang does not explicitly show in Figure 1B the signal line 350 being connected to capacitor electrode 321. However, inherently in order to form the circuitry shown in Figure 4A/B the contact via would pass through the signal line 350 and the insulating layers to connect to the capacitor electrode 320.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Wang’s teachings of connect the bias electrode to the capacitor electrode in the device of Yang for the proper functioning of the sensor element.
Conclusion
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/FAKEHA SEHAR/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893