DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment with respect to claims 1, 3, 5, 25-26, 29-31, and 34, filed on 01/12/2026 have been fully considered for examination based on their merits. The previously presented claims 2, 4, 6, 21, 24, and 33 have been considered. New claim 37 has been considered and entered. Claims 7-20, 22-23, 27-28, and 32, and 35-36 are canceled.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-6, 21, 24-26, 29-31, 33-34, and 37 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-6, 21, 24-26, 29-31, 33-34, and 37 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miao Wang et al, (hereinafter WANG), US 20210175283 A1, in view of Karl Heinz Priewasser, (hereinafter PRIEWASSER, US 20160254188 A1.
Regarding Claim 1, WANG teaches a method of manufacturing an electrical package (Figs. 3.1a-3.4c, manufacturing operations of a flexible integrated array sensor with a function array having a single-function, [0012]), comprising:
providing a semiconductor wafer (Figs. 3.1a/3.1b, 100, silicon wafer, [0033]) having a backside surface (annotated Figure 3.1a) and an active surface (annotated Figure 3.1a) opposite to the backside surface (annotated Figure 3.1a), wherein electrical terminals (Fig. 3.1b, 221/222, conductive tungsten plug) are formed over the active surface (annotated Figure 3.1b), and the semiconductor wafer (Figs. 3.1a/3.1b, 100, silicon wafer, [0033]) comprises a plurality of electronic units having integrated circuits (Fig. 3.1d, 231, piezoelectric sensing unit, [0027]);
forming a removable layer (Fig. 3.1f, 250/240, layer of polymer/first connecting metal, [0040]) on the active surface (annotated Figure 3.1a) of the semiconductor wafer (Figs. 3.1a/3.1f, 100, silicon wafer);
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performing a half-cut operation (Fig. 3.2 S2, ion beam etching/reactive ion etching technique is used to etching one or more deep grooves, 110, [0041]) on the removable layer (Fig. 3.2, 250/240, layer of polymer/first connecting metal, [0040]) to form a trench (Fig. 3.2 110, deep grooves, [0044]) penetrating the removable layer (Fig. 3.2, 250/240, layer of polymer/first connecting metal, [0040]) and the semiconductor wafer (Fig. 3.2, 100, silicon wafer);
disposing a tape (Fig. 3.3c, 310, bonding material, [0042]) on the removable layer (Fig. 3.3b, 250/240, layer of polymer/first connecting metal, [0040]); and
performing a removing operation on the backside surface of the semiconductor wafer (Fig. 3.3d, S3, thinning the bottom surface of silicon wafers, 100 include grinding, chemical mechanical polishing, wet etching, plasma etching and dry polishing, [0042]) to separate the plurality of electronic units (annotated Figure 3.3d) thereby defining a plurality of dies from the plurality of electronic units (annotated Figure 3.3d);
disposing the plurality of dies (annotated Figure 3.3d) on a supporter, wherein the supporter has no electrical functions (Figs. 3.3c-3.4b, 300, support wafer, [0042]);
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removing the tape (Figs. 3.4b-3.4c, S4, 310, bonding material, [0042]);
removing the supporter (Figs. 3.4b-3.4c, S4, 300, support wafer, [0042]).
WANG does not disclose a method of manufacturing an electrical package, comprising: the plurality of dies attached to the tape by separate removable layers; removing the removable layer to expose the electrical terminals.
PRIEWASSER teaches a method of manufacturing an electrical package (Figs 1-13, wafer dividing method, [0075-0087]), comprising: the plurality of dies (Fig. 11, 23, [0133]) attached to the tape (Fig. 12, 24, adhesive pick-up tape, [0136]) by separate removable layers (Figs. 12/13, 4/7, adhesive tape/hard carrier, [0136-0137]); removing the removable layer (Figs. 12/13, 4/7, adhesive tape/hard carrier, [0136-0137]) to expose the electrical terminals (Figs. 13/1, 14, bumps).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified WANG to incorporate the teachings of PRIEWASSER, such that a method of manufacturing an electrical package, comprising: the plurality of dies attached to the tape by separate removable layers; removing the removable layer to expose the electrical terminals, so the individual separated dies (23) can be picked up from the adhesive pick-up tape (24) by a pick-up device (PRIEWASSER, Figure 13, [0138]).
Regarding Claim 2, WANG as modified by PRIEWASSER teaches the method of Claim 1.
WANG further teaches the method (Figs. 3.1a-3.4c, manufacturing operations of a flexible integrated array sensor with a function array having a single-function, [0012]), wherein the trench (Fig. 3.2, 110, deep grooves) is covered by the tape (Figs. 3.4b-3.4c, S4, 310, bonding material, [0042]) after disposing (Fig. 3.3a, S3, [0037]) the tape (Figs. 3.4b-3.4c, S4, 310, bonding material, [0042]).
Regarding Claim 3, WANG as modified by PRIEWASSER teaches the method of Claim 1.
WANG further teaches the method (Figs. 3.1a-3.4c, manufacturing operations of a flexible integrated array sensor with a function array having a single-function, [0012]), further comprising: providing a redistribution structure (Fig. 3.1a, 211, readout circuit units, [0023]) on the active surface (annotated Figure 3.1a) of the semiconductor wafer (Figs. 3.1a/3.1b, 100, silicon wafer, [0033]), wherein the redistribution structure (Fig. 3.1a, 211, readout circuit units, [0023]) is covered by the semiconductor wafer (Figs. 3.1a/3.3d, 100, silicon wafer, [0033]) after the removing operation (Fig. 3.3d, S3, thinning the bottom surface of silicon wafers, 100 include grinding, chemical mechanical polishing, wet etching, plasma etching and dry polishing, [0042]) is performed.
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Regarding Claim 4, WANG as modified by PRIEWASSER teaches the method of Claim 3.
WANG further teaches the method (Figs. 3.1a-3.4c, manufacturing operations of a flexible integrated array sensor with a function array having a single-function, [0012]), wherein the removable layer (Fig. 3.1f, 250/240, layer of polymer/first connecting metal, [0040]) is formed (Fig. 3.1f, S1, 250/240, layer of polymer/first connecting metal, [0033-0035]) before the half-cut (Fig. 3.2 S2, ion beam etching/reactive ion etching technique is used to etching one or more deep grooves, 110, [0036], [0041]).
Regarding Claim 5, WANG as modified by PRIEWASSER teaches the method of Claim 1.
WANG further teaches the method (Figs. 3.1a-3.4c, manufacturing operations of a flexible integrated array sensor with a function array having a single-function, [0012]), wherein performing the removing operation comprises grinding the backside surface of the semiconductor wafer (Fig. 3.3d, S3, thinning the bottom surface of silicon wafers, 100 include grinding, chemical mechanical polishing, wet etching, plasma etching and dry polishing, [0042], [0044]) to separate the plurality of electronic units (annotated Figure 3.3d), and wherein no cut operation (Figs. 3.3a-3.4c, from S3 to S4, no further deep groove formation is demonstrated, [0043]) is performed after the grinding the semiconductor wafer (Fig. 3.3d, S3, thinning the bottom surface of silicon wafers, 100 include grinding, chemical mechanical polishing, wet etching, plasma etching and dry polishing, [0042], [0044]).
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Regarding Claim 6, WANG as modified by PRIEWASSER teaches the method of Claim 1.
WANG further teaches the method (Figs. 3.1a-3.4c, manufacturing operations of a flexible integrated array sensor with a function array having a single-function, [0012]), wherein the removable layer (Fig. 3.1f, 250/240, layer of polymer/first connecting metal, [0040]) is in direct contact with the tape (Fig. 3.3a, 270, top polymer substrate layer, [0037]; Figs. 3.4b-3.4c, S4, 310, bonding material, [0042]).
Regarding Claim 21, WANG as modified by PRIEWASSER teaches the method of Claim 1.
WANG further teaches the method (Figs. 3.1a-3.4c, manufacturing operations of a flexible integrated array sensor with a function array having a single-function, [0012]), wherein the half-cut operation is (Fig. 3.2 S2, ion beam etching/reactive ion etching technique is used to etching one or more deep grooves, 110, [0041]) performed before disposing the tape (Fig. 3.3a, S3, 270, top polymer substrate layer, [0037], [0043]).
Regarding Claim 24, WANG as modified by PRIEWASSER teaches the method of Claim 1.
WANG further teaches the method (Figs. 3.1a-3.4c, manufacturing operations of a flexible integrated array sensor with a function array having a single-function, [0012]), wherein a thickness of the tape (Figs. 3.4b-3.4c, S4, 310, bonding material, [0042]) is less than (annotated Figure 3.3c) thickness of the removable layer (Fig. 3.1f, 250/240, layer of polymer/first connecting metal, [0040]).
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Regarding Claim 25, WANG as modified by PRIEWASSER teaches the method of Claim 1.
WANG further teaches the method (Figs. 3.1a-3.4c, manufacturing operations of a flexible integrated array sensor with a function array having a single-function, [0012]), wherein the trench (Fig. 3.2, 110, deep grooves) is enclosed (annotated Figure 3D) by the supporter (Figs. 3.4b-3.4c, S4, 300, support wafer, [0042]) and the tape (Figs. 3.4b-3.4c, S4, 310, bonding material, [0042]).
Regarding Claim 26, WANG as modified by PRIEWASSER teaches the method of Claim 1.
WANG further teaches the method (Figs. 3.1a-3.4c, manufacturing operations of a flexible integrated array sensor with a function array having a single-function, [0012]), wherein the semiconductor wafer (Figs. 3.1a/3.1b, 100, silicon wafer, [0033]) comprises a redistribution structure (Fig. 3.1a, 211, readout circuit units, [0023]) adjacent to the active surface (annotated Figure 3.1a), and a lateral surface (annotated Figure 3.1a) of the redistribution structure (Fig. 3.1a, 211, readout circuit units, [0023] ; annotated Figure 3.2) is exposed (annotated Figure 3.1a) to the trench (Fig. 3.2, 110, deep grooves).
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Regarding Claim 29, WANG as modified by PRIEWASSER teaches the method of Claim 26.
WANG further teaches the method (Figs. 3.1a-3.4c, manufacturing operations of a flexible integrated array sensor with a function array having a single-function, [0012]), wherein a portion (annotated Figure 3.2) of the redistribution structure (Fig. 3.1a, 211, readout circuit units, [0023] ; annotated Figure 3.2) is removed (annotated Figure 3.2) by the half-cut operation (Fig. 3.2 S2, ion beam etching/reactive ion etching technique is used to etching one or more deep grooves, 110, [0041]).
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Regarding Claim 30, WANG as modified by PRIEWASSER teaches the method of Claim 6.
WANG further teaches the method (Figs. 3.1a-3.4c, manufacturing operations of a flexible integrated array sensor with a function array having a single-function, [0012]), wherein the semiconductor wafer (Figs. 3.1a/3.1b, 100, silicon wafer, [0033]) comprises a redistribution structure (Fig. 3.1a, 211, readout circuit units, [0023]; annotated Figure 3.2) adjacent to the active surface (annotated Figure 3.1a), and the trench (Fig. 3.2, 110, deep grooves) passes through (annotated Figure 3.2) the redistribution structure (Fig. 3.1a, 211, readout circuit units, [0023]).
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Regarding Claim 31, WANG as modified by PRIEWASSER teaches the method of Claim 6.
WANG further teaches the method (Figs. 3.1a-3.4c, manufacturing operations of a flexible integrated array sensor with a function array having a single-function, [0012]), wherein a vertical length of the tape (Fig. 3.3c, 310, bonding material; annotated Figure 3.3c) is less than (annotated Figure 3.3c) that of the removable layer (Fig. 3.2, 250/240, layer of polymer/first connecting metal, [0040]) in a cross-sectional view (Fig. 3.3c, [0037]).
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PRIEWASSER further teaches a method of manufacturing an electrical package (Figs 1-13, wafer dividing method, [0075-0087]), wherein a lateral length (annotated Figure 12) of the supporter (Fig. 12, 24, adhesive pick-up tape, [0136]) is greater than that of the tape (Figs. 12/13, 4/7, adhesive tape/hard carrier, [0136-0137]).
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Regarding Claim 33 WANG as modified by PRIEWASSER teaches the method of Claim 1.
PRIEWASSER further teaches a method of manufacturing an electrical package (Figs 1-13, wafer dividing method, [0075-0087]), wherein the removable layer (Figs. 12/13, 4/7, adhesive tape/hard carrier, [0136-0137]) comprises a liquid glue and is removed by a de-glue solution ([0113-0114], [0121]).
Regarding Claim 34, WANG as modified by PRIEWASSER teaches the method of Claim 1.
PRIEWASSER further teaches a method of manufacturing an electrical package (Figs 1-13, wafer dividing method, [0075-0087]), wherein the separated removable layers (Figs. 12/13, 4/7, adhesive tape/hard carrier, [0136-0137]) are removed ([0137]) to expose the electrical terminals (Figs. 13/1, 14, bumps).
Regarding Claim 37, A method of manufacturing an electrical package, comprising:
providing a semiconductor wafer (Figs. 3.1a/3.1b, 100, silicon wafer, [0033]) having a backside surface (annotated Figure 3.1a) and an active surface (annotated Figure 3.1a) opposite to the backside surface (annotated Figure 3.1a), wherein electrical terminals (Fig. 3.1b, 221/222, conductive tungsten plug) are formed over the active surface (annotated Figure 3.1b), and the semiconductor wafer (Figs. 3.1a/3.1b, 100, silicon wafer, [0033]) comprises a plurality of electronic units having integrated circuits (Fig. 3.1d, 231, piezoelectric sensing unit, [0027]);
forming a removable layer (Fig. 3.1f, 250/240, layer of polymer/first connecting metal, [0040]) on the active surface (annotated Figure 3.1a) of the semiconductor wafer (Figs. 3.1a/3.1f, 100, silicon wafer);
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performing a half-cut operation (Fig. 3.2 S2, ion beam etching/reactive ion etching technique is used to etching one or more deep grooves, 110, [0041]) on the removable layer (Fig. 3.2, 250/240, layer of polymer/first connecting metal, [0040]) to form a trench (Fig. 3.2 110, deep grooves, [0044]) penetrating the removable layer (Fig. 3.2, 250/240, layer of polymer/first connecting metal, [0040]) and the semiconductor wafer (Fig. 3.2, 100, silicon wafer);
disposing a tape (Fig. 3.3c, 310, bonding material, [0042]) on the removable layer (Fig. 3.3b, 250/240, layer of polymer/first connecting metal, [0040]); and
grinding the backside surface of the semiconductor wafer (Fig. 3.3d, S3, thinning the bottom surface of silicon wafers, 100 include grinding, chemical mechanical polishing, wet etching, plasma etching and dry polishing, [0042]) to the extent of revealing the trench (Fig. 3.2 110, deep grooves, [0044]) penetrating to separate the plurality of electronic units (annotated Figure 3.3d) thereby defining a plurality of dies from the plurality of electronic units (annotated Figure 3.3d);
disposing the plurality of dies (annotated Figure 3.3d) on a supporter, wherein the supporter has no electrical functions (Figs. 3.3c-3.4b, 300, support wafer, [0042]);
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removing the tape (Figs. 3.4b-3.4c, S4, 310, bonding material, [0042]);
removing the supporter (Figs. 3.4b-3.4c, S4, 300, support wafer, [0042]).
WANG does not disclose a method of manufacturing an electrical package, comprising: the plurality of dies attached to the tape by separate removable layers; removing the removable layer to expose the electrical terminals.
PRIEWASSER teaches a method of manufacturing an electrical package (Figs 1-13, wafer dividing method, [0075-0087]), comprising: the plurality of dies (Fig. 11, 23, [0133]) attached to the tape (Fig. 12, 24, adhesive pick-up tape, [0136]) by separate removable layers (Figs. 12/13, 4/7, adhesive tape/hard carrier, [0136-0137]); removing the removable layer (Figs. 12/13, 4/7, adhesive tape/hard carrier, [0136-0137]) to expose the electrical terminals (Figs. 13/1, 14, bumps).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified WANG to incorporate the teachings of PRIEWASSER, such that a method of manufacturing an electrical package, comprising: the plurality of dies attached to the tape by separate removable layers; removing the removable layer to expose the electrical terminals, so the individual separated dies (23) can be picked up from the adhesive pick-up tape (24) by a pick-up device (PRIEWASSER, Figure 13, [0138]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20050148160 A1 – Figure 15F
STATEMENT OF RELEVANCE – Singulating step is performed by attaching a dicing tape to the back side coat table, [0246].
US 20170162556 A1 – Figures 14-15
STATEMENT OF RELEVANCE – Cross-sectional and bottom perspective views respectively of an individual subassembly that includes a first routing circuitry, first semiconductor devices, second vertical connecting elements, a balance layer and an anti-warping controller.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SESHA SAIRAMAN SRINIVASAN whose telephone number is (703)756-1389. The examiner can normally be reached Monday-Friday 7:30 AM -5:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
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