Prosecution Insights
Last updated: July 17, 2026
Application No. 17/507,201

LIGHT EMITTING DIODE PACKAGES

Non-Final OA §103
Filed
Oct 21, 2021
Priority
Jan 16, 2019 — divisional of 11/189,766
Examiner
LI, MEIYA
Art Unit
2811
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
CreeLED Inc.
OA Round
7 (Non-Final)
69%
Grant Probability
Favorable
7-8
OA Rounds
0m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 69% — above average
69%
Career Allowance Rate
641 granted / 931 resolved
+0.9% vs TC avg
Strong +26% interview lift
Without
With
+25.5%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
50 currently pending
Career history
982
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
65.6%
+25.6% vs TC avg
§102
15.9%
-24.1% vs TC avg
§112
15.3%
-24.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 931 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on May 22, 2026 has been entered. Claim Rejections - 35 USC § 103 The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claim(s) 1-6 and 9-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamada al. (2016/0260873) in view of Kim et al. (2019/0058089). As for claim 1, Yamada et al. show in Fig. 8 and related text a light emitting diode (LED) package 600, comprising: an LED chip 14 comprising a first face, a second face, and a chip sidewall therebetween, and a first contact 13 (left) and a second contact 13 (right); a lead frame 12 comprising a first lead frame portion 12 (left) and a second lead frame portion 12 (right), wherein the first contact is attached to the first lead frame portion and the second contact is attached to the second lead frame portion; an insulating material 11 at least partially surrounding the lead frame, the insulating material forming a recess with recess sidewalls such that the LED chip resides within the recess; a underfill material 16 arranged between the LED chip and the lead frame, wherein an interface between the first contact and the first lead frame portion and another interface between the second contact and the second lead frame portion are devoid of the underfill material, and wherein the underfill material covers a portion of the chip sidewall and extends from the chip sidewall to the recess sidewalls; and an encapsulant material 17/18/19/20 arranged on the LED chip and the underfill material, the encapsulant material filling the recess between the underfill material and the recess sidewalls. Yamada et al. do not disclose the first lead frame portion and the second lead frame portion are accessible outside the insulating material for receiving external electrical connections. Kim et al. teach in Fig. 1 and related text the first lead frame portion 121 and the second lead frame portion 122 are accessible outside the insulating material 130 for receiving external electrical connections. Yamada et al. and Kim et al. are analogous art because they are directed to a LED package and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yamada et al. with the specified feature(s) of Kim et al. because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to include the first lead frame portion and the second lead frame portion being accessible outside the insulating material for receiving external electrical connections, as taught by Kim et al., in Yamada et al.'s device, in order to reduce heat dissipation of the device and provide external connections. As for claim 2, the combined device shows the first contact of the LED chip is flip-chip mounted to the first lead frame portion, and the second contact of the LED chip is flip-chip mounted to the second lead frame portion (Yamada: Fig. 8; [0077]). As for claim 3, the combined device shows the underfill material is arranged between the first lead frame portion and the second lead frame portion (Yamada: Fig. 8). As for claim 4, the combined device shows the underfill material is arranged between the first contact of the LED chip and the second contact of the LED chip (Yamada: Fig. 8). As for claim 5, the combined device shows the underfill material is arranged between lateral edges of the LED chip and the lead frame (Yamada: Fig. 8). As for claim 6, the combined device shows the underfill material is configured to redirect light from the LED chip away from the lead frame (Yamada: [0082]). As for claim 9, the combined device shows the underfill material comprises epoxy (Yamada: [0086]). As for claim 10, the combined device shows the underfill material comprises a material with a durometer value on a Shore D hardness scale that is higher than a durometer value of the encapsulant material (Yamada: [0081]: epoxy; [0085]: phenyl silicone; note: epoxy has a higher durometer value on a Shore D hardness than phenyl silicone). As for claim 11, the combined device shows the underfill material comprises a material with a durometer value on a Shore D hardness scale of at least 40 (Yamada: [0081]; note: the durometer value on a Shore D hardness scale of epoxy is in range from 70-90). As for claim 12, the combined device shows the durometer value is in a range from 40 to 100 (Yamada: [0081]; note: the durometer value on a Shore D hardness scale of epoxy is in range from 70-90). As for claim 13, the combined device shows recess sidewalls comprise reflective sidewalls (Yamada: Fig. 8; [0161]). Claim(s) 7 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamada et al. (2016/0260873) and Kim et al. (2019/0058089) in view of Ikeda et al. (2017/0092817). As for claim 7, Yamada et al. and Kim et al. disclosed substantially the entire claimed invention, as applied to claim 1 above, except the underfill material comprises titanium dioxide (TiO2). Ikeda et al. teach in Fig. 11 and related text the underfill material 205 comprises titanium dioxide (TiO2) ([0150]). Yamada et al., Kim et al. and Ikeda et al. are analogous art because they are directed to a semiconductor package and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yamada et al. and Kim et al. with the specified feature(s) of Ikeda et al. because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to include the underfill material comprising titanium oxide, as taught by Ikeda et al., in Yamada et al. and Kim et al.’s device, in order to improve the light extraction efficiency of the device. As for claim 8, the combined device shows the underfill material further comprises silicone (Yamada: [0081]; Ikeda: [0150]). Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamada et al. (2016/0260873) and Kim et al. (2019/0058089) in view of Puschner et al. (2006/0049532). Yamada et al. and Kim et al. disclosed substantially the entire claimed invention, as applied to claim 1 above, except the underfill material comprises a material with a durometer value on a Shore D hardness scale that is higher than a durometer value of the encapsulant material. Puschner et al. teach in Fig. 1 and related text the underfill material 3 comprises a material with a durometer value on a Shore D hardness scale that is higher than a durometer value of the encapsulant material 6 ([0019], [0022], [0033] and [0040]). Yamada et al., Kim et al. and Puschner et al. are analogous art because they are directed to a semiconductor package and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yamada et al. and Kim et al. with the specified feature(s) of Puschner et al. because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to include the underfill material comprising a material with a durometer value on a Shore D hardness scale that being higher than a durometer value of the encapsulant material, as taught by Puschner et al., in Yamada et al. and Kim et al.'s device, in order to provide a better flexibility, prevent the device from cracking and improve the performance of the device. Response to Arguments Applicant’s arguments with respect to claim(s) 1-13 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MEIYA LI whose telephone number is (571)270-1572. The examiner can normally be reached Monday-Friday 7AM-3PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LYNNE GURLEY can be reached on (571)272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MEIYA LI/Primary Examiner, Art Unit 2811
Read full office action

Prosecution Timeline

Show 14 earlier events
Feb 05, 2026
Examiner Interview Summary
Feb 05, 2026
Applicant Interview (Telephonic)
Feb 06, 2026
Response Filed
Feb 26, 2026
Final Rejection mailed — §103
Apr 21, 2026
Response after Non-Final Action
May 22, 2026
Request for Continued Examination
May 26, 2026
Response after Non-Final Action
Jun 29, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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METHOD OF MANUFACTURING LIGHT-EMITTING ELEMENT AND LIGHT-EMITTING ELEMENT
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Patent 12652835
MULTILAYER WORK FUNCTION METAL IN NANOSHEET STACKS USING A SACRIFICIAL OXIDE MATERIAL
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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

7-8
Expected OA Rounds
69%
Grant Probability
94%
With Interview (+25.5%)
3y 7m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 931 resolved cases by this examiner. Grant probability derived from career allowance rate.

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