DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 16 January 2026 has been entered and prosecution reopened.
Response to Arguments
Applicant’s arguments/amendments, see Remarks/Claims, filed 16 January 2026, with respect to the rejection(s) of the claim(s) in the previous Office action have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Sung-Bong Kim (US 6448651 B1).
The indicated allowability of claims 1, 3, and 4 is withdrawn in view of the newly discovered reference Sung-Bong Kim (US 6448651 B1). Rejections based on the newly cited reference(s) follow.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 4, 10, 11, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Sung-Bong Kim (US 6448651 B1; hereinafter Kim) in view of Yun Yu Wang et al. (US 20040018680 A1; hereinafter Wang).
Regarding Claim 1, Kim discloses a manufacture method of an interconnection structure (Fig. 3a, 3b, 3c, and 4; entire disclosure) comprising:
forming a first dielectric layer (106; C5:L66) over a first conductive terminal (conductive active area 104; C7:L24-L28), wherein an open hole (Fig. 3a; h2) is defined in the first dielectric layer (106);
forming a conductor pillar (108b/118b; C10:L18) comprising a first conductor pillar portion (108b) surrounded by the first dielectric layer (106) and penetrating through the open hole of the first dielectric layer (as shown in Fig. 3c) and a second conductor pillar portion (118b) comprising a semiconductor material (C7:L14-L15), wherein the conductor pillar is electrically connected to the first conductive terminal (104) but not electrically connected to a first conduction layer (110/112; C10:L19-22) over the first dielectric layer (106) (as shown in Fig. 3c/4), wherein an opening hollow (hollow between 110/112 shown in Fig. 3c; hereinafter OH) is defined in the first conduction layer (110/112), and the conductor pillar (108b/118b) passes through the opening hollow (OH) of the first conduction layer (110/112) such that the conductor pillar is not electrically connected to the first conduction layer (as shown in Fig. 3c/4); wherein a dimension of the open hole (h2) is different from a dimension of the opening hollow (OH) (as shown in Fig. 3a and Fig. 3c);
forming an upper dielectric layer (114; C7:L1-L4) over the first conduction layer (110/112) and surrounding the second conductor pillar portion (118b); and
forming an upper conduction layer (122; C7:L18-L22) over the upper dielectric layer (114), wherein the second conductor pillar portion (118b) of the conductor pillar is connected to the upper conduction layer (122); wherein the second conductor pillar portion (118b) has a top surface higher than a top surface of the upper dielectric layer (114) (as shown in Fig. 3c); the first conductor pillar portion (118b) is self-aligned with the second conductor pillar portion (108b), and a bottom area of the second conductor pillar portion is equal to an upper area of the first conductor pillar portion (as shown in Fig. 3c).
Kim is silent regarding the semiconductor material being epitaxial.
In the same field of endeavor, Wang teaches an epitaxially grown polysilicon stud/pillar for the purpose of a semiconductor device conductive contact/via (see disclosure of Wang).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the polysilicon first and second conductor pillar portions of Kim (108b/118b) via the epitaxy method of Wang in order to provide a conductive feature that has much better contact resistance than non-epitaxial grown poly-silicon (as described in Wang; ¶0071).
Regarding Claim 3, modified Kim discloses the manufacture method according to claim 1, wherein the step of forming the conductor pillar (108b/118b) comprises:
forming the open hole (h2) in the first dielectric layer (106) to reveal the first conductive terminal (104) (as shown in Fig. 3a);
forming the first conductor pillar portion (108b) on the revealed first conductive terminal (104) (as shown in Fig. 3a → Fig. 3b), wherein a semiconductor seed portion on the first conductor pillar portion (as modified the top portion of 108b implicitly is a seed portion for epitaxially grown 118b);
forming the first conduction layer (110/112) over the first dielectric layer (106); and
forming the second conductor pillar portion (118b) on the semiconductor seed portion (top of 108b) (as shown in Fig. 3b → Fig. 3c).
Regarding Claim 4, modified Kim teaches the manufacture method according to claim 3, the step of forming the first conductor pillar portion (108b) comprising:
forming the first conductor pillar portion (108b) by a first selective epitaxy growth method based on a seed portion (top of 104 which is a semiconductor; C5:L62 – C6:L5) of the first conductive terminal (104) (as modified by Wang this is implicitly satisfied as 108b is formed via epitaxy from a seed portion at the top of 104 exposed in the hole h2).
Regarding Claim 10, Kim discloses a manufacture method of an interconnection structure (Fig. 3a, 3b, 3c, and 4; entire disclosure) comprising:
forming a first dielectric layer (106; C5:L66) over a first conductive terminal (conductive active area 104; C7:L24-L28);
forming a first conductor pillar portion (108b; C10:L18) surrounded by the first dielectric layer (106), wherein the first conductor pillar portion extends upward passing through the first dielectric layer (106) and connected to the first conductive terminal (104) (as shown in Fig. 3b);
by selective formation, forming a second conductor pillar portion (118b; C10:L18) made of semiconductor material (C7:L14-L15) and based on a top surface of the first conductor pillar portion (top of 108b, as shown in Fig. 3c which is selective in that it is formed in the hole only and not blanket deposited and polished back), wherein a bottom area of the second conductor pillar portion is equal to an upper area of the first conductor pillar portion (as shown in Fig. 3c);
forming a first conduction layer (110/112; C10:L19-22) with an opening hollow (hollow between 110/112 shown in Fig. 3c; hereinafter OH) over the first dielectric layer (106), wherein the second conductor pillar portion (118b) passes though the opening hollow (OH) and not electrically connected to the first conduction layer (110/112 as shown in Fig. 3c/4);
forming a second dielectric layer (114/116; C7:L1-L4) over the first conduction layer (110/112) and filling in the opening hollow (OH; as seen in Fig. 3c); and
forming a second connection layer (122; C7:L18-L22) laterally extending and over the second dielectric layer (114/116), wherein the second connection layer (122) directly contacts to the top surface of the second conductor pillar portion (118b) (as shown in Fig. 3c/4).
Kim is silent regarding forming the semiconductor material by epitaxial growth.
In the same field of endeavor, Wang teaches an epitaxially grown polysilicon stud/pillar for the purpose of a semiconductor device conductive contact/via (see disclosure of Wang).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the polysilicon first and second conductor pillar portions of Kim (108b/118b) via the epitaxy method of Wang in order to provide a conductive feature that has much better contact resistance than non-epitaxial grown poly-silicon (as described in Wang; ¶0071).
Regarding Claim 11, modified Kim teaches the manufacture method according to claim 10, but Kim is silent regarding wherein the first conductor pillar portion (silicon 108b) is made of doped silicon.
In the same field of endeavor, Wang teaches silicon may be doped in situ during growth to lower contact resistance and enhance operational stability (¶0018).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the silicon first conductor pillar portion (108b) of Kim be doped silicon as in Wang in order to lower contact resistance and enhance operational stability (Wang; ¶0018).
Regarding Claim 15, modified Kim teaches the manufacture method according to claim 10, the step of forming the first conductor pillar portion (108b) comprising:
forming open holes (Fig. 3a; h2) in the first dielectric layer (106) to reveal a first seed region of the first terminal (top seed region of exposed 104 in h2, wherein it acts as a seed portion as modified by the formation method of Wang); and by selective epitaxy growth, forming the first conductor pillar portion based on the revealed first seed region (104 revealed by h2) of the first terminal (104) (wherein this is implicitly satisfied by the modification of Wang in claim 10 above).
Allowable Subject Matter
Claim 12 is allowed.
Claims 5-9 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the objected to claim, the base claim, and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 5, modified Kim teaches the manufacture method according to claim 3. However, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the Examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, all the limitations of the instant invention in their entirety (the individual limitations may be found just not in combination with proper motivation); further including:
before the step of forming the first conduction layer (110/112), further comprising: forming a first dielectric sub-layer over the first dielectric layer; planarizing the first dielectric sub-layer and the first conductor pillar portion, wherein a top surface of the first dielectric sub-layer has a level substantially the same as that of the first conductor pillar portion.
Regarding Claim 6, modified Kim teaches the manufacture method according to claim 3, wherein the step of forming the first conduction layer comprises:
depositing the first conduction layer (110/112) over the first dielectric layer (106); depositing a second dielectric sub-layer (116; L38-L40) over the first conduction layer (110/112).
However, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the Examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, all the limitations of the instant invention in their entirety (the individual limitations may be found just not in combination with proper motivation); further including:
patterning the first conduction layer and the second dielectric sub-layer to define the opening hollow.
For at least this reason, claims 7-9 would also be allowable based on their dependency from claim 6.
Regarding Claim 12, the closest prior art of record (see previous Office Actions such as in view of Parekh) teaches a manufacture method of an interconnect structure comprising:
forming a first conductor pillar (Fig. 5A; 86) surrounded by a first dielectric layer (20), wherein the first conductor pillar extends upward passing through the first dielectric layer and connected to a first conductive terminal (40), and a top surface of the first conductor pillar (86) is higher than a top surface of the first dielectric layer (20; as shown in Fig. 5A); and
forming a first connection layer (104) laterally extending and over the first dielectric layer, wherein the first connection layer directly contacts to the top surface of the first conductor pillar (86).
However, to the examiner’s knowledge, the prior art does not teach or render obvious, at least to the skilled artisan, all the limitations of the instant invention in their entirety (the individual limitations may be found just not in combination with proper motivation); further including:
wherein the first conductor pillar comprises a tungsten pillar, a TiN layer surrounding the tungsten pillar, and a semiconductor seed portion is on a top of the tungsten pillar; wherein the seed portion is made of doped silicon and the first connection layer is electrically connected to the tungsten pillar through the seed portion.
Regarding Claim 14, modified Kim teaches the manufacture method according to claim 10. However, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the Examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, all the limitations of the instant invention in their entirety (the individual limitations may be found just not in combination with proper motivation); further including:
forming a first dielectric sub-layer over the first dielectric layer; and planarizing the first dielectric sub-layer and the first conductor pillar portion such that a top surface of the first dielectric sub-layer has a level substantially the same as that of the-first conductor pillar portion.
Conclusion
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NATHAN PRIDEMORE
Examiner
Art Unit 2898
/NATHAN PRIDEMORE/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898