DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on February 13, 2026 has been entered.
Status of the Claims
Species 1, as shown in FIGs. 2A-5, was elected.
Amendment filed February 13, 2026 is acknowledged. Claims 1 and 11 have been amended. Non-elected Species, claims 11 and 13-19 have been withdrawn from consideration. Claims 1, 3-5, 7-8, 10-11 and 13-19 are pending.
Action on merits of the Elected Species 1, claims 1, 3-5, 7-8 and 10 follows.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1, 3-5, 7-8 and 10 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Amended claim 1, line 3, recites: “forming isolation trench in termination region”; and lines 14-17, recites: “conducting an oxidation a process to form a dielectric structure having a first dielectric layer and a dielectric area, with the first dielectric layer disposed on the first trenches and the dielectric area surrounding the active region, and the dielectric area at the termination region formed by the same oxidation process of forming the first dielectric layer in the first trenches, …”.
Are these “isolation trench in termination region” and “the dielectric area at the termination region” the same or different structures?
If they are the same, then, why do they have different nomenclatures?
If they are different, then, where is the “isolation trench in termination region” ?
Claimed limitations are contradictory. Therefore, claim 1 and all dependent claims are indefinite.
For the purpose of examination on merits, these two structures are considered as the same.
Amended claim 1, lines 29-31, recites: “conducting an oxide deposition to form a second dielectric layer covering the shield electrode, and the second dielectric layer further including an oxidized layer covering the trench space at the active region and the junction region”.
Two terms “an oxide deposition” and “an oxidized layer” are contradictory, since “oxide deposition” and “oxidized layer” being formed of two different processes, i.e., deposition vs. oxidation.
Claimed limitations are contradictory. Therefore, claim 1 and all dependent claims are indefinite.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 3-5, 7-8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over QIN et al. (US. Pub. No. 2016/0064556) in view of TSURUTA (US. Pub. No. 2005/0012175), GRIVNA (US. Pub. No. 2011/0136310) and GAO et al. (US. Pub. No. 2016/0359018) of record.
With respect to claim 1, As best understood by the Examiner, QUIN teaches a method of forming a power semiconductor device comprising forming isolation trench structure (204) in termination region, substantially as claimed the method including:
providing a semiconductor substrate (202), the semiconductor substrate having an active region and a termination region surrounding the active region;
disposing an epitaxial layer (106) on the semiconductor substrate;
etching the epitaxial layer to form a plurality of first trenches (114, 118) and a second trench (not shown), the first trenches (114, 118) being disposed at the active region and a junction region located between the active region and the termination region, and the second trench (204) being disposed at the termination region, and a second trench depth of the second trench (204) is less than a first trench depth of each of the first trenches (114, 118); (FIG. 8-9)
conducting a process to form a dielectric structure having a first dielectric layer (1002) and a dielectric area (204), with the first dielectric layer (1002) disposed on the first trenches (114, 118) and the dielectric area (204) surrounding the active region, and the dielectric area (204) at the termination region formed by the process of forming the dielectric layer (204) in the trench, wherein side and bottom surfaces of each of the first trenches (114, 118) are covered by the first dielectric layer (1002) to form a trench space in each of the first trenches (114, 118) and second trench is filled and fully covered with a dielectric material (204) to form the dielectric area (204), so the dielectric area (204) has a depth based on the second trench depth and less than the first trench depth of the first trench (118) at the junction region, wherein the dielectric material comprises silicon dioxide, and the first dielectric layer (1002) of the first trench (118) at the junction region is configured to adjacent the dielectric area (204); (FIG. 10)
conducting a deposition process to dispose a shield electrode (1004) in the trench space of the first trench(es) (114, 118) at the active region and the junction region; (FIG. 10) and
conducting an etching to etch the shield electrode (1004) at the active region to preliminarily create a gate electrode forming space; (FIG. 11)
conducting an oxide deposition to form a second dielectric layer (1202) covering the shield electrode (1004), and the second dielectric layer (1202) further including an oxidized layer (1202) covering the trench space at the active region and the junction region;
creating the gate electrode forming space;
conducting a deposition process to dispose a gate electrode (125) filled in the gate electrode forming space of the first trench (114) at the active region;
forming a doped region (306) between the gate electrode (125);
conducting an oxide deposition to form a third dielectric layer (216) covering the active region and the termination region; and
forming a metal layer (326) on the third dielectric layer (216), wherein the metal layer (326) is a source contact of the power semiconductor device, and the metal layer (326) contacts the doped region (306) through a contact hole. (See FIGs. 7-18).
Thus, QUIN is shown to teach all the features of the claim with the exception of explicitly disclosing forming the dielectric area by etching a plurality of second trenches and forming the dielectric structure by conducting an oxidation process, such that the first dielectric layer of the first trench at the junction region abuts the dielectric area; etching the shield electrode utilizing anisotropically etch; and forming the second dielectric layer by oxide deposition.
However, TSURUTA teaches a method of forming a power semiconductor device comprising forming isolation trench structure (2) including:
etching epitaxial layer to form a plurality of first trenches (25) and a plurality of second trenches (24), wherein a second trench width (W1) of the second trenches (24) is less than a first trench width (W3) of the first trenches (25), and a second trench depth (L10) of the second trenches (24) is less than a first trench depth (L11) of the first trench (25); (FIG. 9A)
conducting an oxidation process to form a dielectric structure having a first dielectric layer (27) and a dielectric area (2), with the dielectric layer (27) disposed on the first trenches (25), and the dielectric area (2) formed by the same oxidation process of forming the first dielectric layer (27) in the first trenches (25), wherein side and bottom surfaces of the first trenches (25) are covered by the first dielectric layer (27) to form a trench space (3) in each of the first trenches (25) and each of the second trenches (24) is filled and fully covered with a dielectric material (27) to form the dielectric area (2) so the dielectric area (2) has a depth based on the second trench depth (L11) and less than the first trench depth (L10) of the first trench (25), wherein the dielectric material comprises silicon dioxide, and the first dielectric layer (27) of the first trench (25) is configured to abut the dielectric area (2). (See FIG. 9B).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the isolation trench structure of QIN including forming the plurality of first trenches and the plurality of second trenches, then oxidizing the trenches as taught by TSURUTA to simplify the process by reducing the number of the process steps.
Further, GRIVNA teaches a method of forming a power semiconductor device including:
conducting a deposition process to dispose a shield electrode (440) in the trench space of the first trench(es) (22) at the active region and the junction region; (FIG. 9) and
conducting an anisotropy etching to etch the shield electrode (440) at the active region to preliminarily create a gate electrode forming space. (FIG. 10).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to conduct the etching of the shield electrode of QIN utilizing anisotropic etching as taught by GRIVNA for the same intended purpose of forming the shield electrode.
Furthermore, GAO teaches a method of forming a power semiconductor device including:
conducting an oxide deposition to form a second dielectric layer (1020) covering shield electrode (818), and the second dielectric layer (1020) further including an oxidized layer covering the trench space at active region and junction region; (FIG. 11) and
etching the second dielectric layer (1020) at the active region to further create the gate electrode forming space; (FIG. 12)
conducting a deposition process to dispose a gate electrode (1332) filled in the gate electrode forming space of the first trench (308) at the active region.
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the power semiconductor device of QIN including etching the second dielectric layer to create the second space as taught by GAO to avoid sharp corner being formed.
With respect to claim 3, in view of TSURUTA, the dielectric area (2) has a pattern shape at bottom of the dielectric area (2) and the pattern shape corresponds to a bottom shape of the second trench (24).
With respect to claim 4, in view of TSURUTA, the pattern shape comprises a continuous wave shape or a continuous ripple shape.
With respect to claim 5, in view of TSURUTA, the first trench width (W3) is around 1.2-1.5 m and the second trench width (W1) is around 0.9-1.1pm.
With respect to claim 7, in view of TSURUTA, the first trench depth (111) and the second trench depth (L10) are around 1-50pm.
With respect to claim 8, the termination region of QIN has a termination length and in view of TSURUTA, the termination length (A1) is around 1-200 pm.
It is well settled that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40 ºC and 80 ºC and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100 ºC and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages.").
With respect to claim 10, the epitaxial layer (106) of QIN is N-type lightly doped layer and the doped region (304) is N-type highly doped region.
Response to Arguments
Applicant’s arguments with respect to amended claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/ANH D MAI/ Primary Examiner, Art Unit 2893