DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4-6, 8, 10, 15-16, and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miyoshi (US PGPub 2011/0140199) in view of Chin (US PGPub 2013/0228831) and Hung (US PGPub 2020/0328592).
Regarding claims 1 and 21, Miyoshi discloses in Fig. 10 and para. [0079-0080], an electrostatic discharge (ESD) protection device (para. [0002]), comprising:
a) a base layer (1);
b) a first well region (14) of a first doping type (p-type), extending from an upper surface of the base layer to an internal portion of the base layer;
c) a first doped region (2) of the first doping type (p-type), located in the first well region (14) and extending from the upper surface of the base layer to an internal portion of the base layer;
d) a second doped region (3) of a second doping type (n-type), extending from the upper surface of the base layer to an internal portion of the base layer;
e) a field oxide layer (4) located on the upper surface of the base layer and adjacent to the second doped region (3); and
f) a field plate (13) extending from the upper surface of the field oxide layer (4) to the first doped region (2). Miyoshi further discloses that the high voltage diode and the high voltage NLDMOS device are formed simultaneously over an identical substrate (para. [0080]).
Miyoshi appears not to explicitly disclose that the field oxide layer comprises a first oxide layer on the upper surface of the base layer, and a second oxide layer on the first oxide layer and the upper surface of the base layer, wherein a side of the second oxide layer close to the second doped region is retracted relative to a side of the field plate close to the second doped region; h) a third doped region of the first doping type adjacent to the second doped region, wherein the third doped region is located at a side opposite to a side of the second doped region adjacent the field oxide layer; and i) wherein the first doped region, the second doped region, and the third doped region form a bipolar junction transistor, wherein the first doped region is connected to an anode electrode, and wherein the second doped region and the third doped region are connected to a cathode electrode.
Chin discloses in Fig. 2F and para. [0021-0023], an LDMOS including a field oxide layer comprising a first oxide layer (140) on the upper surface of a base layer, and a second oxide layer (151) on the first oxide layer and the upper surface of the base layer. Chin further discloses that the relative distance of a side of the second oxide layer close to the second doped region (L1) with respect to a side of the field plate close to the second doped region (L2) effects the breakdown voltage, wherein L1<L2 provides a lower breakdown voltage than the case wherein L1>L2 (para. [0023]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a field oxide layer comprising a first oxide layer on the upper surface of the base layer, and a second oxide layer on the first oxide layer and the upper surface of the base layer, wherein a side of the second oxide layer close to the second doped region is retracted relative to a side of the field plate close to the second doped region to provide a lower breakdown voltage of the protection diode relative to the breakdown voltage of the NLDMOS of Miyoshi. In so doing, the field oxide layer comprises a first oxide layer on the upper surface of the base layer, and a second oxide layer on the first oxide layer and the upper surface of the base layer, wherein a side of the second oxide layer close to the second doped region is retracted relative to a side of the field plate close to the second doped region and the second oxide layer is indented toward the anode electrode relative to a side of the field plate that is closer to the cathode electrode (L1<L2).
The combination of Miyoshi and Chin appears not to explicitly disclose h) a third doped region of the first doping type adjacent to the second doped region, wherein the third doped region is located at a side opposite to a side of the second doped region adjacent the field oxide layer; and i) wherein the first doped region, the second doped region, and the third doped region form a bipolar junction transistor, wherein the first doped region is connected to an anode electrode, and wherein the second doped region and the third doped region are connected to a cathode electrode.
Hung discloses in Figs. 2 & 4 and para. [006] & [0024-0025], oppositely doped regions in each of the first and second wells to provide parasitic bipolar transistors to lower the trigger voltage of the device (para. [0006]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the oppositely doped regions in the each well region as in Hung in Miyoshi to lower the trigger voltage of the device. In so doing, there is a third doped region of the first doping type adjacent to the second doped region, wherein the third doped region is located at a side opposite to a side of the second doped region adjacent the field oxide layer; and wherein the first doped region, the second doped region, and the third doped region form a bipolar junction transistor (see Hung, FIG. 4), wherein the first doped region is connected to an anode electrode, and wherein the second doped region and the third doped region are connected to a cathode electrode.
Regarding claim 2, Miyoshi further discloses that the field oxide layer (4) is not in contact with the first doped region (2).
Regarding claim 4, Miyoshi further discloses that the field plate (13) comprises a first part on the field oxide layer, and a second part on the upper surface of the base layer (on 12, para. [0079]).
Regarding claim 5, Miyoshi further discloses a thin oxide layer (12, para. [0079]) located between the field plate (13) and the upper surface of the base layer, wherein the thin oxide layer is adjacent to the field oxide layer (4).
Regarding claim 6, Miyoshi further discloses a thickness of the field oxide layer (4) decreases along a direction from the second doped region (3) to the first doped region (2) (birds-beak region of the field oxide layer).
Regarding claim 8, Miyoshi further discloses that the first oxide layer (field oxide) comprises a first part with uniform thickness and a second part with uneven thickness on both sides of the first part (birds-beak of the field oxide layer).
Regarding claim 10, Miyoshi as combined further discloses that a side of the second oxide layer close to the second doped region is indented relative to a side of the first part of the first oxide layer close to the second doped region (Chin, Fig. 2F, 140 & 151).
Regarding claim 15, Miyoshi further discloses that the distance between the field plate and the second doped region in part determines a breakdown voltage of the device (Figs. 7-8 and para. [0074-0076 & 0081]).
Regarding claim 16, Miyoshi further discloses that the smaller a distance between a side of the field oxide layer close to the first doped region and a side of the field plate close to the first doped region, the smaller a current capability of the device (Figs. 7-8 and para. [0074-0076 & 0081]).
Claims 3, 11 and 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miyoshi in view of Chin and Hung, and further in view of YOU (US PGPub 2019/0363188).
Regarding claim 3, Miyoshi further discloses that the high voltage diode and the high voltage NLDMOS device are formed simultaneously over an identical substrate (para. [0080]).
Miyoshi appears not to explicitly disclose a second well region of the second doping type extending from the upper surface of the base layer to internal portion of the base layer, wherein the second doped region is located in the second well region.
YOU discloses in Fig. 1 and para. [0020-0021], an LDMOS device (para. [0002]) comprising an n-well (N-Drift) in a high voltage n-type well (HVNW) in a p-type substrate (PSUB), the N-drift well region providing a doping level to trade-off breakdown voltage and on-resistance of the device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the N-drift n-well of YOU in Miyoshi to provide appropriate breakdown voltage and on-resistance. In so doing, as per the teaching of Miyoshi that the diode and LDMOS are formed simultaneously over an identical substrate, there is a second well region of the second doping type (n) extending from the upper surface of the base layer to internal portion of the base layer, wherein the second doped region is located in the second well region.
Regarding claim 11, Miyoshi as combined therein discloses that the first well region and the second well region are not in contact (YOU, Fig. 1).
Regarding claim 17, Miyoshi as combined further discloses that the greater a distance between a side of the second well region close to the first well region and a side of the field oxide layer close to the first well region, the greater a breakdown voltage of the device (YOU, para. [0021]).
Regarding claim 18, Miyoshi further discloses that the high voltage diode and the high voltage NLDMOS device are formed simultaneously over an identical substrate (para. [0080]).
Miyoshi appears not to explicitly disclose that the base layer comprises a substrate of the first doping type.
YOU discloses in Fig. 1 and para. [0020-0021], an LDMOS device (para. [0002]) comprising an n-well (N-Drift) in a high voltage n-type well (HVNW) in a p-type substrate (PSUB), the N-drift well region providing a doping level to trade-off breakdown voltage and on-resistance of the device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the N-drift n-well in the p-type substrate of YOU in Miyoshi to provide appropriate breakdown voltage and on-resistance. In so doing, as per the teaching of Miyoshi that the diode and LDMOS are formed simultaneously over an identical substrate, the base layer comprises a substrate of the first doping type (p).
Regarding claim 19, Miyoshi further discloses that the high voltage diode and the high voltage NLDMOS device are formed simultaneously over an identical substrate (para. [0080]).
Miyoshi appears not to explicitly disclose that the base layer comprises a substrate of a first doping type and a high-voltage well region of a second doping type located in the substrate, and the first well region is located in the high-voltage well region.
YOU discloses in Fig. 1 and para. [0020-0021], an LDMOS device (para. [0002]) comprising an n-well (N-Drift) in a high voltage n-type well (HVNW) in a p-type substrate (PSUB), the N-drift well region providing a doping level to trade-off breakdown voltage and on-resistance of the device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the N-drift n-well in the p-type substrate of YOU in Miyoshi to provide appropriate breakdown voltage and on-resistance. In so doing, as per the teaching of Miyoshi that the diode and LDMOS are formed simultaneously over an identical substrate, the base layer comprises a substrate of a first doping type (p) and a high-voltage well region of a second doping type (n) located in the substrate, and the first well region is located in the high-voltage well region.
Regarding claim 20, Miyoshi further discloses that the high voltage diode and the high voltage NLDMOS device are formed simultaneously over an identical substrate (para. [0080]).
Miyoshi appears not to explicitly disclose that the field plate is a polysilicon field plate.
YOU discloses in Fig. 1 and para. [0020], an LDMOS device (para. [0002]) comprising a gate conductor comprising polysilicon.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use polysilicon as the gate conductor as in YOU in Miyoshi, the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). (See MPEP 2144.07). In so doing, the field plate is a polysilicon field plate.
Response to Arguments
Applicant’s arguments, see pages 6-7, filed 10/14/2025, with respect to the objection to the drawings and §112 claim rejections have been fully considered and are persuasive. The objection to the drawings and §112 claim rejections have been withdrawn.
Applicant's arguments filed 10/14/2025 with respect to claim 1 have been fully considered but they are not persuasive. The combination of Miyoshi, Chin, and Hung disclose the claimed device. See the rejection of claim 1 for further details.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUCKER J WRIGHT whose telephone number is (571)270-3234. The examiner can normally be reached 8:30am-5:00pm.
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/TUCKER J WRIGHT/Primary Examiner, Art Unit 2891