Prosecution Insights
Last updated: July 17, 2026
Application No. 17/550,230

METHOD OF MANUFACTURING TRANSISTOR

Non-Final OA §102§103
Filed
Dec 14, 2021
Priority
Dec 14, 2020 — RE 10-2020-0174159
Examiner
CULBERT, CHRISTOPHER A
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Display Co., Ltd.
OA Round
3 (Non-Final)
42%
Grant Probability
Moderate
3-4
OA Rounds
0m
Est. Remaining
49%
With Interview

Examiner Intelligence

Grants 42% of resolved cases
42%
Career Allowance Rate
144 granted / 341 resolved
-25.8% vs TC avg
Moderate +7% lift
Without
With
+6.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
43 currently pending
Career history
416
Total Applications
across all art units

Statute-Specific Performance

§103
82.1%
+42.1% vs TC avg
§102
11.3%
-28.7% vs TC avg
§112
5.2%
-34.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 341 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/1/2025 has been entered. Claim Rejections - 35 USC § 102 The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claim(s) 1-3 and 10-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wu et al (US 2019/0067302 A1). Regarding claim 1, Wu discloses a method of manufacturing a transistor, the method comprising: forming an active layer on a base substrate (Wu discloses that the bottom of the device may be “silicon-on-insulator”, the silicon portion may be considered an active layer and the insulator may be considered a base substrate); forming a sacrificial layer (402 in Fig. 4) on the active layer; doping a first dopant ion in an entire portion of the active layer through a first ion implantation process without using a mask (¶ 0063; the “entire portion” being the portion of the active layer which is implanted with the ion); removing the sacrificial layer (see Fig. 11); forming a gate insulating layer (118 in Fig. 1); and forming a gate electrode (114) on the gate insulating layer. Regarding claim 2, Wu further discloses wherein the sacrificial layer comprises silicon oxide (¶ 0062). Regarding claim 3, Wu further discloses wherein the sacrificial layer is formed through a chemical vapor deposition process (¶ 0062). Regarding claim 10, Wu further discloses wherein a doping amount of the first dopant ion in the active layer has a peak in a region (deep well 202 in Fig. 5) and that region is less than or equal to 20 nm from a surface of the active layer (the deep well is at the surface of the active layer). Regarding claim 11, the Examiner notes that applicant has claimed a concentration per area instead of a concentration per volume. As the active layer of Wu is a volume that is doped with ions and Applicant has given no restrictions for how this area may be selected, it can be selected arbitrarily. As such, there will exist a 1 nanometer x 1 nanometer area through an ion in the active layer. This area has a concentration of more than 1012 ions/cm2. The Examiner notes that if Applicant instead claimed a concentration per volume (e.g., ions/cm3 or an area concentration within a specific area (such as the surface of the active layer), then this line of reasoning would no longer apply. Regarding claim 12, Wu further discloses wherein forming the gate electrode comprises sequentially forming an insulating layer (1002, Fig. 13B) and a gate electrode forming layer (1304) on the active layer after removing the sacrificial layer, and patterning the gate electrode forming layer (see Fig. 13C) to form a gate electrode (324 in Fig. 13P) on the insulating layer; and wherein the method of manufacturing the transistor further comprises forming an interlayer insulating layer (214u in Fig. 13S) on the gate electrode; and forming a source electrode and a drain electrode (216 in Fig. 13S) on the interlayer insulating layer. Regarding claim 13, Wu further discloses doping a second dopant ion on the active layer through a second ion implantation process (¶ 0065). Regarding claim 14, Wu further discloses wherein an upper surface of the doped part contacts with the insulating layer (see Fig. 13S). Claim Rejections - 35 USC § 103 The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claim(s) 4 and 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al (US 2019/0067302 A1) as applied to claim 1 above, and further in view of Chuang et al. (US 2020/0194316 A1). Regarding claim 4, Wu does not disclose that the sacrificial layer is removed through a wet etching method. Chuang, in the same field of endeavor, discloses removing sacrificial materials via a wet etching method (“chemical mechanical polishing”, ¶ 0021). There was a benefit to using such a method in that it can selectively etch the sacrificial material without unnecessary damage to the other components. It would have been obvious to one having ordinary skill in the art before the Application's effective filing date to using the wet etching method of Chuang for this benefit. Regarding claim 5, Wu does not disclose that the sacrificial layer is removed through a chemical mechanical polishing method. Chuang, in the same field of endeavor, discloses removing sacrificial materials via a chemical mechanical polishing method (“chemical mechanical polishing”, ¶ 0021). There was a benefit to using such a method in that it can selectively etch the sacrificial material without unnecessary damage to the other components. It would have been obvious to one having ordinary skill in the art before the Application's effective filing date to using the chemical mechanical polishing method of Chuang for this benefit. Claim(s) 6 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al (US 2019/0067302 A1) as applied to claim 1 above, and further in view of Fujii (US 2018/0286950 A1). Regarding claim 6, Wu differs from the claimed invention by the substitution of a group III element for the first dopant ion with an unspecified element. However, doping with group III elements and the corresponding function was known in the art (“boron”, ¶ 0047 of Fujii). As such, it would have been obvious to one having ordinary skill in the art before the Application's effective filing date to have substituted the known dopant of boron as taught by Fujii for the unspecified dopant of Wu and the results of the substitution would have been predictable. (see MPEP § 2143(I)(B)). Regarding claim 7, Fujii discloses that the group III element is boron (¶ 0047). Response to Arguments Applicant's arguments filed 10/1/2025 have been fully considered but they are not persuasive. Applicant argues that ¶ 0063 of Wu states that the selective doping is performed with a mask. This argument is not persuasive as ¶ 0063 states that the selective doping “may, for example, be performed using an ion implantation with a mask” and that “some other suitable selecting doping process” may be used. As such, Wu clearly states that the mask is not required. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A CULBERT whose telephone number is (571)272-4893. The examiner can normally be reached M-F 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTOPHER A CULBERT/ Examiner, Art Unit 2815
Read full office action

Prosecution Timeline

Dec 14, 2021
Application Filed
May 01, 2025
Non-Final Rejection mailed — §102, §103
Jul 31, 2025
Response Filed
Aug 11, 2025
Final Rejection mailed — §102, §103
Oct 01, 2025
Response after Non-Final Action
Nov 11, 2025
Request for Continued Examination
Nov 17, 2025
Response after Non-Final Action
Apr 08, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
42%
Grant Probability
49%
With Interview (+6.8%)
3y 7m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 341 resolved cases by this examiner. Grant probability derived from career allowance rate.

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