Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 23 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20180286876 A1) in view of Wang (US 20190326445 A1).
Regarding claim 1, Kim discloses an apparatus, comprising: alternated layers of conductor material (Fig. 2, 130a-b) and insulator material (140), the alternated layers including two layers of insulator material (Insulative layers directly above and below any given conductive layer); a vertical channel (110) through at least four of the alternated layers of the substrate, wherein an edge of the two layers of insulator material abuts an edge of the vertical channel (Fig. 2, shows edges of 140 abutting 110); and a memory cell (comprises at least 125a, 124a, 123a, and 121a) on the vertical channel disposed in a layer of conductor material between the two layers of insulator material (Shown), wherein the memory cell comprises: a control gate (comprises at least 125a, 124a, and 123a) disposed in a recess of the layer of conductor material between the two layers of the insulator material, wherein the recess opens towards the edge of the vertical channel (Shown), and the control gate has a concave surface facing the vertical channel (inner face of 123a), a trap base (121a) disposed in the recess between the control gate and the edge of the vertical channel (Shown), where the trap base has a planar surface (face of 121a facing the channel 110) that is recessed from the edge of the two layers of insulator material (Fig. 2 shows 121a being slightly recessed inward compared to the rightmost edge of insulator layers 140) and tunnel oxide material (113a; para. 32 "the tunnel dielectric layer 113a can comprise an oxide material") that covers the trap base and extends into the vertical channel outside of the recess and beyond the edge of the two layers of insulator material (Shown) wherein the control gate includes a gate structure (124a) and two dielectric films (125a and 123a; para. 33 "dielectric layers 123a-125a…"), and wherein the gate structure is distinct from the trap base and the layer of conductor material (Shown), and insulated from each of the trap base and the layer of conductor material by a respective dielectric film of the two dielectrics (124a is insulated from trap base 121a by 123a, and 124a is insulated from conductor material 130a by 125a). However, Kim does not explicitly disclose the apparatus comprising a substrate or the control gate being configured to apply a control gate voltage.
On the other hand, Wang discloses an apparatus comprising a substrate (Fig. 12, substrate 11). It would have been obvious to one of ordinary skill in the art before the time of effective filing to modify Kim according to the teachings up Wang such that the device taught by Kim would be anchored to substrate as is extremely common in the art, in order to provide the device with a stable foundational piece.
Regarding claim 2, Kim discloses wherein a cross section taken through a center line axis of the vertical channel and a center of the memory cell has a substantially flat front line for the trap base parallel to the vertical channel (Fig. 2 shows the front/inner face of the trap bases being substantially parallel to the vertical channel).
Regarding claim 23, Kim discloses wherein the memory cell has a cross section passing and including a center line axis of the vertical channel, and the control gate has a rounded bracket profile on the cross section (Fig. 2 shows control gate comprising 125a, 124a, and 123a having a rounded bracket
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profile; see attached figure).
Regarding claim 24, Kim discloses wherein the trap base is at least partially surrounded by the rounded bracket profile of the control gate (Shown in Fig. 2).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20180286876 A1) as applied to claims 1-2 and 23-24 above, and further in view of Seo (US 20140131785 A1) in view of Wang (US 20190326445 A1).
Regarding claim 3, Kim discloses the apparatus of claim 1. However, Kim does not disclose wherein material adjacent to the edge of the vertical channel has a waviness with no substantial range of variation between peaks and valleys of the material.
On the other hand, Seo discloses wherein material adjacent to the edge of the vertical channel has a waviness with no substantial range of variation between peaks and valleys of the material (Figs. 2B/6A, para. 47-49 and Figs. 6A describe improvements to the electrical performance of the individual memory cells due to a reduced waviness). It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Kim according to the teachings of Seo such that the material adjacent to the edge of the vertical channel would have a waviness with no substantial range of variation between peaks and valleys of the material, in order to reduce interference between neighboring memory cells and improve the read current.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20180286876 A1) in view of Wang (US 20190326445 A1) as applied to claims 1-2 and 23-24 above, and further in view of Lim (US 20210066346 A1).
Regarding claim 5, Kim discloses the apparatus of claim 1. However, Kim does not disclose wherein the material adjacent to outside edges of the vertical channel tapers to a pinch point and a tunnel oxide within the vertical channel is formed.
On the other hand, Lim discloses wherein the material adjacent to outside edges of the vertical channel (Fig. 5B, 140 is within vertical channel 150) tapers to a pinch point (Fig. 5B shows 140 tapering to a pinch point), and a tunnel oxide within the vertical channel is formed (Tunnel oxide 142; para. 36 "The tunnel insulating layer 142… may include, for example silicon oxide"). It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Kim according to the teachings of Lim such that the material adjacent to outside edges of the vertical channel would taper to a pinch point, and a tunnel oxide within the vertical channel would be formed, in order to improve necking.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20180286876 A1) in view of Wang (US 20190326445 A1) as applied to claims 1-2 and 23-24 above, and further in view of Kurokawa (US 20130293263 A1).
Regarding claim 6, Kim discloses the apparatus of claim 1. However, Kim does not disclose wherein a control gate voltage minus a threshold voltage of a programmed memory cell within the vertical channel is in a range of between 300 millivolts and 450 millivolts.
On the other hand, Kurokawa discloses wherein a control gate voltage minus a threshold voltage of a programmed memory cell within the vertical channel is in a range of between 300 millivolts and 450 millivolts (Fig. 17 shows that overdrive voltages in the range of 300-400 mV significantly reducing signal delay; overdrive voltage is defined as control gate voltage - threshold voltage). It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Kim according to the teachings of Kurokawa such that the overdrive voltage (defined as the control gate voltage minus the threshold voltage) of a programmed memory cell within the vertical channel would be in a range of 300 mV to 450 mV, in order to reduce signal delay and consequently optimize transistor switching speeds during read, write and programming operations.
Claims 15-16 and 25-26 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20180286876 A1) in view of Agarwal (US 10784274 B1) and Wang (US 20190326445 A1).
Regarding claim 15, Kim discloses wherein the 3D memory device includes: alternated layers of conductor material (Fig. 2, 130a-b) and insulator material (140), the alternated layers including two layers of insulator material (Insulative layers directly above and below any given conductive layer); a memory array of vertical 3D NAND strings formed in the substrate, wherein a pillar of the vertical 3D NAND strings passes through the alternated layers of the substrate (Shown best in Fig. 1), an edge of the plurality of layers of insulator material abuts an edge of the pillar (Fig. 2, shows edges of 140 abutting 110), and respective memory cells on the pillar (comprises at least 125a-b, 124a-b, 123a-b, and 121a-b) are disposed in respective layers of conductor material between respective layers of the insulator material (Shown), wherein the memory cell comprises: a control gate (comprises at least 125a, 124a, and 123a) disposed in a recess of the layer of conductor material between the two layers of the insulator material, wherein the recess opens towards the edge of the vertical channel (Shown), and the control gate has a concave surface facing the vertical channel (inner face of 123a), a trap base (121a) disposed in the recess between the control gate and the edge of the pillar (Shown), and tunnel oxide material (113a; para. 32 "the tunnel dielectric layer 113a can comprise an oxide material") that covers the trap base and extends into the pillar outside of the recess and beyond the edge of the two layers of insulator material (Shown) wherein the control gate includes a gate structure (124a) and two dielectric films (125a and 123a; para. 33 "dielectric layers 123a-125a…"), and wherein the gate structure is distinct from the trap base and the layer of conductor material (Shown), and insulated from each of the trap base and the layer of conductor material by a respective dielectric film of the two dielectrics (124a is insulated from trap base 121a by 123a, and 124a is insulated from conductor material 130a by 125a). However, Kim does not explicitly disclose a system comprising a processor and a three-dimensional memory device coupled to the processor, the apparatus comprising a substrate or the control gate being configured to apply a control gate voltage.
On the other hand, Agarwal discloses a system, comprising: a processor and a three-dimensional memory device coupled to the processor (Fig. 7 shows processor 2004 coupled to 3D memory device DRAM). It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Kim according to the teachings of Agarwal such that the 3D memory device would be coupled to a system comprising a processor, in order to provide the memory device with a source of data to store.
Kim in view of Agarwal still does not disclose the apparatus comprising a substrate. However, Wang discloses an apparatus comprising a substrate (Fig. 12, substrate 11). It would have been obvious to one of ordinary skill in the art before the time of effective filing to modify Kim according to the teachings up Wang such that the device taught by Kim would be anchored to substrate as is extremely common in the art, in order to provide the device with a stable foundational piece.
Kim in view of Agarwal and Wang still does not disclose the control gate being configured to apply a control gate voltage. Nonetheless, it is inherent that the control gate is configured to apply a control gate voltage, as it is a basic and necessary function of any memory device capable of read/write operations.
Regarding claim 16, Kim discloses wherein a cross section taken through a center line axis of the pillar and a center of the memory cell has a substantially flat front line for the trap base parallel to the pillar (Fig. 2 shows the front/inner face of the trap bases being substantially parallel to the vertical channel).
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Regarding claim 25, Kim discloses wherein the memory cell has a cross section passing and including a center line axis of the vertical channel, and the control gate has a rounded bracket profile on the cross section (Fig. 2 shows control gate comprising 125a, 124a, and 123a having a rounded bracket profile; see attached figure).
Regarding claim 26, Kim discloses the trap base is at least partially surrounded by the rounded bracket profile of the control gate (Shown in Fig. 2).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20180286876 A1) in view of Agarwal (US 10784274 B1) and Wang (US 20190326445 A1) as applied to claims 15-16 and 25-26 above, and further in view of Seo (US 20140131785 A1).
Regarding claim 17, Kim in view of Agarwal discloses the system of claim 15. However, Kim in view of Agarwal does not disclose wherein material adjacent to the edge of the pillar has a waviness with no substantial range of variation between peaks and valleys of the material.
On the other hand, Seo discloses wherein material adjacent to the edge of the pillar has a waviness with no substantial range of variation between peaks and valleys of the material (Figs. 2B/6A, para. 47-49 and Figs. 6A describe improvements to the electrical performance of the individual memory cells due to a reduced waviness). It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Kim in view of Agarwal according to the teachings of Seo such that the material adjacent to the edge of the vertical channel would have a waviness with no substantial range of variation between peaks and valleys of the material, in order to reduce interference between neighboring memory cells and improve the read current.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20180286876 A1) in view of Agarwal (US 10784274 B1) and Wang (US 20190326445 A1) as applied to claims 15-16 and 25-26 above, and further in view of Lim (US 20210066346 A1).
Regarding claim 19, Kim in view of Agarwal discloses the system of claim 15. However, Kim in view of Agarwal does not disclose wherein the pillar tapers to a neck with a pinch point and a tunnel oxide within the pillar is formed.
On the other hand, Lim discloses wherein the pillar tapers to a neck with a pinch point (Fig. 5B, narrowest points in 150), and a tunnel oxide (142) within the pillar is formed (para. 36 "The tunnel insulating layer 142… may include, for example silicon oxide"). It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Kim in view of Agarwal according to the teachings of Lim such that the material adjacent to outside edges of the vertical channel would taper to a pinch point, and a tunnel oxide within the vertical channel would be formed, in order to improve necking.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20180286876 A1) in view of Agarwal (US 10784274 B1) and Wang (US 20190326445 A1) as applied to claims 15-16 and 25-26 above, and further in view of Kurokawa (US 20130293263 A1).
Regarding claim 20, Kim in view of Agarwal discloses the system of claim 15. However, Kim in view of Agarwal does not disclose wherein a control gate voltage minus a threshold voltage of a programmed memory cell within the vertical channel is in a range of between 300 millivolts and 450 millivolts.
On the other hand, Kurokawa discloses wherein a control gate voltage minus a threshold voltage of a programmed memory cell within the vertical channel is in a range of between 300 millivolts and 450 millivolts (Fig. 17 shows that overdrive voltages in the range of 300-400 mV significantly reducing signal delay; overdrive voltage is defined as control gate voltage - threshold voltage). It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Kim in view of Agarwal according to the teachings of Kurokawa such that the overdrive voltage (defined as the control gate voltage minus the threshold voltage) of a programmed memory cell within the vertical channel would be in a range of 300 mV to 450 mV, in order to reduce signal delay and consequently optimize transistor switching speeds during read, write and programming operations.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20180286876 A1) in view of Wang (US 20190326445 A1) as applied to claims 1-2 and 23-24 above, and further in view of Nakanishi (US 20110294290 A1).
Regarding claim 21, Kim discloses the apparatus of claim 1. However, Kim does not disclose wherein the tunnel oxide material has a first surface extending into the vertical channel and a second surface opposing the first surface and the second surface is immediately adjacent to the planar surface of the trap base wherein both the first surface and the second surface are partially recessed towards the trap base to conformally cover the planar surface of the trap base and the edge of the two layers of insulator material.
On the other hand, Nakanishi discloses wherein the tunnel oxide material (Fig. 13, 170 in combination with 165; para. 125 "170 may be a silicon oxide layer") has a first surface extending into the vertical channel (Right side surface of 165) and a second surface opposing the first surface (left side surface of 165), and the second surface is immediately adjacent to the planar surface of the trap base (Fig. 4 shows second surface being immediately adjacent to the planar surface of the trap base 162), wherein both the first surface and the second surface are partially recessed towards the trap base to conformally cover the planar surface of the trap base and the edge of the two layers of insulator material (See fig. 4). It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Kim according to the teachings of Nakanishi such that the tunnel oxide material would have a first surface extending into the vertical channel and a second surface opposing the first surface, and the second surface would be immediately adjacent to the planar surface of the trap base wherein both the first surface and the second surface are partially recessed towards the trap base to conformally cover the planar surface of the trap base and the edge of the two layers of insulator material, in order to increase the simplify manufacturing by depositing a layer that simply conforms to the underlying trap base.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20180286876 A1) in view of Agarwal (US 10784274 B1) and Wang (US 20190326445 A1) as applied to claims 15-16 and 25-26 above, and further in view of Nakanishi (US 20110294290 A1).
Regarding claim 22, Kim in view of Agarwal discloses the system of claim 15. However, Kim in view of Agarwal does not disclose wherein the tunnel oxide material has a first surface extending into the vertical channel and a second surface opposing the first surface and the second surface is immediately adjacent to the planar surface of the trap base wherein both the first surface and the second surface are partially recessed towards the trap base to conformally cover the planar surface of the trap base and the edge of the two layers of insulator material.
On the other hand, Nakanishi discloses wherein the tunnel oxide material (Fig. 13, 170 in combination with 165; para. 125 "170 may be a silicon oxide layer") has a first surface extending into the vertical channel (Right side surface of 165) and a second surface opposing the first surface (left side surface of 165), and the second surface is immediately adjacent to the planar surface of the trap base (Fig. 4 shows second surface being immediately adjacent to the planar surface of the trap base 162), wherein both the first surface and the second surface are partially recessed towards the trap base to conformally cover the planar surface of the trap base and the edge of the two layers of insulator material (See fig. 4). It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Kim in view of Agarwal according to the teachings of Nakanishi such that the tunnel oxide material would have a first surface extending into the vertical channel and a second surface opposing the first surface, and the second surface would be immediately adjacent to the planar surface of the trap base wherein both the first surface and the second surface are partially recessed towards the trap base to conformally cover the planar surface of the trap base and the edge of the two layers of insulator material, in order to increase the simplify manufacturing by depositing a layer that simply conforms to the underlying trap base.
Response to Arguments
Applicant’s arguments, see pgs. 9-14, filed 2/2/2026, with respect to the rejection(s) of claim(s) 1-3, 5, 6, 15-17, and 19-24 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of newly found prior art. Kim (US 20180286876 A1) remedies all deficiencies the previous prior art may have had in light of the claim amendments.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/S.J.S./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817