DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 10, 15, 25, and 26 have been amended.
Claim 9 has been cancelled.
Claims 27 and 28 have been added.
Claims 1-8, 10-17, and 19-28 have been examined.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on February 17, 2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 10-14, 16, 19, 25, and 26 are rejected under 35 U.S.C. 103 as being unpatentable over US Publication No. 2016/0246602 by Radhika et al. (as cited by Applicant and hereinafter referred to as “Radhika”) in view of US Publication No. 2009/0063831 by Ekman (hereinafter referred to as “Ekman”).
Regarding claims 1, 25, and 26, taking claim 1 as representative, Radhika discloses:
a processor-implemented method for task processing comprising: accessing a two-dimensional (2D) array of compute elements, wherein each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements (Radhika discloses, at ¶ [0054] et seq., accessing a CGRA includes a compiler mapping operations to the PEs therein, which discloses a 2D array of elements known to a compiler and coupled to neighboring elements.);
providing control for the array of compute elements on a cycle-by-cycle basis, wherein the control is enabled by a stream of wide, variable length, control words generated by the compiler, and wherein the control includes a branch (Radhika discloses, at ¶ [0054] et seq., the compiler configures the operations associated with if paths and else paths, which discloses a branch, to the PEs in each cycle, which discloses a stream of wide, variable length control words generated by the compiler, including a branch.);
executing two sides of the branch in the array while waiting for a branch decision to be acted upon by control logic, wherein the branch decision is based on computation results in the array… the commit write having been scheduled by the compiler to occur …(Radhika discloses, at ¶ [0074], using partial predication in some instances. As explained, e.g., at ¶ [0009], partial predication involves executing both the if-path and the else-path and then selecting the result based on the outcome of the branch. Radhika also discloses, at ¶ [0074], the compiler generating scheduled instructions, which discloses scheduling the commit write.); and
promoting data produced by a taken branch path, based on the branch decision (Radhika discloses, at ¶ [0074], using partial predication in some instances. As explained, e.g., at ¶ [0009], partial predication involves selecting the final result based on the outcome of the branch, which discloses promoting data produced by the taken branch path.).
Radhika does not explicitly disclose operation of the array is halted if either of the two sides of the branch attempts to execute a commit write ahead of the branch decision and the commit write is to occur outside a branch indecision window, wherein the branch indecision window includes one of an amount of time, and a number of cycles that can elapse from the time of the branch decision in the array until the time the branch decision can be acted upon by a control unit.
However, in the same field of endeavor (e.g., branches) Ekman discloses:
operation is halted prior to the branch decision and the commit write is to occur outside a branch indecision window, wherein the branch indecision window includes one of an amount of time, and a number of cycles that can elapse from the time of the branch decision in the array until the time the branch decision can be acted upon by a control unit. (Ekman discloses, e.g., at ¶ [0025], speculatively executed instructions are not committed until the branch is resolved, which discloses operation is halted if either of the two sides of the branch attempts to execute a commit write ahead of the branch decision and the commit write occurs outside a branch indecision window. A branch indecision window includes, by definition, an amount of time.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Radhika to include halting operation and committing outside a branch indecision window, as disclosed by Ekman in order to ensure correct operation with speculative execution.
Regarding claim 2, Radhika discloses the elements of claim 1, as discussed above. Radhika also discloses:
using the data that was promoted for a downstream operation (Radhika discloses, at ¶ [0074], using partial predication in some instances. As explained, e.g., at ¶ [0009], partial predication involves selecting the final result, which discloses using the final result.).
Regarding claim 3, Radhika discloses the elements of claim 2, as discussed above. Radhika also discloses:
ignoring results from a side of the branch not indicated by the branch decision (Radhika discloses, at ¶ [0074], using partial predication in some instances. As explained, e.g., at ¶ [0009] et seq., partial predication involves selecting the final result and suppressing the false path output, which discloses ignoring results from the not taken branch.).
Regarding claim 4, Radhika discloses the elements of claim 2, as discussed above. Radhika also discloses:
removing results from a side of the branch not indicated by the branch decision (Radhika discloses, at ¶ [0074], using partial predication in some instances. As explained, e.g., at ¶ [0009] et seq., partial predication involves selecting the final result and suppressing the false path output, which discloses removing results from the not taken branch.).
Regarding claim 5, Radhika discloses the elements of claim 1, as discussed above. Radhika also discloses:
the data produced by a taken branch path is used for a committed write (Radhika discloses, at Figure 12, the CGRA writing to data memory. As disclosed at ¶ [0006], this involves committing results, which discloses using data produced by the taken path for a committed write.).
Regarding claim 6, Radhika discloses the elements of claim 5, as discussed above. Radhika also discloses:
the committed write cannot be ignored or reversed (Radhika discloses, at Figure 12, the CGRA writing to data memory. As disclosed at ¶ [0006], this involves committing results, which discloses using data produced by the taken path for a committed write that cannot be ignored or reversed.).
Regarding claim 7, Radhika discloses the elements of claim 5, as discussed above. Radhika also discloses:
the committed write includes a committed write to data storage (Radhika discloses, at Figure 12, the CGRA writing to data memory. As disclosed at ¶ [0006], this involves committing results, which discloses using data produced by the taken path for a committed write to data storage.).
Regarding claim 8, Radhika discloses the elements of claim 7, as discussed above. Radhika also discloses:
the data storage resides outside of the 2D array of compute elements (Radhika discloses, at Figure 12, the CGRA writing to data memory that is outside of the CGRA.).
Regarding claim 10, Radhika discloses the elements of claim 1, as discussed above. Radhika also discloses:
the scheduling the commit write avoids halting operation of the array (Radhika discloses, at ¶ [0053] et seq., scheduling enables the PEs to run immediately after the branch outcome is determined, which avoids halting the array.).
Regarding claim 11, Radhika discloses the elements of claim 1, as discussed above. Radhika also discloses:
the executing obviates branch prediction logic (Radhika discloses, at ¶ [0074], using partial predication in some instances. As explained, e.g., at ¶ [0009], partial predication involves executing both the if-path and the else-path, which discloses obviating branch prediction logic.).
Regarding claim 12, Radhika discloses the elements of claim 1, as discussed above. Radhika also discloses:
loading the data produced by a taken branch path into in-array compute element memory (Radhika discloses, at ¶ [0053] et seq., executing the instructions on the true path, which discloses loading data produced by that path into an in-array compute element memory.).
Regarding claim 13, Radhika discloses the elements of claim 12, as discussed above. Radhika also discloses:
ignoring data that was loaded into the in- array compute element memory, based on the branch decision (Radhika discloses, at ¶ [0074], using partial predication in some instances. As explained, e.g., at ¶ [0009] et seq., partial predication involves selecting the final result and ignoring the false path output, which discloses ignoring data loaded into the in-array compute element memory.).
Regarding claim 14, Radhika discloses the elements of claim 1, as discussed above. Radhika also discloses:
executing an additional branch concurrently with the two sides of a branch (Radhika discloses, at ¶ [0053], performing operations that are independent of the current branch, which discloses an additional branch.).
Regarding claim 16, Radhika discloses the elements of claim 14, as discussed above. Radhika also discloses:
the additional branch and the two sides of a branch comprise two independent branch decisions (Radhika discloses, at ¶ [0053], performing operations that are independent of the current branch, which discloses an additional branch.).
Regarding claim 19, Radhika discloses the elements of claim 1, as discussed above. Radhika also discloses:
storing portions of a control word, from the stream of control words, within a cache associated with the array of compute elements (Radhika discloses, at Figure 4 and related description, an instruction memory, which discloses storing portions of a control word from a stream of control words.).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over US Publication No. 2016/0246602 by Radhika et al. (as cited by Applicant and hereinafter referred to as “Radhika”) in view of Ekman in view of US Patent No. 5,634,025 by Breternitz (hereinafter referred to as “Breternitz”).
Regarding claim 15, Radhika discloses the elements of claim 14, as discussed above. Radhika also discloses:
the additional branch and the two sides of a branch comprise a multiway branch evaluation (Radhika discloses, at ¶ [0087], at least two potential paths, which discloses a multiway branch.).
Radhika does not explicitly disclose the multiway branch evaluation includes three branches wherein the multiway branch evaluation includes a switch operation.
However, in the same field of endeavor (e.g., branches) Breternitz discloses:
the multiway branch evaluation includes three branches (Breternitz discloses, e.g., at col. 11, lines 45-50, three-way branches.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Radhika to include three-way branching, as disclosed by Breternitz, to increase flexibility of control flow.
However, in the same field of endeavor (e.g., branches) Ekman discloses:
switch operations (Ekman discloses, at ¶ [0029], switch operations.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Radhika to include switch operations, as disclosed by Ekman in order to improve efficiency of the method.
Claims 17, 20, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Radhika in view of Ekman in view of US Patent No. 4,760,525 by Webb (hereinafter referred to as “Webb”).
Regarding claim 17, Radhika discloses the elements of claim 1, as discussed above. Radhika also discloses:
…provide branch address offsets to the array of compute elements (Radhika discloses, at ¶ [0054] et seq., executing operations associated with branches, which discloses providing branch address offsets.).
Radhika does not explicitly disclose the aforementioned providing uses row ring buses.
However, in the same field of endeavor (e.g., processing) Webb discloses:
moving data using ring busses (Webb discloses, at col. 5, lines 37-39, using a ring bus.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Radhika to include a ring bus, as disclosed by Webb, because doing so is a known technique to reduce memory latency.
Regarding claim 20, Radhika discloses the elements of claim 19, as discussed above. Radhika does not explicitly disclose the cache comprises a dual read, single write (2R1W) data cache.
However, in the same field of endeavor (e.g., processing) Webb discloses:
memory having two read ports and one write port (Webb discloses, at col. 24, lines 11-13, memory having two read ports and one write port.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Radhika to include two read one write memory, as disclosed by Webb, because multiple ports can improve flexibility by improving bandwidth capabilities.
Regarding claim 21, Radhika discloses the elements of claim 20, as discussed above. Radhika also discloses:
… simultaneous fetch of potential branch paths for a control unit (Radhika discloses, at ¶ [0054] et seq., the compiler configures the operations associated with if paths and else paths.).
Radhika does not explicitly disclose the 2R1W cache.
However, in the same field of endeavor (e.g., processing) Webb discloses:
memory having two read ports and one write port (Webb discloses, at col. 24, lines 11-13, memory having two read ports and one write port.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Radhika to include two read one write memory, as disclosed by Webb, because multiple ports can improve flexibility by improving bandwidth capabilities.
Claims 22-24 are rejected under 35 U.S.C. 103 as being unpatentable over Radhika in view of Ekman in view of US Publication No. 2020/0159809 by Catthoor et al. (hereinafter referred to as “Catthoor”).
Regarding claim 22, Radhika discloses the elements of claim 1, as discussed above. Radhika also discloses:
the compiler maps …functionality to the array of compute elements (Radhika discloses, at ¶ [0054] et seq., the compiler schedules operations for the PEs.).
Radhika does not explicitly disclose the aforementioned functionality is machine learning.
However, in the same field of endeavor (e.g., processing) Catthoor discloses:
machine learning (Catthoor discloses, at Figure 1 and related description, neural networks, which discloses machine learning.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Radhika to include machine learning, as disclosed by Catthoor, in order to increase value by operating in the widespread field of machine learning.
Regarding claim 23, Radhika discloses the elements of claim 22, as discussed above Radhika does not explicitly disclose the aforementioned machine learning functionality includes a neural network implementation.
However, in the same field of endeavor (e.g., processing) Catthoor discloses:
machine learning (Catthoor discloses, at Figure 1 and related description, neural networks, which discloses machine learning.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Radhika to include neural networks, as disclosed by Catthoor, in order to increase value by operating in the widespread field of neural networks.
Regarding claim 24, Radhika discloses the elements of claim 1, as discussed above. Radhika does not explicitly disclose stacking the 2D array of compute elements with another 2D array of compute elements to form a three-dimensional stack of compute elements.
However, in the same field of endeavor (e.g., processing) Catthoor discloses:
machine learning (Catthoor discloses, at Figure 15 and related description, stacking planar arrays to provide a vertical stack.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Radhika to include stacked arrays, as disclosed by Catthoor, because stacking is a known way to improve performance, e.g., due to routing optimizations.
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Radhika in view of Ekman in view of US Patent No. 5,961,269 by Nguyen et al. (hereinafter referred to as “Nguyen”).
Regarding claim 27, Radhika discloses the elements of claim 1, as discussed above. Radhika does not explicitly disclose the additional branch is used to handle an error.
However, in the same field of endeavor (e.g., processing) Nguyen discloses:
branching to error handling routines (Nguyen discloses, at col. 13, lines 34-39, branching to code to handle errors.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Radhika to include using branches to handle errors, as disclosed by Nguyen, in order to improve performance by maintaining separate special purpose functions, i.e., error handling, apart from the main code.
Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over Radhika in view of Ekman in view of US Patent No. 5,907,693 by Fant et al. (hereinafter referred to as “Fant”).
Regarding claim 28, Radhika discloses the elements of claim 1, as discussed above. Radhika does not explicitly disclose the data produced by the taken branch path enables computation wave-front propagation within the array of compute elements.
However, in the same field of endeavor (e.g., processing) Fant discloses:
wavefront propagation (Fant discloses, at col. 13, lines 34-39, wavefront propagation.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Radhika to include wavefront propagation, as disclosed by Fant, in order to improve performance increasing instruction parallelism.
Response to Arguments
On page ___ of the response filed ___ (“response”), the Applicant argues ____
Though fully considered, the Examiner respectfully disagrees.
Accordingly, the Applicant’s arguments are deemed unpersuasive.
On page ___ of the response the Applicant argues ____
Though fully considered, the Examiner respectfully disagrees.
Accordingly, the Applicant’s arguments are deemed unpersuasive.
Though fully considered, the Examiner respectfully disagrees. The remarks and rejections presented above apply similarly to these claims.
These remarks have been fully considered and, in light of the claim amendments presented in the response, are deemed persuasive. Please see above for new grounds of rejection of the amended claims.
Conclusion
The following prior art made of record and not relied upon is considered pertinent to Applicant’s disclosure.
Doe et al. (US _____) disclose _____.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN DOMAN whose telephone number is (571)270-5677. The examiner can normally be reached on Monday through Friday 8:30am-6pm Eastern Time.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWN DOMAN/Primary Examiner, Art Unit 2183
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