DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendments filed 1/21/2026 have been entered and considered. The amendments to claims 1, 9, 11, 13, 18, and 20 and the newly added claims 22 and 23 are acknowledged.
In view of the amendments, the objections to claims 1 and 20 and the rejections under 35 U.S.C 112 of claims 11, 13, and 18 have been withdrawn.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 11, and 12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Objections
Claim 20 are objected to because of the following informalities: the claim recites “the layer of SiGe material are”. The examiner understands that the use of “are” is a typographical error and that it should read “wherein the layer of SiGe material is”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
Claim 1 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation " high-k gate dielectric metal”. There is insufficient antecedent basis for this limitation in the claim. The claim previously recites “high-k gate dielectric material”.
Claim 20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 20 recites the limitation " high-k gate dielectric metal”. There is insufficient antecedent basis for this limitation in the claim. The claim previously recites “high-k gate dielectric material”.
Claim 23 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 23 recites the limitation " high-k gate dielectric metal”. There is insufficient antecedent basis for this limitation in the claim. The claim previously recites “high-k gate dielectric material”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, 6, 9-10, and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Iwamoto US 20100252888 A1 (hereinafter referred to as Iwamoto), in view of Kronholz et al. US 20120156864 A1 (hereinafter referred to as Kronholz), in view of Javorka et al. US 20130032901 A1 (hereinafter referred to as Javorka), in view of Chiang et al. US 20110248351 A1 (hereinafter referred to as Chiang).
Regarding claim 1, Iwamoto teaches
A structure (“semiconductor device 3” para. 0095 FIG. 14) comprising: a p-FET gate structure (“PMOSFET” para. 0095 FIG. 14) comprising a stack of p-FET work function materials (“metal electrode layer 22 is made of a metal M1” includes TiN or TiAlN, para. 0095, which are known p-type workfunction materials as evidenced in para. 0034 of Chien et al. US 20210119033 A1 and “metal electrode layer 34 is made of a metal M2P” which are p-type workfunction materials, para. 0040 FIG. 17), an n-well (“N well 13” para. 0045) and a high-k gate dielectric material (“gate insulating film 27” that is a high-dielectric insulator stack, para. 0041) directly contacting the p-FET work function materials, each of which are over the n-well; an n-FET gate structure (“NMOSFET” para. 0095) comprising the stack of p-FET work function materials (“NMOSFET” includes “metal electrode layer 22” and “metal electrode layer 34”) directly contacting an underlying gate dielectric material (“gate insulating film 25” para. 0041) which is directly contacting a p-well (“P well 12” para. 0045); the n-well also directly abutting the p-well at a junction (as seen in FIG. 14, there is a junction of the “P well 12” and “N well 13” under the “element-isolating oxide film 11” para. 0045); polysilicon material (“p-type polysilicon electrode layer 70” para. 0077) directly contacting the stack of p-FET work function materials of the p-FET gate and the p-FET work function materials of the n-FET gate structure such that the p-FET work function materials are between and directly contacting the polysilicon material and the high-k gate dielectric material for the p-FET gate structure (“p-type polysilicon electrode layer 70” is formed directly above “metal electrode layer 34” and “gate insulating film 27” is directly below “metal electrode 22”) and the p-FET work function materials of the n-FET gate structure is directly contacting and between the underlying gate dielectric material and the polysilicon material (“p-type polysilicon electrode layer 70” is formed directly above “metal electrode layer 34” and “gate insulating film 25” is directly below “metal electrode 22”);
sidewall spacers (“offset spacer 46” para. 0061) directly contacting outer sidewalls of the stack of p-FET work function materials and the polysilicon material of the p-FET gate structure and the p-FET work function materials of the n-FET gate structure (“offset spacer 46” contacts side surfaces of “metal electrode layer 22”, “metal electrode layer 34”, and “p-type polysilicon electrode layer 70” in the “NMOSFET” and “PMOSFET”) and the underlying gate dielectric material and the polysilicon material of the n-FET gate structure (“offset spacer 46” contacts side surfaces of “p-type polysilicon electrode layer 70” and “gate insulating film 25” in “NMOSFET”), wherein the high-k gate dielectric material is confined between and directly contact the sidewall spacers (“gate insulating film 27” is between both sides of “offset spacer 46”); a trench isolation structure (“element-isolating oxide film 11” para. 0045) extending between the junction and within both the p-well of the n-FET, and the n-well of the p-FET and spaced apart from underlying semiconductor material that is devoid of the n-well and the p-well (“semiconductor substrate 10” below “P well” and “N well 13”, para. 0034), and wherein the trench isolation structure contacts and electrically isolates diffusion regions [in] the p-FET gate structure and the n-FET gate structure (“deep SD region 60” in the “NMOSFET” and “deep SD region 66” in the “PMOSFET” labeled 56 in FIG. 14), the diffusion regions are within the n-well and the p-well (“deep SD region 60” is in the “P well 12” and “deep SD region 66” is in the ”N well 13”).
Iwamoto fails to teach a layer of SiGe material directly contacting the n-well, the high-k gate dielectric material directly contacting the layer of SiGe, wherein the layer of SiGe material is confined between and directly contact the sidewall spacers, halo implants which directly contact the high-k gate dielectric material and directly contact the sidewall spacers.
Nevertheless, Kronholz teaches
a layer of SiGe material (“threshold adjusting semiconductor alloy 208, such as a silicon/germanium alloy” para. 0045 FIG. 2f-2k) directly contacting the n-well (“threshold adjusting semiconductor alloy 208” is above and in contact with “active region 202A”, para. 0045), the high-k gate dielectric material directly contacting the layer of SiGe (“dielectric material 261A” is above and contacts “threshold adjusting semiconductor alloy 208”, para. 0050), wherein the layer of SiGe material is confined between and directly contact the sidewall spacers (“threshold adjusting semiconductor alloy 208” is between the “protective liner material 265”, para. 0054).
Iwamoto and Kronholz teach gate structures comprising work function materials. The silicon germanium “threshold adjusting semiconductor alloy 208” in Kronholz is used “in order to appropriately adjust the electronic characteristics at and near the surface of the active region 202A” (para. 0045). The “threshold adjusting semiconductor alloy 208” is formed in “gate electrode structure 260A”, which is a p-channel gate structure (para. 0054). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the SiGe layer in the gate structure can enhance the electrical performance for the p-type transistor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the structure in Iwamoto with the SiGe layer taught in Kronholz. The Sige layer in the gate structure improves electrical performance for the gate of the p-FET.
However, Iwamoto, modified by Kronholz, fails to teach halo implants which directly contact the high-k gate dielectric material and directly contact the sidewall spacers.
Nevertheless, Javorka taches
halo implants (“halo/extension regions 131” para. 0019 FIG. 1E) which directly contact the high-k gate dielectric material (“high-k gate dielectric layer 115” para. 0019) and directly contact the sidewall spacers (“Spacers 111” para. 0019).
Iwamoto, modified by Kronholz, and Javorka teach structures comprising a p-FET gate and an n-FET gate. While Iwamoto teaches the formation of “extension regions 50 and 54” under the “NMOSFET” and “PMOSFET”, Javorka teaches “halo/extension regions 129 and 131” underlapping “gates 103 and 105” respectively, where the examiner understands they may be a halo region or a drain/source extension region. Chiang teaches halo implants as a method of adjusting channel threshold voltages and states “this implements heavy implantations to achieve the higher threshold voltage devices” (para. 0001), as well as reducing short channel effects, such as punch-through effects (para. 0020). A person of ordinary skill in the art before the effective filing date of the claimed invention would have recognized the halo implants in Javorka as a way of increasing channel threshold voltages instead of using the “extension regions 50 and 54”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the channel threshold voltages and minimize channel defects of the structure in Iwamoto and Kronholz through halo implantation as taught in Javorka and Chiang.
Regarding claim 2, Iwamoto, modified by Kronholz, Javorka, and Chiang, teaches the structure of claim 1, wherein the p-FET gate structure and the n-FET gate structure comprise high-k metal gate structures comprising the stack of p-FET work function materials (“gate electrode 63” of “NMOSFET” and “gate electrode 71” of “PMOSFET” comprise the workfunction materials “metal electrode layer 22” and “metal electrode layer 34”, para. 0095, and respective high-dielectric insulators “gate insulating films 25 and 27”, para. 0041. As such, the examiner considers “gate electrode 63” and “gate electrode 71” as high-k metal gate structures.), wherein the stack of p-FET work function materials is a same stack of work function materials (“gate electrode 63” of “NMOSFET” and “gate electrode 71” of “PMOSFET” comprise the workfunction materials “metal electrode layer 22” and “metal electrode layer 34”).
Regarding claim 6, Iwamoto, modified by Kronholz, Javorka, and Chiang, teaches the structure of claim 2, wherein the n-FET gate structure is devoid of the SiGe layer under the stack of p-FET work function materials (Iwamoto nor Kronholz teach the use of a SiGe layer under the p-FET work function materials).
Regarding claim 9, Iwamoto, modified by Kronholz, Javorka, and Chiang, teach wherein the halo implants in the p-well and the n-well are directly under the sidewall spacers of the p-FET gate structure and the n-FET gate structure (by forming appropriately doped “halo/extension regions 131” of Javorka in “P well 12” and under the “NMOSFET” taught between Iwamoto and Kronholz and “halo extension regions 129” in “N well 13” and under the “PMOSFET”, the halo regions are directly under the “offset spacers 46”. In other words, “halo/extension regions 131 and 129” from Jvorka replace “extension regions 50 and 54” from Iwamoto).
Regarding claim 10, Iwamoto, modified by Kronholz, Javorka, and Chiang, teaches the structure of claim 1, wherein the layer of SiGe material is under the p-FET work function material of the p-FET gate structure (“threshold adjusting semiconductor material 208” from Kronholz is under “gate insulating film 27” Iwamoto after combining. Thus, “threshold adjusting semiconductor material 208” is under “metal electrode layer 22” and “metal electrode layer 34”.) and the trench isolation structure extends partially within the p-well of the n-FET and partially within the n-well of the p-FET such that the p-well of the n-FET and the n-well of the p-FET separate the trench isolation structure from the semiconductor substate (as seen in FIG. 14, portions of “P well 12” and “N well 13” are disposed between “element-isolating oxide film 11” and “semiconductor substrate 10”).
Regarding claim 21, Iwamoto, modified by Kronholz, Javorka, and Chiang, teaches the structure of claim 1, further comprising source and drain diffusion regions adjacent to the p-FET gate within the n-well and adjacent to the n-FET gate within the p-well (“deep SD region 60” in the “P well 12” of “NMOSFET” and “deep SD region 66” in the “N well 13” in “PMOSFET” labeled 56 in FIG. 14), the trench isolation structure extending between and contacting a respective one of the source and drain diffusion regions of the p-FET gate and the n-FET gate (“element-isolating oxide film 11” contacts “deep SD region 60” and “deep SD region 66”).
Regarding claim 22, Iwamoto, modified by Kronholz, Javorka, and Chiang, teaches the structure of claim 21, wherein the halo implants directly contact the layer of SiGe material (since the SiGe “threshold adjusting semiconductor alloy 208” is formed on the lowermost part of the “gate electrode 71” of “PMOSFET” in Iwamoto, as modified, and the “halo/extension region 129” is formed below the “gate 103” of the p-type transistor in Javorka, forming “halo/extension region 129” below the “gate electrode 71” will result in it contacting the SiGe “threshold adjusting semiconductor alloy 208”).
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Iwamoto, modified by Kronholz, Javorka, and Chiang, as applied to claim 2 above, in view of Chien et al. US 20210119033 A1 (hereinafter referred to as Chien).
Regarding claim 4, Iwamoto, modified by Kronholz, Javorka, and Chiang, teach structure of claim 2, wherein one layer in the stack contains metal based on Al (“metal electrode layer 22” may comprise TiAlN, para. 0038). However, Iwamoto, modified by Kronholz, Javorka, and Chiang, fail to teach wherein the stack of p-FET work function materials comprises a stack of metals based on Al.
Nevertheless, Chien teaches p-type work function layer materials including TiAlC having a work function greater than 5.2eV (para. 0034). The materials for p-type workfunction in Iwamoto have a work function between 5-6eV (Iwamoto para. 0040). The TiAlC in Chien falls within the preferred range of workfunction for the metal layer in Iwamoto. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that TiAlC is a known material suitable for use as a p-type metal of high workfunction and can be substituted for a material used for “metal electrode layer 34” in Iwamoto. The p-FET work function materials now comprise a stack of Al based materials.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the structure taught between Iwamoto, Kronholz, Javorka, and Chiang with the aluminum p-type work function material taught in Chien. TiAlC is a known material suitable for use as a p-FET workfunction material with high workfunction. The substitution of TiAlC for the materials taught in Iwamoto achieves the stack of Al based p-FET workfunction materials.
Regarding claim 5, Iwamoto, modified by Kronholz, Javorka, Chiang, and Chien, teach the structure of claim 2, wherein the stack of p-FET work function materials comprises TiAlC, TiAl, or TaAlC (the stack of p-type workfunction layers includes TiAlC in the “metal electrode layer 34” as modified by Chien).
Claims 11-14, 18-19, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Iwamoto US 20100252888 A1 (hereinafter referred to as Iwamoto), in view of Kronholz et al. US 20120156864 A1 (hereinafter referred to as Kronholz), in view of Javorka et al. US 20130032901 A1 (hereinafter referred to as Javorka), further in view of Chiang et al. US 20110248351 A1 (hereinafter referred to as Chiang).
Regarding claim 11, Iwamoto teaches
A structure (“semiconductor device 2” para. 0087 FIG. 12) comprising: a p-FET gate structure (“PMOSFET” para. 0087 FIG. 12) comprising an n-FET work function metal material (“metal electrode layer 26 is made of a metal M2N”, para. 0087, that inludes n-type workfunction materials like Al and La as evidenced in para. 0071 of Nishi et al. US 20090152652 A1 and para. 0018 of Chen et al. US 20190067117 A1.), gate dielectric material (“gate insulating film 27” para. 0041), the p-FET gate structure being over and directly contacting an n-well (“N well 13” para. 0045), and polysilicon material (“silicon electrode layer 62” made of n-type polysilicon, para. 0087) directly contacting the stack of [n-FET work function materials] (“silicon electrode layer 62” is formed directly above “metal electrode layer 26”);
an n-FET gate structure (“NMOSFET” para. 0087) comprising a p-FET work function metal layer (“metal electrode layer 22 is made of a metal M1” para. 0087, comprising TiN or TiAlN, para. 0095, which are known p-type workfunction materials as evidenced in para. 0034 of Chien et al. US 20210119033 A1), and the gate dielectric material (“gate insulating films 25 and 27 are preferably high-dielectric insulating films” and may both comprise HfO.sub.2, para. 0041, so both are understood to be the same.) and the polysilicon material (“silicon electrode layer 62”), the gate dielectric material directly contacting an underlying p-well (“P well 12” para. 0045),
the n-well directly abutting and the underlying p-well at a junction (as seen in FIG. 14, there is a junction of the “P well 12” and “N well 13” under the “element-isolating oxide film 11” para. 0045), sidewall spacers (“offset spacer 46” para. 0061) directly contacting outer sidewalls of the n-FET workfunction metal material, the gate dielectric material and the polysilicon material of the p-FET gate structure and the p-FET work metal function material (“offset spacer 46” contacts side surfaces of “metal electrode layer 22”, “metal electrode layer 26”, and “silicon electrode layer 62” in the “PMOSFET”), the gate dielectric material and the polysilicon material of the n-FET gate structure (“offset spacer 46” contacts side surfaces of “gate insulating film 25” and “silicon electrode layer 62” in the “NMOSFET”); a shallow trench isolation structure (“element-isolating oxide film 11” para. 0045) within the junction of the n-well under the p- FET gate structure and the p-well under the n-FET gate structure, with the shallow trench isolation structure extending partially through a thickness of the p-well and the n-well such that the shallow trench isolation structure is spaced apart from semiconductor material devoid of the p-well and the n-well (“semiconductor substrate 10” below “P well” and “N well 13” and spaced apart from “element-isolating oxide film 11”, para. 0034).
However, Iwamoto fails to teach the n-FET gate structure comprising p-FET work function metal material different than the n-FET work function metal material, the polysilicon material directly contacting the stack of p-FET work function materials, sidewall spacers directly contacting outer sidewalls of the layer of SiGe, and a halo implant region in a semiconductor substrate under the sidewall spacers of the n-FET gate structure and the p-FET gate structure, the halo implant region directly contacts the layer of SiGe, wherein the layer of SiGe is also under underneath and in direct contact with the gate dielectric material and over and in direct contact with the semiconductor substrate.
Nevertheless, an alternate embodiment in Iwamoto teaches an n-FET gate structure where a p-FET workfunction material contacts the polysilicon material. The “NMOSFET” in “semiconductor device 3” comprises “metal electrode layer 34” in contact with “p-type polysilicon electrode layer 70”, where “metal electrode layer 34” comprises p-type workfunction material (para. 0040 and 0087 FIG. 14). In both cases, band discontinuity between the uppermost workfunction material and the polysilicon gate is alleviated and contact resistance between the materials is reduced (para. 0013, 0081, 0087, and 0095). The “NMOSFET” in “semiconductor device 3” has a higher gate workfunction compared to the “NMOSFET” gate in “semiconductor device 2” because of the use of “metal electrode layer 34” and “p-type polysilicon electrode layer 70”. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that a higher workfunction for the “NMOSFET” gate can be achieved by using p-type workfunction materials while maintaining a reduced band discontinuity between the p-type workfunction materials and the polysilicon gate electrode.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the structure taught in an embodiment Iwamoto with the n-FET structure taught in an alternate embodiment of Iwamoto. A higher workfunction for the gate is achieved without compromising the desired contact resistance between the workfunction materials and the polysilicon material. In this manner, the n-FET gate structure comprises p-FET workfunction metal different than the n-FET workfunction metal material in the p-FET gate structure.
However, Iwamoto fails to teach sidewall spacers directly contacting outer sidewalls of the layer of SiGe, and a halo implant region in a semiconductor substrate under the sidewall spacers of the n-FET gate structure and the p-FET gate structure, the halo implant region directly contacts the layer of SiGe, wherein the layer of SiGe is also under underneath and in direct contact with the gate dielectric material and over and in direct contact with the semiconductor substrate.
Nevertheless, Kronholz teaches
a layer of SiGe material (“threshold adjusting semiconductor alloy 208, such as a silicon/germanium alloy” para. 0045 FIG. 2f-2k), sidewall spacers directly contacting outer sidewalls of the layer of SiGe (“threshold adjusting semiconductor alloy 208” is between the “protective liner material 265”, para. 0054), wherein the layer of SiGe is also under underneath and in direct contact with the gate dielectric material (“dielectric material 261A” is above and contacts “threshold adjusting semiconductor alloy 208”, para. 0050) and over and in direct contact with the semiconductor substrate (“threshold adjusting semiconductor alloy 208” is above and in contact with “active region 202A” of “semiconductor layer 202”, para. 0045).
Iwamoto and Kronholz teach gate structures comprising work function materials. The silicon germanium “threshold adjusting semiconductor alloy 208” in Kronholz is used “in order to appropriately adjust the electronic characteristics at and near the surface of the active region 202A” (para. 0045). The “threshold adjusting semiconductor alloy 208” is formed in “gate electrode structure 260A”, which is a p-channel gate structure (para. 0054). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the SiGe layer in the gate structure can enhance the electrical performance for the p-type transistor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the structure in Iwamoto with the SiGe layer taught in Kronholz. The Sige layer in the gate structure improves electrical performance for the gate of the p-FET.
However, Iwamoto, modified by Kronholz, fails to teach a halo implant region in a semiconductor substrate under the sidewall spacers of the n-FET gate structure and the p-FET gate structure, the halo implant region directly contacts the layer of SiGe.
Nevertheless, Javorka teaches
a halo implant region (“halo/extension regions 131 and 129” para. 0019 FIG. 1E) in a semiconductor substrate (“substrate 101”, para. 0019) under the sidewall spacers (“spacers 111 and 109” para. 0018) of the n-FET gate structure (“gate 105” is of an n-type transistor, para. 0019) and the p-FET gate structure (“gate 103” is of a p-type transistor, para. 0021).
Iwamoto, modified by Kronholz, and Javorka teach structures comprising a p-FET gate and an n-FET gate. While Iwamoto teaches the formation of “extension regions 50 and 54” under the “NMOSFET” and “PMOSFET”, Javorka teaches “halo/extension regions 129 and 131” underlapping “gates 103 and 105” respectively, where the examiner understands they may be a halo region or a drain/source extension region. Chiang teaches halo implants as a method of adjusting channel threshold voltages and states “this implements heavy implantations to achieve the higher threshold voltage devices” (para. 0001), as well as reducing short channel effects, such as punch-through effects (para. 0020). A person of ordinary skill in the art before the effective filing date of the claimed invention would have recognized the halo implants in Javorka as a way of increasing channel threshold voltages instead of using the “extension regions 50 and 54”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the channel threshold voltages and minimize channel defects of the structure in Iwamoto and Kronholz through halo implantation as taught in Javorka and Chiang.
The combination of Iwamoto with Kronholz, Javorka, and Chiang further teaches
the halo implant region directly contacts the layer of SiGe (since the SiGe “threshold adjusting semiconductor alloy 208” is formed on the lowermost part of the “gate electrode 71” of “PMOSFET” in Iwamoto, as modified, and the “halo/extension region 129” is formed below the “gate 103” of the p-type transistor in Javorka, forming “halo/extension region 129” below the “gate electrode 71” will result in it contacting the SiGe “threshold adjusting semiconductor alloy 208”).
Regarding claim 12, Iwamoto, modified by Kronholz, Javorka, and Chiang, teaches the structure of claim 11, wherein the p-FET gate structure and the n-FET gate structure comprise high-k metal gate structures (“gate electrode 63” of “NMOSFET” and “gate electrode 71” of “PMOSFET” comprise respective high-dielectric insulators “gate insulating films 25 and 27”, para. 0041. As such, the examiner considers “gate electrode 63” and “gate electrode 71” as high-k metal gate structures.)
Regarding claim 13, Iwamoto, modified by Kronholz, Javorka, and Chiang, teaches the structure of claim 12, wherein the layer of SiGe is under the n-FET work function metal material (“threshold adjusting semiconductor material 208” from Kronholz is under “gate insulating film 27” of Iwamoto after combining. Thus, “threshold adjusting semiconductor material 208” is under “metal electrode layer 26”.) and above the halo implant region within an n-well (the “halo/extension region 129” from Javorka are formed under “offset spacer 46” in Iwamoto. As such, “threshold adjusting semiconductor material 208” is formed above the “halo/extension regions 129”), with source/drain diffusion regions adjacent to and contacting the halo implant (as taught in Javorka, “halo/extension regions 129” are in contact with “source/drain regions 125”, para. 0019 FIG. 1E.).
Regarding claim 14, Iwamoto, modified by Kronholz, Javorka, and Chiang, teaches the structure of claim 13, wherein the p-FET work function metal material comprises a stack of metal (after modifying with the alternate embodiment in Iwamoto the p-FET work function material comprises “metal electrode layer 22” and the “metal electrode layer 34” that are p-type workfunction materials).
Regarding claim 18, Iwamoto, modified by Kronholz, Javorka, and Chiang, teaches the structure of claim 13, wherein the halo implant region is under the p-FET gate structure and in an n-well and the n-FET gate structure in a p-well (the “halo/extension regions 129” of the p-transistor gate “gate 103” from Javorka are formed in “N well 13” under “PMOSFET” and “halo/extension regions 131” are formed in “P well 12 under “NMOSFET” in Iwamoto, as modified), with the sidewall spacers above the halo implant region (the “halo/extension regions 129 and 131” from Javorka are formed under “offset spacers 46” in Iwamoto), and wherein the layer of SiGe is under the n-FET work function material and above the halo implant region (“threshold adjusting semiconductor alloy 208” is formed under “gate insulating film 27” in the “PMOSFET” gate, as modified with Kronholz, and above “halo/extension regions 129” incorporated from Javorka);
The source/drain regions contact the halo implant region associated with the p-FET gate structure and the n-FET gate structure (“halo/extension regions 129 and 131” respectively contact “source/drain regions 125 and 127” in Javorka. As modified, “halo/extension region 131” contact “deep SD region 60” in the “NMOSFET” and “halo/extension region 129” contact “deep SD region 66” in the “PMOSFET” labeled 56 in Iwamoto);
a first isolation trench structure between the n-well and the p-well (“element-isolating oxide film 11”);
However, Iwamoto, modified by Kronholz, and Javorka fails to teach additional isolation trench structures within the p-well and the n-well and isolating the source/drain diffusion regions.
Nevertheless, Chiang further teaches
additional isolation trench structures (“solation feature 212 is formed in the substrate 210 to isolate various regions, such as first region 214 and second region 215, of the substrate 210. The isolation feature 212 also isolates the first and second device regions 214 and 215 from other devices (not shown).”, para. 0014 FIG. 4) within the p-well and the n-well (“The substrate 210 may include doped regions, such as a p-well, an n-well, or combination thereof’, para. 0013) and isolating the source/drain regions (“HDD regions 228”, para. 0023 FIG. 4. The “isolation features 212” in the left and right side of the device correspond to the ones that “isolate the first and second device regions 214 and 215 from other devices”)
Iwamoto, modified by Kronholz and Javorka, and Chiang teach n-FET and p-FET gate structures having doped well regions, spacers, and work function materials (“The gate stacks 220 and 222 include a work function layer”, para. 0017. Also, Chiang discloses in para. 0012 that “the integrated circuit device 200 could include NFETs and PFETs”.). Based on the positions of the “isolation features 212” relative to the “HDD regions 228” at the ends, they are considered to isolate the source/drain regions of the device from other devices. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the use of additional isolation trenches can isolate the source/drain regions from other adjacent devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the structure as taught between Iwamoto, Kronholz, and Javorka with the additional isolation trenches as taught in Chiang. These additional trenches help isolate the source/drain regions from adjacent structures.
Regarding claim 19, Iwamoto, modified by Kronholz, Javorka, and Chiang, teaches the structure of claim 13, wherein the layer of SiGe comprises a thickness of approximately 20A to 500A (“the layer 208 may be provided with a thickness of approximately 12 nm and less”, which is 120A or less, para. 0045 in Kronholz).
Regarding claim 23, Iwamoto, modified by Kronholz, Javorka, and Chiang structure of claim 11, wherein the halo implant region directly contacts the gate dielectric material and directly contacts the sidewall spacers (“halo/extension regions 131” in shown as in direct contact with “high-k gate dielectric layer 115” and directly contact with “Spacers 111”, Javorka para. 0019 FIG. 1E. As modified, “halo/extension regions 131” replaces “extension region 50” and contacts the “gate insulating film 27” and “offset spacer 46”).
Claim 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Iwamoto, modified by Kronholz, Javorka, and Chaing, as applied to claim 14 above, in view of Chien et al US 20210119033 A1 (hereinafter referred to as Chien).
Regarding claim 15, Iwamoto, modified by Kronholz, Javorka, and Chiang, teach structure of claim 14, wherein one layer in the stack contains metal based on Al (“metal electrode layer 22” may comprise TiAlN, para. 0038). However, Iwamoto, modified by Kronholz, Javorka, and Chiang, fail to teach wherein the stack of p-FET work function materials comprises a stack of metals based on Al.
Nevertheless, Chien teaches p-type work function layer materials including TiAlC having a work function greater than 5.2eV (para. 0034). The materials for p-type workfunction in Iwamoto have a work function between 5-6eV (Iwamoto para. 0040). The TiAlC in Chien falls within the preferred range of workfunction for the metal layer in Iwamoto. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that TiAlC is a known material suitable for use as a p-type metal of high workfunction and can be substituted for a material used for “metal electrode layer 34” in Iwamoto. The p-FET work function materials now comprise a stack of Al based materials.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the structure taught between Iwamoto, Kronholz, Javorka, and Chiang with the aluminum p-type work function material taught in Chien. TiAlC is a known material suitable for use as a p-FET workfunction material with high workfunction. The substitution of TiAlC for the materials taught in Iwamoto achieves the stack of Al based p-FET workfunction materials.
Regarding claim 16, Iwamoto, modified by Kronholz, Javorka, Chiang, and Chien, teach the structure of claim 13, wherein the stack of p-FET work function materials comprises TiAlC, TiAl, or TaAlC (the stack of p-type workfunction layers includes TiAlC in the “metal electrode layer 34” as modified by Chien).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Iwamoto, modified by Kronholz, Javorka, and Chiang, as applied to claim 13 above, in view of Yu et al. US 20130126976 A1 (hereinafter referred to as Yu).
Iwamoto, modified by Kronholz, Javorka, and Chiang, teach the structure of claim 13, wherein the n-FET work function metal material comprises La (“metal electrode layer 26 is made of a metal M2N”, para. 0087, that inludes n-type workfunction materials like La).
However, Iwamoto, modified by Kronholz and Chiang fails to teach wherein the n-FET work function metal material comprises La doped oxides.
Nevertheless, Yu teaches
wherein the n-FET work function material comprises La doped oxides (“n-type work function metal layer 15 composed of TiN, LaO”, para. 0024).
Iwamoto, modified by Kronholz, Javorka, and Chiang, and Yu teach n-FET and p-FET structures with workfunction adjusting layers. Yu teaches LaO as an n-type work function layer. As further evidenced in para. 0042 of Park et al. US 20200083220 A1, LaO is a known n-type workfunction material similar to La, TaN, and Nb. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that LaO is a suitable material that can be used as an n-type workfunction layer. Substitution for LaO achieves the expected result of modifying the workfunction of the “PMOSFET”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the structure taught between Iwamoto, Kronholz, Javorka,and Chiang with the La oxide taught in Yu. LaO is a known material suitable for use as an n-FET workfunction material.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Iwamoto US 20100252888 A1 (hereinafter referred to as Iwamoto), in view of Kronholz et al. US 20120156864 A1 (hereinafter referred to as Kronholz), ), in view of Javorka et al. US 20130032901 A1 (hereinafter referred to as Javorka), in view of Chiang et al. US 20110248351 A1 (hereinafter referred to as Chiang).
Iwamoto teaches
A method (a method of forming “semiconductor device 3” para. 0095 FIG. 14) comprising: forming a p-FET gate structure (“PMOSFET” para. 0095 FIG. 14) comprising forming a stack of p-FET work function materials (“metal electrode layer 22 is made of a metal M1” which includes TiN or TiAlN, para. 0095, and “metal electrode layer 34 is made of a metal M2P” which are p-type workfunction materials, para. 0040 FIG. 17), polysilicon material (“p-type polysilicon electrode layer 70” para. 0077) over the p-FET work function materials, and high-k gate dielectric material (“gate insulating film 27” that is a high-dielectric insulator stack, para. 0041) directly contacting the p-FET work function materials, each of which are over an n-well (“N well 13” para. 0045);
forming an n-FET gate structure (“NMOSFET” para. 0095) comprising the stack of p-FET work function materials (“NMOSFET” includes “metal electrode layer 22” and “metal electrode layer 34) and the polysilicon material (“p-type polysilicon electrode layer 70”) over a p-well (“P well 12” para. 0045) such that the p-FET work function materials are between and directly contacting the polysilicon material and the high-k gate dielectric material (“p-type polysilicon electrode layer 70” is formed directly above “metal electrode layer 34” and “gate insulating film 27” is directly below “metal electrode layer 22”), wherein the n-well directly abuts the p-well at a junction (as seen in FIG. 14, there is a junction of the “P well 12” and “N well 13” under the “element-isolating oxide film 11” para. 0045);
forming sidewall spacers (“offset spacer 46” para. 0061) on and directly contacting outer sidewalls of the stack of p-FET work function materials and the polysilicon material of the p-FET gate structure and the n-FET gate structure (“offset spacer 46” contacts side surfaces of “metal electrode layer 22”, “metal electrode layer 34”, and “p-type polysilicon electrode layer 70” in the “NMOSFET” and “PMOSFET”); and
forming a trench isolation structure (“element-isolating oxide film 11” para. 0045) extending between the junction and within both the p- well of the n-FET and the n-well of the p-FET and spaced apart from underlying semiconductor material that is devoid of the n-well and the p-well well (“semiconductor substrate 10” below “P well” and “N well 13”, para. 0034), wherein the trench isolation structure contacts and electrically isolates diffusions regions [in] the p-FET gate structure and the n-FET gate structure (“deep SD region 60” in the “NMOSFET” and “deep SD region 66” in the “PMOSFET” labeled 56 in FIG. 14), the diffusions regions are within the n-well and the p-well (“deep SD region 60” is in the “P well 12” and “deep SD region 66” is in the ”N well 13”).
However, Iwamoto fails to teach a layer of SiGe material under the p-FET work function materials, high-k gate dielectric material between and directly contacting the layer of SiGe material and the p-FET work function materials, wherein the layer of SiGe material is also confined between and directly contact the sidewall spacers; and forming a plurality of halo implants which directly contacts the high-k gate dielectric metal and directly contacts the sidewall spacers.
Nevertheless, Kronholz teaches “threshold adjusting semiconductor alloy 208” made of silicon/germanium alloy (para. 0045 FIG. 2f-2k) directly contacting the high-k dielectric “dielectric material 261A” below (para. 0050) and below conductive materials that adjust the work function of “gate electrode structure 260A” of the P-channel transistor (para. 0053). The “threshold adjusting semiconductor alloy 208” is between the “protective liner material 265” (para. 0054). The silicon germanium “threshold adjusting semiconductor alloy 208” in Kronholz is used “in order to appropriately adjust the electronic characteristics at and near the surface of the active region 202A” (para. 0045). The “threshold adjusting semiconductor alloy 208” is formed in “gate electrode structure 260A”, which is a p-channel gate structure (para. 0054). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the SiGe layer below the high-k dielectric in the gate structure can enhance the electrical performance for the p-type transistor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the structure in Iwamoto with the SiGe layer taught in Kronholz. The SiGe layer in the gate structure improves electrical performance for the gate of the p-FET.
However, Iwamoto, modified by Kronholz, fails to teach forming a plurality of halo implants which directly contacts the high-k gate dielectric material and directly contacts the sidewall spacers.
Nevertheless, Javorka taches
Forming a plurality of halo implants (“halo/extension regions 131” para. 0019 FIG. 1E) which directly contact the high-k gate dielectric material (“high-k gate dielectric layer 115” para. 0019) and directly contact the sidewall spacers (“Spacers 111” para. 0019).
Iwamoto, modified by Kronholz, and Javorka teach structures comprising a p-FET gate and an n-FET gate. While Iwamoto teaches the formation of “extension regions 50 and 54” under the “NMOSFET” and “PMOSFET”, Javorka teaches “halo/extension regions 129 and 131” underlapping “gates 103 and 105” respectively, where the examiner understands they may be a halo region or a drain/source extension region. Chiang teaches halo implants as a method of adjusting channel threshold voltages and states “this implements heavy implantations to achieve the higher threshold voltage devices” (para. 0001), as well as reducing short channel effects, such as punch-through effects (para. 0020). A person of ordinary skill in the art before the effective filing date of the claimed invention would have recognized the halo implants in Javorka as a way of increasing channel threshold voltages instead of using the “extension regions 50 and 54”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the channel threshold voltages and minimize channel defects of the structure in Iwamoto and Kronholz through halo implantation as taught in Javorka and Chiang.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC MULERO FLORES whose telephone number is (571)270-0070. The examiner can normally be reached Mon-Fri 8am-5pm (typically).
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/ERIC MANUEL MULERO FLORES/ Examiner, Art Unit 2898
/JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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