DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/6/2026 has been entered.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the high-k dielectric layer extending into the source/drain region as found in claim 1 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Nowhere does it appear that the new limitation “and the high-k dielectric layer extends into the source/drain region” was originally shown or described. The high-k dielectric layers as presented in the drawings exist outside of any source/drain region. Therefore, the quoted limitation above introduces new matter.
Claims 2-10 inherit this rejection for new matter.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 and 21-27 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
(Re Claim 1) The structure required by “and the high-k dielectric extends into the source/drain region” is unclear as the high-k dielectric is shown outside of any source/drain region.
During examination, the quoted limitation above was understood to require only that the high-k dielectric is adjacent to the source/drain region.
Claims 2-10 inherit this rejection for indefiniteness.
(Re Claim 21) “[T]he first source/drain region” and “the top of the silicide layer” lacks antecedence.
During examination, these limitations were respectively read as “the source/drain region” and “a top of the silicide layer”.
Claims 22-27 inherit these rejections for lack of antecedence.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 4-10 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2020/0126798), and Metz et al. (US 7,7425,500) both of record, and Wang et al. (US 2021/0083090) newly cited.
(Re Claim 1) Lin teaches a semiconductor device, comprising: a substrate (202+204; Fig. 14A); and a first transistor (Fig. 2B markup), including:
a first channel region (region containing 204A within the area marked first transistor; Fig. 2B markup, and Fig. 3A and 14A) overlying the substrate; a source/drain region (250; Fig. 2B markup and Fig. 14A; “a source/drain region” includes the plural form, as discussed on p. 3 of the instant specification) in contact (leftmost 250 part; Fig. 14A, ¶37) with the first channel region, the source/drain region having a first surface opposite the substrate and side surfaces extending from the first surface (Fig. 13B markup); a silicide layer (270 on the left; Fig. 14B) formed on the first surface and the side surfaces of the source/drain region; a dielectric fin structure (leftmost 206; Fig. 14B) formed on the substrate (compare Fig. 12B and 13B); and
a shallow trench isolation region (208; Fig. 13B).
Lin has not been shown to explicitly teach the semiconductor device comprising:
a dielectric fin structure formed on the substrate, wherein the dielectric fin structure includes:
a first dielectric layer including a sidewall;
a second dielectric layer within the first dielectric layer;
an end defined by the first dielectric layer and the second dielectric layer; and
a high-k dielectric layer on the end and the high-k dielectric layer including an end surface facing away from the first dielectric layer and the second dielectric layer;
wherein the silicide layer extends to an uppermost surface of the shallow trench isolation region, the silicide layer terminates before reaching the end surface of the high-k dielectric layer, and the high-k dielectric layer extends into the source/drain region.
However, Lin states that the silicide layer 270 may completely fill the recess 260 “depending upon the value of the width w1’ of the recess 260…the silicide layer 270 may be formed to a thickness of about 5 nm to about 10 nm, which may range from about 30% to about 100% of the width w1’ of the recess 260” (Fig. 11B, ¶41).
Metz teaches forming a silicide layer (30; Fig. 3) conformally around a source/drain region (20; Fig. 3).
As the recess 260 is bounded by the dielectric fin structure and the shallow isolation region, when the recess is completely filled with the silicide layer 270 the dielectric fin structure will contact the silicide layer on one of the side surfaces (left; Fig. 14B markup) of the source/drain region.
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to do so as filling the recess with the silicide layer is a disclosed alternative embodiment in Lin and increases the contact area between the silicide layer 270 and the source/drain regions 250, reducing contact resistance between the source/drain regions and an eventual source/drain contact (Lin: ¶42).
This results in the dielectric fin structure being in direct contact with the silicide layer on one of the side surfaces (left side surface; Fig. 14B) of the source/drain region.
A PHOSITA would find it obvious to use either ALD or CVD as taught by Metz as this allows for conformal metal deposition and subsequent silicide layer formation on the entire exposed surface of the source/drain layer of Lin (Metz: col. 3 ln. 9-14, col. 3 ln. 26-30; Lin: “In one example, a metal layer (e.g., nickel) may be deposited over the device 200 by a deposition process such as CVD, ALD, PVD, other suitable processes, or combinations thereof.”; ¶41) decreasing the contact resistance (Lin: ¶42). As a consequence of this deposition process when filling the recess 260 of Lin the silicide layer 270 will extend to an uppermost surface (top as seen in Fig. 14B) of a shallow trench isolation region.
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Wang teaches a dielectric fin structure (114; Fig. 3A), wherein the dielectric fin structure includes:
a first dielectric layer (116; Fig. 3A) including a sidewall (left side);
a second dielectric layer (118; Fig. 3A) within the first dielectric layer;
an end (Fig. 3A markup) defined by the first dielectric layer and the second dielectric layer; and
a high-k dielectric layer (120; Fig. 3A) on the end and the high-k dielectric layer including an end surface (topmost surface as seen in Fig. 3A) facing away from the first dielectric layer and the second dielectric layer.
A PHOSITA would find it obvious to utilize the dielectric fin structure arrangement of Wang for the dielectric fin structure of modified Lin, to provide protection to the dielectric fin structure during processing through the mask effect of the high-k dielectric (Wang: ¶41).
Doing so results in the silicide layer terminating before reaching the end surface of the high-k dielectric (due to separation provided by the first dielectric layer 116), and the high-k dielectric layer extends into the source/drain region (see the 112(b) rejection above).
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(Re Claim 2) Modified Lin teaches the device of claim 1, wherein the first channel region includes a plurality of first semiconductor nanostructures (plurality of 204A portions; compare Fig. 3A and 14A).
(Re Claim 4) Modified Lin teaches the semiconductor device of claim 1, wherein the silicide layer extends at least partially between the substrate and the source/drain region (Fig. 14B).
(Re Claim 5) Modified Lin teaches the semiconductor device of claim 1, wherein the silicide layer has a thickness within a range from 1 nm to 10 nm (¶41).
(Re Claim 6) Modified Lin teaches the semiconductor device of claim 1, wherein the silicide layer covers the first surface and the side surfaces of the source/drain region (Fig. 14B).
(Re Claim 7) Modified Lin teaches the semiconductor device of claim 1, further comprising a second transistor (Fig. 2B markup) including a second channel region (region containing 204A within the area marked second transistor; Fig. 2B markup, and Fig. 3A and 14A), wherein the source/drain region is in contact with the second channel region (250 part second from left; Fig. 14A).
(Re Claim 8) Modified Lin teaches the semiconductor device of claim 7, wherein the first transistor includes a first gate electrode (leftmost 280 parts; Fig. 14A) overlying the first channel region (Fig. 14A), the second transistor includes a second gate electrode (280 parts second from the left; Fig. 14A) overlying the second channel region, and the silicide layer (Fig. 14A) is positioned between the first and second gate electrodes.
(Re Claim 9) Modified Lin teaches the semiconductor device of claim 8, wherein the first channel region includes a plurality of first semiconductor nanostructures (plurality of 204A portions overlapping with the first transistor region; Fig. 3A and 14A) spaced apart from one another and overlying the substrate (Fig. 14A), the second channel region includes a plurality of second semiconductor nanostructures (plurality of 204A portions overlapping with the second transistor region; Fig. 3A and 14A) spaced apart from one another and overlying the substrate (Fig. 14A), the first gate electrode surrounds the first semiconductor nanostructures (Fig. 14A), and the second gate electrode surrounds the second semiconductor nanostructures (Fig. 14A).
(Re Claim 10) Modified Lin teaches the semiconductor device of claim 9, wherein the silicide layer extends to an uppermost surface (top surface of 204; Fig. 14B) of the substrate (due to filling of recess 260 with silicide layer 270 through conformal deposition as demonstrated by Metz; see rejection of claim 1).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2020/0126798), and Metz et al. (US 7,7425,500) both of record, and Wang et al. (US 2021/0083090) newly cited, and further in view of Ching et al. (US 2019/0067120) referred to as Ching120, and Bouche et al. (US 2021/0305362), both of record, with reference to Lin et al. (US 10,847,373) referred to as Lin373, the issued patent1, of record.
(Re Claim 3) Modified Lin teaches the semiconductor device of claim 1, comprising a source/drain contact (290; Fig. 14B) on the first surface of the silicide layer (Lin373: Col. 13 Ln. 23-25) wherein the source/drain contact covers the source/drain region (Fig. 14B).
Modified Lin does not explicitly teach the semiconductor device wherein the source/drain contact covers an additional source/drain region.
Ching120 teaches forming a source/drain contact (1302; Fig. 8D) covering a source/drain region (1004 contacting 504c; Fig. 8D, ¶¶84-85) and an additional source/drain region (1004 contacting 504d; Fig. 8D, ¶¶84-85).
Bouche teaches forming source/drain contacts (164; Fig. 1A) such that they cover any number of source/drain regions (128/130; Fig. 1, ¶23).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the source/drain contact of modified Lin such that it covers the source/drain region (left 254; Fig. 14B) and an additional source/drain region (right 254; Fig. 14B), bridging the two source/drain regions in the manner taught by Ching120, as forming contacts to source/drain regions predictably results in an electrical connection and changing source/drain contact connections is a matter of design choice (Bouche: “multiple S/D regions 128/130, this is simply illustrative, and the S/D contacts 164 may be arranged so as to isolate and connect various ones of the S/D regions 128/130 as desired.”; ¶23), dependent on the overall circuit design comprised of transistors, taking into account e.g., parasitic capacitance or routing length. See Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
Claims 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2020/0126798) of record, and Wang et al. (US 2021/0083090) newly cited.
(Re Claim 18) Lin teaches a device, comprising: a substrate (202; Fig. 14A); a first transistor on the substrate (Fig. 2B markup), the first transistor including a plurality of first semiconductor nanostructures (plurality of 204A portions overlapping with the first transistor region; Fig. 3A and 14A) corresponding to a channel region of the first transistor (region containing 204A within the area marked first transistor; Fig. 2B markup, and Fig. 3A and 14A); a second transistor (Fig. 2B markup) on the substrate, the second transistor including a plurality of second semiconductor nanostructures (plurality of 204A portions overlapping with the second transistor region; Fig. 3A and 14A) corresponding to a channel region of the second transistor (region containing 204A within the area marked second transistor; Fig. 2B markup, and Fig. 3A and 14A);
a source/drain region (250; Fig. 2B markup and Fig. 14A; “a source/drain region” includes the plural form, as discussed in p. 3 of the instant specification) in contact with the plurality of first semiconductor nanostructures and the plurality of second semiconductor nanostructures along a first direction (“first direction” is top to bottom as seen in Fig. 14A); a first dielectric fin structure (leftmost 206; Fig. 14B) and a second dielectric fin structure (rightmost 206; Fig. 14B) adjacent to opposite sides of the source/drain region along a second direction that is transverse to the first direction (“second direction” is left to right as seen in Fig. 14B); and a silicide layer (270; Fig. 14B) on a top surface of the source/drain region (Fig. 14B markup), the silicide layer extending laterally between the first and second dielectric fin structures and the source/drain region (Fig. 14B).
Lin has not been shown to explicitly teach the device, wherein first dielectric fin structure includes a first high-k dielectric layer at a first upper end of the first dielectric fin structure, and wherein the second dielectric fin structure includes a second high-k dielectric layer at a second upper end of the second dielectric fin structure; and the silicide layer is in direct contact with a first sidewall of the first dielectric fin structure at least partially defined by the first high-k dielectric layer and the silicide layer is in direct contact with a second sidewall of the second dielectric fin structure at least partially defined by second high-k dielectric layer.
However, Lin states that the silicide layer 270 may completely fill the recess 260 “depending upon the value of the width w1’ of the recess 260…the silicide layer 270 may be formed to a thickness of about 5 nm to about 10 nm, which may range from about 30% to about 100% of the width w1’ of the recess 260” (Fig. 11B, ¶41).
As the recess 260 is bounded by the dielectric fin structure and the shallow isolation region, when the recess is completely filled with the silicide layer 270 the dielectric fin structure will contact the silicide layer on one of the side surfaces (left; Fig. 14B markup) of the source/drain region.
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to do so as filling the recess with the silicide layer is a disclosed alternative embodiment in Lin and increases the contact area between the silicide layer 270 and the source/drain regions 250, reducing contact resistance between the source/drain regions and an eventual source/drain contact (Lin: ¶42).
This results in the silicide layer being in direct contact with a sidewall (right sidewall of the leftmost 206; Fig. 14B) of the first dielectric fin structure.
Wang teaches a dielectric fin structure (114; Fig. 3A), wherein the dielectric fin structure includes a high-k dielectric layer (120; Fig. 3A) on at an upper end of the dielectric fin structure.
A PHOSITA would find it obvious to utilize the dielectric fin structure arrangement of Wang for the first and second dielectric fin structures of modified Lin, to provide protection to the dielectric fin structures during processing through the mask effect of the high-k dielectric (Wang: ¶41).
Doing so results the in first dielectric fin structure including a first high-k dielectric layer (corresponding to 120 from Wang) at a first upper end (corresponding to the upper end shown in Wang’s Fig. 3A markup) of the first dielectric fin structure, and wherein the second dielectric fin structure includes a second high-k dielectric layer (corresponding to 120 from Wang) at a second upper end (corresponding to the upper end shown in Wang’s Fig. 3A markup) of the second dielectric fin structure; and the silicide layer is in direct contact with a first sidewall (corresponding to a right sidewall as shown in Wang’s Fig. 3A markup) of the first dielectric fin structure at least partially defined by the first high-k dielectric layer (Wang: Fig. 3A) and the silicide layer is in direct contact with a second sidewall (corresponding to the left sidewall as shown in Wang’s Fig. 3A markup) of the second dielectric fin structure at least partially defined by second high-k dielectric layer (Wang: Fig. 3A).
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(Re Claim 20) Modified Lin teaches the device of claim 18, wherein the silicide layer extends at least partially between the substrate and the source/drain region (Fig. 13B).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2020/0126798) of record, and Wang et al. (US 2021/0083090) newly cited, as applied to claim 18 above, with reference to Lin et al. (US 10,847,373) referred to as Lin373, the issued patent2, of record.
(Re Claim 19) Modified Lin teaches the device of claim 18, further comprising a conductive source/drain contact (290; Fig. 13B) on the silicide layer (Lin373: Col. 13 Ln. 23-25).
Claims 21-22 and 24-26 are rejected under 35 U.S.C. 103 as being unpatentable over Ching et al. (US 2020/0243666) newly cited.
(Re Claim 21) Ching teaches semiconductor device (the device present at the step shown in Fig. 8E), comprising: a substrate (102; Fig. 8E); a transistor on the substrate (the transistor associated with 160b; Fig. 8E), the transistor including: a channel region (each 106+152+154; Fig. 8E) comprising a plurality of semiconductor nanostructures (106; Fig. 8E) overlying the substrate (Fig. 8E); a source/drain region (138; Fig. 8E; “a source/drain region” includes the plural form, as discussed in p. 3 of the instant specification) in contact with the channel region (Fig. 7G and 8E), the source/drain region having a first surface (top angled surfaces; Fig. 7G) opposite the substrate and side surfaces (left and right surfaces extending from the angled surfaces; Fig. 7G) extending from the first surface; and a first dielectric fin structure (the left 117+118+120; Fig. 8C) on the substrate, the first dielectric fin structure further includes: a first dielectric layer (117; Fig. 8C); a second dielectric layer (118; Fig. 18C) within the first dielectric layer; a first end (topmost part of 117+118; Fig. 8C) defined by the first dielectric layer and the second dielectric layer; and a first high-k dielectric layer (left 120; Fig. 8C) on the first end and the first high-k dielectric layer including a first end surface (topmost surface of 120; Fig. 8C) facing away from the first dielectric layer and the second dielectric layer; a second dielectric fin structure (the right 117+118+120; Fig. 8C) on the substrate, the second dielectric fin structure including: a third dielectric layer (117; Fig. 8C); a fourth dielectric layer (118; Fig. 8C) within the third dielectric layer; a second end (topmost surface of 117+118; Fig. 8C) defined by the third dielectric layer and the fourth dielectric layer; and a second high-k dielectric layer (right 120; Fig. 8C) on the second end and the second high-k dielectric layer including a second end surface (topmost surface of 120; Fig. 8C) facing away from the third dielectric layer and the fourth dielectric layer;
Ching has not been shown to teach a device wherein a silicide layer on the first surface and the side surfaces of the first source/drain region, wherein the first high-k dielectric layer of the first dielectric fin structure and the second high-k dielectric layer of the second dielectric fin structure protrudes from the top of the silicide layer.
Ching teaches forming a silicide layer (172; Fig. 5A) and a source/drain contact (174; Fig. 5A) on dielectric fin structures (118+120; Fig. 5A and 5B).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form a silicide layer on the source/drain region of Ching’s Fig. 8E embodiment, as shown in Ching’s Fig. 5A embodiment, to reduce contact resistance; and a PHOSITA would find it obvious to a form source/drain contact connected to the source/drain region as taught by Ching’s Fig. 5A to provide for an electrical connection to Ching’s device allowing for power or logical operations to be routed to or through Ching’s device.
This results in modified Ching teaching a silicide layer (Ching’s 172 now incorporated in the embodiment seen in Ching’s Fig. 7H) on the first surface (Ching: Fig. 5A) and the side surfaces (“on” does not require contact) of the source/drain region, wherein the first high-k dielectric layer of the first dielectric fin structure and the second high-k dielectric layer of the second dielectric fin structure protrudes from the top (the angled top surface of the silicide layer) of the silicide layer (the silicide layer is formed up to the ends of the dielectric fin structure, as seen in Ching’s Fig. 5A, while the first and second high-k dielectric layers are formed starting from that point and above it),
(Re Claim 22) Modified Ching teaches the semiconductor device of claim 21, wherein the silicide layer extends at least partially between the substrate and the source/drain region (compare Fig. 5A and 7H; see also the Fig. 5A markup).
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(Re Claim 24) Modified Ching teaches the semiconductor device of claim 21, further comprising a gate electrode (156; Fig. 8E) surrounding the plurality of semiconductor nanostructures.
(Re Claim 25) Modified Ching teaches the semiconductor device of claim 21, further comprising a source/drain contact on the first surface of the silicide layer (as taught by Ching’s Fig. 5A).
(Re Claim 26) Modified Ching teaches the semiconductor device of claim 21, wherein the silicide layer covers the entirety of the first surface (Ching: Fig. 5A) and the entirety of the side surfaces of the source/drain region (“covers” does not require contact. The entirety of the side surfaces are covered from above by the silicide layer).
Claims 23 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Ching et al. (US 2020/0243666) newly cited as applied to claim 21 above, and further in view of Lin et al. (US 2020/0126798) of record.
(Re Claim 23) Modified Ching teaches the semiconductor device of claim 21, but has not been explicitly shown to teach the device wherein the silicide layer has a thickness within a range from 1 nm to 10 nm.
Lin teaches forming a silicide layer with a thickness of about 5 nm to about 10 nm (Lin: ¶41).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to utilize the thicknesses provided by Lin when forming the silicide layer of modified Ching, as Lin’s thicknesses are known to provide a conformal silicide layer. Also, In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976).
(Re Claim 27) Modified Ching teaches the semiconductor device of claim 21, but has not been explicitly shown to teach the device wherein the silicide layer includes one or more of titanium silicide, cobalt silicide, ruthenium silicide, aluminum silicide, or nickel silicide.
Ching is silent with respect to a particular material composition of the silicide layer.
Lin teaches forming a silicide layer using e.g., titanium silicide (¶41).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the silicide layer using titanium silicide as taught by Lin, as this allows for forming a lower contact resistance silicide layer. The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). "Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
Response to Arguments
Applicant's arguments filed 4/6/2026 have been fully considered but they are moot in view of the new rejections.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chiang et al. (US 2021/0057525) teaches a dielectric fin structure (112; Fig. 6) with a high-k dielectric (117+119; ¶31).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christopher A Schodde whose telephone number is (571)270-1974. The examiner can normally be reached M-F 1000-1800 EST.
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/CHRISTOPHER A. SCHODDE/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
1 Noting in Lin’s issued patent, paragraph 49 (corresponding to Col. 13 Ln. 23-25 of the patent) of the originally filed disclosure was amended to recite “an S/D contact”.
2 Noting in Lin’s issued patent, paragraph 49 (corresponding to Col. 13 Ln. 23-25 of the patent) of the originally filed disclosure was amended to recite “an S/D contact”.
Prosecution Insights