Attorney's Docket Number: 0756-12274
Filing Date: 1/3/2022
Continuing Data: 6/22/2011 (US 13/166,073)
Claimed Priority Dates: 4/28/2011 (JP 2011-100534)
7/2/2010 (JP 2010-152179)
Inventors: Yamazaki et al.
Examiner: Marcos D. Pizarro
DETAILED ACTION
This Office action responds to the amendment filed on 11/4/2025.
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions. In the event the determination of the status of the application as subject to pre-AIA is incorrect, any correction of the statutory basis for a rejection as subject to AIA instead will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination (RCE) under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after the final rejection in paper no. 15, mailed on 8/19/2025. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/4/2025 has been entered.
Amendment Status
The RCE submission filed on 11/4/2025 as an amendment in reply to paper no. 15 has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 2, 5, 8, 9, 11, 13-21.
Claim Rejections - 35 USC § 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims under pre-AIA 35 U.S.C. 103(a), the examiner presumes that the subject matter of the various claims was commonly owned at the time any inventions covered therein were made absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and invention dates of each claim that was not commonly owned at the time a later invention was made in order for the examiner to consider the applicability of pre-AIA 35 U.S.C. 103(c) and potential pre-AIA 35 U.S.C. 102(e), (f) or (g) prior art under pre-AIA 35 U.S.C. 103(a).
Claims 2, 5, 9, 11, 13-15 and 18-21 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Yamazaki (US 2010/0025678) in view of Bojarczuk (US 2006/0102968).
Regarding claim 2, Yamazaki (see, e.g., fig. 1D) shows most aspects of the instant invention including a semiconductor device comprising:
A gate insulating layer 102
A first gate electrode 101 in contact with one surface of the gate insulating layer
An oxide semiconductor layer 103 in contact with the other surface of the gate insulating layer and overlapping the first gate electrode
A buffer layer 104 over and in contact with the semiconductor layer
Source 105a and drain 105b electrodes over and in contact with the buffer layer
wherein:
The source 105a and drain 105b electrodes include at least one of tungsten, platinum and molybdenum (see, e.g., par. 0108), and
The buffer layer 104 always exists between the source/drain electrodes 105 and the gate insulating layer 102
Regarding claim 11, Yamazaki (see, e.g., fig. 1D) shows most aspects of the instant invention including a semiconductor device comprising:
A gate insulating layer 102
A first gate electrode 101 in contact with one surface of the gate insulating layer
An oxide semiconductor layer 103 in contact with the other surface of the gate insulating layer and overlapping the first gate electrode
A buffer layer 104 over and in contact with the semiconductor layer
An oxide insulating layer which is in contact with the oxide semiconductor layer (see, e.g., par.0119)
Source 105a and drain 105b electrodes which are electrically connected to the semiconductor layer
wherein:
The source 105a and drain 105b electrodes include at least one of tungsten, platinum and molybdenum (see, e.g., par. 0108), and
The buffer layer 104 always exists between the source/drain electrodes 105 and the gate insulating layer 102
Regarding claims 2 and 11, Yamazaki (see, e.g., par. 0100) shows the gate insulating layer 102 includes aluminum oxide. He, however, fails to teach the gate insulating including at least one of gallium oxide, gallium aluminum oxide, and aluminum gallium oxide.
Bojarczuk teach that aluminum oxide (AlO) and gallium oxide (GaO) are both high-k dielectric materials suitable for use as gate dielectrics (see, e.g., Bojarczuk: par. 0030).
It would have been obvious to one of ordinary skill in the art at the time of filing the invention to modify the gate insulating layer of Yamazaki to include gallium oxide in place of aluminum oxide, as taught by Bojarczuk, because Bojarczuk identifies gallium oxide and aluminum oxide as alternative high-k gate dielectric materials used for the same purpose, and one of ordinary skill in the art would have reasonably expected such a substitution to maintain the insulating function of the gate dielectric.
The substitution of one known high-k gate dielectric material for another known high-k gate dielectric material used for the same purpose constitutes a simple substitution of known materials yielding predictable results, and therefore would have been obvious. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Regarding claim 13, Yamazaki (see, e.g., pars. 0119 and 0100) teaches that the oxide insulating layer includes at least one of gallium oxide, aluminum oxide, gallium aluminum oxide, and aluminum gallium oxide.
Regarding claims 5 and 14, Yamazaki (see, e.g., par. 0102) shows that the thickness of the oxide semiconductor layer 103 is greater than or equal to 3 nm and less than or equal to 30 nm.
Regarding claim 15, Yamazaki (see, e.g., pars. 0119 and 0100) shows that the oxide insulating layer contains a Group 13 element.
Regarding claims 9 and 18, Yamazaki (see, e.g., pars. 0108 and 0110) shows that the nitrogen concentrations of the source 105a and drain 105b electrode are 2x1019 atoms/cm3 or lower.
Regarding claim 19, Yamazaki (see, e.g., pars. 0119 and 0100) shows that the oxide insulating layer comprises a metal oxide.
Regarding claims 20 and 21, Yamazaki teaches that the nitrogen concentration of the semiconductor layer 103 and buffer layer 104 is lower than 2x1019 atoms/cm3 and 5x1018 atoms/cm3, respectively (see, e.g., pars. 0102, 105 and 106).
Claims 8, 16 and 17 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Yamazaki/Bojarczuk in view of Shieh (US 2010/0012932) and Son (US 2008/0299702).
Regarding claims 8, 16 and 17, Yamazaki/Bojarczuk fail to teach that the gate insulating layer 102 and oxide insulating layer contain oxygen with a composition proportion higher than a stoichiometric proportion.
Along these lines, Shieh (see, e.g., par.0018/ll.1-5 and par. 0020) suggests using the oxygen composition of the gate insulating and oxide insulating layers to adjust the threshold voltage of TFTs. Shieh uses an oxygen-rich gate insulating layer to reduce the carrier concentration in the channel and adjust the breakdown voltage (see, e.g., pars.0018 and 0020). Son teaches the same with respect to the oxide insulating layer. That is, Son uses an oxygen-rich oxide insulating layer to reduce the carrier concentration and adjust the breakdown voltage of the TFT (see, e.g., par. 0035, 0036 and 0040).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to have an oxygen composition higher than the stoichiometric composition for the gate insulating and oxide insulating layers of Yamazaki/Bojarczuk, as suggested by Shieh and Son, to reduce the carrier concentration in the channel and adjust its breakdown voltage.
Response to Arguments
Applicant’s arguments with respect to the claims have been considered but are moot in view of the new grounds of rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Marcos Pizarro at 571-272-1716 and between the hours of 9:00 AM to 7:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Marcos.Pizarro@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy, can be reached on 571-272-1705.
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/Marcos D. Pizarro/Primary Examiner, Art Unit 2814
MP/mp
1 February 2026