DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 9,099,999, as disclosed in previous office actions) in view of He (US 2021/0210460).
As for claim 19, Wang et al. disclose in Figs. 2-4 and the related text a method of forming an integrated chip structure, comprising:
processing a first substrate according to a first fabrication process to form a first chiplet 10-1 predominantly having a first plurality of devices (col. 3 lines 2-55) and a first plurality of interconnects 104 over the first plurality of devices, wherein the first plurality of devices are a first type of integrated chip device (col. 3 lines 2-55), and wherein the first fabrication process is associated with a first technology node having a first minimum feature size (col. 4 lines 31-59);
processing a second substrate according to a second fabrication process to form a second chiplet 10-3 predominantly having a second plurality of devices (col. 3 lines 2-55) and a second plurality of interconnects 104 over the second plurality of devices, wherein the second plurality of devices are a second type of integrated chip device that is different than the first type of integrated chip device (col. 3 lines 2-55), and wherein the second fabrication process is associated with a second technology node having a second minimum feature size that is different than the first minimum feature size (Fig. 4 and col. 4 lines 31-59); and
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processing a third substrate according to a third fabrication process to form a third chiplet 10-4 predominantly having a third plurality of devices (col. 3 lines 2-55) and a third plurality of interconnects 104 over the third plurality of devices, wherein the third plurality of devices are a third type of integrated chip device that is different than the first type of integrated chip device and the second type of integrated chip device (col. 3 lines 2-55), and wherein the third fabrication process is associated with a third technology node having a third minimum feature size that is different than the second minimum feature size (Fig. 4 and col. 4 lines 31-59); and
bonding the second chiplet 10-3 and the third chiplet 10-4 to an upper surface of the first chiplet 10-1 by way of inter-tier connectors 106 (Fig. 4).
Wang et al. do not disclose the first plurality of interconnects are between the first substrate and the second substrate and wherein the second plurality of interconnects are arranged along a surface of the second substrate facing away from the first substrate.
He teaches in Fig. 4 and the related text a first plurality of interconnects 424 are between the first substrate 412 and the second substrate 466 and wherein the second plurality of interconnects 434/438 are arranged along a surface of the second substrate 466 facing away from the first substrate 412.
Wand et al. and He are analogous art because they both are directed packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Wang et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Wang et al. to include the limitations as taught by He, in order to provide structure or characteristic in connection [0023].
As for claim 20, Wang et al. disclose the method of claim 19, wherein the first chiplet 10-1 laterally extends for non-zero distances past opposing outermost edges of the second chiplet in across-sectional view (fig. 4).
Claims 21 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. in view of He and further in view of Young et al. (US 2021/0242240).
As for claim 21, Wang et al. disclose the method of claim 19, except a contact etch stop layer is disposed on the first substrate and along opposing sides a gate structure of the first type of integrated chip device in a cross-sectional view, the contact etch stop layer having a first type of strain; and wherein a sidewall spacer is disposed on the second substrate and comprises discrete segments arranged along opposing sides of a gate structure of the second type of integrated chip device, sidewall spacer having a second type of strain that is different than the first type of strain.
Young et al. teach in Fig. 1 and the related text a contact etch stop layer (118 of LV1) is disposed on the first substrate 110 and along opposing sides a gate structure 114 of the first type of integrated chip device in a cross-sectional view (Fig. 1), the contact etch stop layer having a first type of strain [0049]; and wherein a sidewall spacer (118 of LV2) is disposed on the second substrate 150 and comprises discrete segments arranged along opposing sides of a gate structure of the second type of integrated chip device (fig. 1), sidewall spacer having a second type of strain that is different than the first type of strain [0049].
The combined device and Young et al. are analogous art because they both are directed stacked wafer/dies and one of ordinary skill in the art would have had a reasonable expectation of success to modify the combined device because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the combined device to include the limitations as taught by Young et al., in order to prevent leakage current.
Claims 22 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. in view of He and further in view of Semmelmeyer et al. (US 2013/0187292, as disclosed in previous office actions).
As for claim 22, Wang et al. disclose the method of claim 19, wherein processing a fourth substrate according to a fourth fabrication process to form a fourth chiplet 10-6 predominantly having a fourth plurality of devices (col. 3 lines 2-55) and a fourth plurality of interconnects 104 over the fourth substrate 102; and bonding the fourth chiplet to the upper surface of the first chiplet 10-1 by way of the plurality of inter-tier connectors 106 (Fig. 4), wherein the plurality of inter-tier connectors are arranged at a same height above the upper surface of the first chiplet and physically contact lower surfaces of the second chiplet and the third chiplet.
Wang et al. do not disclose the plurality of inter-tier connectors physically contact lower surface of the fourth chiplet.
Semmelmeyer et al. teach in fig. 7 and the related text a plurality of inter-tier connectors 24 physically contact lower surface of the fourth chiplet 96.
Wand et al., He and Semmelmeyer et al. are analogous art because they both are directed packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Wang et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Wang et al. and He to include the limitations as taught by Semmelmeyer et al., in order to reduce thickness of the packaging device.
Claims 23 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. in view of Semmelmeyer et al.
As for claim 23, Wang et al. disclose in Figs. 2-4 and the related text a method of forming an integrated chip, comprising:
forming a first integrated chip structure 10-1 predominantly comprising a first type of integrated chip device (col. 3 lines 2-55);
forming a second integrated chip structure 10-3 predominantly comprising a second type of integrated chip device that is different than the first type of integrated chip device (col. 3 lines 2-55);
forming a third integrated chip structure 10-4 predominantly comprising a third type of integrated chip device that is different than the first type of integrated chip device and the second type of integrated chip device (col. 3 lines 2-55), wherein the first integrated chip structure 10-1, the second integrated chip structure 10-3, and the third chip integrated structure 10-4 are formed using fabrication processes associated with different technology nodes (col. 4 lines 31-59);
forming a fourth integrated chip structure 10-6; and
bonding the second integrated chip structure 10-3, the third integrated chip structure 10-4, and the fourth integrated chip structure 10-6 to an upper surface of the first integrated chip structure 10-1 by way of a plurality of conductive bump structures 106 (Fig. 4) that continuously extend between the upper surface of the first integrated chip structure and lower surfaces of the second integrated chip structure, the third integrated chip structure, and the fourth integrated chip structure (Fig. 4).
Wang et al. do not disclose the fourth integrated chip structure predominately comprising one or more type passive devices.
Semmelmeyer et al. a (fourth) integrated chip structure 10 predominately comprising one or more type passive devices [0020].
Wand et al. and Semmelmeyer et al. are analogous art because they both are directed packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Wang et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Wang et al. and He to include the limitations as taught by Semmelmeyer et al., in order to improve electrical performance.
Claims 24 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. in view of Semmelmeyer et al and further in view of Martorell et al. (US 2021/0111113, as disclosed in previous office action).
As for claim 24, Wang et al. disclose the method of claim 23, except a first type of integrated chip device is a first type of transistor device having a first gate length; and wherein the second type of integrated chip device is a second type of transistor device having a second gate length is different than the first gate length.
Martorell et al. teach in Fig. 1-3 and the related text a first type of integrated chip device 170 is a first type of transistor device having a first gate with a first gate length; and wherein the second type of integrated chip device is a second type of transistor device 120A having a second gate with a second gate length is different than the first gate length [0043].
Martorell et al., Wang et al. and Semmelmeyer et al. are analogous art because they both are directed packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Wang et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the combined device to include the limitations as taught by Martorell et al., in order to achieve improve performance of the device.
Claims 25 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. in view of Semmelmeyer et al and further in view of Young et al.
As for claim 25, Wang et al. disclose the method of claim 24, wherein the one or more conductive bump structures 106 have rounded outer edges (Fig. 4).
Wang et al. do not disclose a first sidewall spacer having a first type of strain is formed along opposing sides of the first gate; and wherein a second sidewall spacer having a second type of strain is formed along opposing sides of the second gate, the first type of strain being different than the second type of strain.
Young et al. teach in Fig. 1 and the related text a first sidewall spacer (118 of LV1) having a first type of strain is formed along opposing sides of the first gate 114 [0049]; and wherein a second sidewall spacer (118 of LV2) having a second type of strain is formed along opposing sides of the second gate 114 [0049], the first type of strain being different than the second type of strain ([0049] of Young teach the first and second sidewall spacers comprises nitride or oxynitride, therefore the first type of strain being different than the second type of strain).
The combined device and Young et al. are analogous art because they both are directed stacked wafer/dies and one of ordinary skill in the art would have had a reasonable expectation of success to modify the combined device because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the combined device to include the limitations as taught by Young et al., in order to prevent leakage current.
Claims 26, 29 and 31 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. in view of Semmelmeyer et al and further in view of Celaya et al. (US 2011/0298115).
As for claim 26, 29 and 31, Wang et al. disclose the method of claim 23, wherein the third type of integrated chip device is (electrically) connected to a gate of a PMOS transistor (first type of integrated chip device) disposed on the second integrated chip structure and further connected to a gate of an NMOS transistor (second type of integrated chip device) disposed on the first integrated chip structure (col. 3 lines 2-55).
Wang et al. do not disclose the third type of integrated chip device is a gate driver circuit.
Celaya et al. teach in Fig. 5 and the related text a (third type of) integrated chip device 18 is a gate driver circuit [0002].
The combined device and Celaya et al. are analogous art because they both are directed stacked wafer/dies and one of ordinary skill in the art would have had a reasonable expectation of success to modify the combined device because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the combined device to include the limitations as taught by Celaya et al., in order to provide gate drive signal (Celaya et al. [0002]).
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. in view of Semmelmeyer et al and further in view of Kim et al. (US 2021/0035975).
As for claim 27, Wang et al. disclose the method of claim 23, except wherein the first type of integrated chip device is an NMOS transistor with a silicon carbide source/drain region; and wherein the second type of integrated chip device is a PMOS transistor with a silicon germanium source/drain region.
Kim et al. teach in Fig. 20 and the related text a first type of integrated chip device is an NMOS transistor with a silicon carbide source/drain region 390; and wherein the second type of integrated chip device is a PMOS transistor with a silicon germanium source/drain region 250 [0073].
The combined device and Kim et al. are analogous art because they both are directed stacked wafer/dies and one of ordinary skill in the art would have had a reasonable expectation of success to modify the combined device because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the combined device to include the limitations as taught by Kim et al. in order to enhance characteristics of the device.
As for claim 30, Wang et al. disclose the method of claim 23, wherein the upper surface of the first integrated chip structure 10-1 laterally extends past outermost edges of the second integrated chip structure 10-3, the third integrated chip structure 10-4.
Wang et al. do not the fourth type of integrated chip device is a gate driver circuit (col. 3 lines 2-55).
Celaya et al. teach in Fig. 5 and the related text a (fourth type of) integrated chip device 18 is a gate driver circuit [0002].
The combined device and Celaya et al. are analogous art because they both are directed stacked wafer/dies and one of ordinary skill in the art would have had a reasonable expectation of success to modify the combined device because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the combined device to include the limitations as taught by Celaya et al., in order to provide gate drive signal (Celaya et al. [0002]).
As for claim 32, Wang et al. disclose the method of claim 23, wherein the second integrated chip structure 10-3 is laterally separated from the third integrated chip structure 10-4 by a non-zero distance (Fig. 4).
Claims 33-38 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. in view of Semmelmeyer et al.
As for claims 33 and 38, Wang et al. disclose in Figs. 2-4 and the related text a method of forming an integrated chip, comprising:
forming a first chiplet 10-1 predominantly comprising NMOS transistor devices disposed on a first substrate (Fig. 2-4 and (col. 3 lines 2-55);
forming a second chiplet 10-3 predominantly comprising PMOS transistor devices disposed on a second substrate (Fig. 2-4, col. 3 lines 2-55);
forming a third chiplet 10-4 predominantly comprising devices disposed on a third substrate (col. 3 lines 2-55);
forming a fourth chiplet 10-6; and
bonding the first chiplet 10-1 to the second chiplet 10-3, the third chiplet 10-4 and the fourth chiplet 10-6 by way of a plurality of conductive bump structures 106 (electrically) contacting an upper surface of the first chiplet 10-1 and lower surfaces of the second chiplet 10-3, the third chiplet 10-4 and the fourth chiplet 10-6 (Fig. 4).
Wang et al. do not disclose the only devices on the third chiplet are predominantly comprising passive devices; the fourth chiplet comprsing gate driver circuits; and singulating the first semiconductor body to form the first chiplet.
Semmelmeyer et al. disclose in Figs. 1-10M and the related text forming a third chiplet 10 predominantly comprising passive devices [0020]; and singulating the first semiconductor body to form the first chiplet (Fig. 10L-10M [0061]).
Celaya et al. teach in Fig. 5 and the related text a (fourth type of) integrated chip device 18 is a gate driver circuit [0002].
Wang et al., Celaya et al. and Semmelmeyer et al. are analogous art because they both are directed packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Wang et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Wang et al. to include the limitations as taught by Semmelmeyer et al., in order to provide gate drive signal (Celaya et al. [0002]) and provide reliability.
As for claim 34, Wang et al. disclose the method of claim 33, further comprising: forming the first chiplet 10-1 using a first fabrication process associated with a first technology node having a first minimum feature size (col. 4 lines 31-59); and forming the second chiplet 10-3 using a second fabrication process associated with a second technology node having a second minimum feature size that is different than the first minimum feature size (col. 4 lines 31-59).
As for claim 35, Wang et al. disclose the method of claim 34, wherein the first chiplet 10-1 is larger than the second chiplet 10-3 and the third chiplet 10-4 (Fig. 4).
As for claim 36, Wang et al. disclose the method of claim 34, wherein a front-side of the first substrate and backsides of the second substrate and the third substrate face the plurality of conductive bump structures 106 (Fig. 4).
Claim 37 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. in view of Semmelmeyer et al. and further in view of He.
As for claim 37, Wang et al. disclose the method of claim 33, further comprising: forming a plurality of interconnects 104 along a front-side of the second substrate (102 of 10-3), the plurality of interconnects coupled to the PMOS transistor devices (Fig. 4, col. 3 lines 2-55); and forming a through substrate via (TSV) 119 extending through the second substrate (Fig. 4), wherein the TSV 119 is configured to be coupled between the plurality of interconnects (upper 106) and the plurality of conductive bump structures 106 (Fig. 4).
Wang et al. do not disclose the plurality of interconnects facing away from the first substrate.
He teaches in Fig. 4 and the related text a plurality of interconnects 434/438 are facing away from the first substrate 412.
Wand et al. and He are analogous art because they both are directed packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Wang et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Wang et al. to include the limitations as taught by He, in order to provide structure or characteristic in connection [0023].
Response to Arguments
Applicant’s arguments with respect to claim(s) above have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRANG Q TRAN whose telephone number is (571)270-3259. The examiner can normally be reached on Monday-Thursday (9am-4pm).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 5712721670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TRANG Q TRAN/Primary Examiner, Art Unit 2811
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