Prosecution Insights
Last updated: April 19, 2026
Application No. 17/572,935

STATIC RANDOM ACCESS MEMORY CELL POWER SUPPLY

Final Rejection §102
Filed
Jan 11, 2022
Examiner
BUI, THA-O H
Art Unit
2825
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company Ltd.
OA Round
6 (Final)
88%
Grant Probability
Favorable
7-8
OA Rounds
2y 4m
To Grant
92%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allow Rate
849 granted / 965 resolved
+20.0% vs TC avg
Minimal +4% lift
Without
With
+4.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
28 currently pending
Career history
993
Total Applications
across all art units

Statute-Specific Performance

§101
1.3%
-38.7% vs TC avg
§103
41.9%
+1.9% vs TC avg
§102
34.0%
-6.0% vs TC avg
§112
10.7%
-29.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 965 resolved cases

Office Action

§102
DETAILED ACTION Notice of AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment Acknowledgment is made of applicant’s Amendment, filed 20 May 2025. The changes and remarks disclosed therein have been considered. Claims 5, 11, 20 have been cancelled by Amendment. Therefore, claims 1-4, 6-10, 12-19, 21-23 are pending in the application. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claims 7-10, 12-14 are rejected under both 35 U.S.C. 102(a)(1) as being anticipated by Sinangil et al (US 9,208,900 B2 hereinafter “Sinangil”). Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. Regarding Independent Claim 7, Sinangil, for example in Figs. 1-9, discloses a system (see for example in Fig. 9) comprising: a word line driver circuit (e.g., 200; in Figs. 2A, 7A); a charge pump circuit (e.g., 400; in Figs. 4A, 4B) configured to: increase a voltage level of a voltage supply provide to a memory cell from a first voltage to a higher second voltage based on a first number of selected capacitors of the plurality of capacitors (e.g., BOOST CAM 500 included 400 is selected to C0, C1, C2 via switch element 412; in Figs. 4A, 4B, 5, 7A; also, the structure in of the prior art (Sinangil) is substantially identical to the structure of the claim. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II)), during a memory read operation of the memory cell (implied read operation; see for example in Figs. 4A, 4B, 5, 7A); and decrease, in response to preventing a data flip error in the memory cell during the memory read operation based on the higher second voltage, a voltage level of the higher second voltage to a third voltage provide to the memory cell based on a second number of selected capacitors of the plurality of capacitors (e.g., BOOST CAM 500 included 400 is selected to C0, C1, C2 via switch element 412; in Figs. 4A, 4B, 5, 7A; also, the structure in of the prior art (Sinangil) is substantially identical to the structure of the claim. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II)), wherein the third voltage is between the first voltage and the higher second voltage, wherein the second number is less than the first number, and wherein the plurality of capacitors are configured to share a first common node electrically connected to the voltage supply and to share a second common node when selected (via BOOST CAM 500 included 400 is selected to C0, C1, C2 via switch element 412; in Figs. 4A, 4B, 5, 7A; also, the structure in of the prior art (Sinangil) is substantially identical to the structure of the claim. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II)); and a memory array (e.g., memory array 100; in Fig. 1A) comprising a plurality of memory cells (e.g., 106; in Fig. 1A), wherein each of the memory cells (e.g., 106; in Fig. 1B) comprises: a plurality of pull-up devices (e.g., 132/136; in Fig. 1B); a plurality of pull-down devices (e.g., 130/134; in Fig. 1B); and a plurality of pass devices (e.g., 142/144; in Fig. 1B); wherein the wordline driver circuit is configured to provide the voltage supply to the plurality of pass devices (e.g., 200 via 730; in Fig. 7A), and wherein the charge pump circuit is electrically coupled to the plurality of pull-up devices (e.g., Boost Cam 500; in Figs. 4A, 4B, 5, 7A) and is configured to transition from the second voltage to the voltage supply after a transition from the voltage supply to ground applied to the plurality of pass devices by the wordline driver circuit (see for example in Figs. 4A, 4B, 5, 7A; also, the structure in of the prior art (Sinangil) is substantially identical to the structure of the claim. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II)). Regarding claim 8, Sinangil, for example in Figs. 1-9, discloses wherein the charge pump circuit comprises: a multiplexer circuit configured to output the higher second voltage based on the first number of capacitors electrically coupled to the voltage supply (e.g., the switches 412 as considered as multiplexer; in Figs. 4A, 4B, 5, 7A; also, the structure in of the prior art (Sinangil) is substantially identical to the structure of the claim. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II)). Regarding claim 9, Sinangil, for example in Figs. 1-9, discloses wherein the charge pump circuit is further configured to adjust the higher second voltage to the third voltage based on a de-selection of capacitors coupled to the voltage supply (in Figs. 4A, 4B, 5, 7A; also, the structure in of the prior art (Sinangil) is substantially identical to the structure of the claim. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II)). Regarding claim 10, Sinangil, for example in Figs. 1-9, discloses wherein the charge pump circuit is further configured to transition from the voltage supply to the higher second voltage or to the third voltage prior to a transition from ground to the voltage supply applied to gate terminals of the plurality of pass devices by the wordline driver circuit (see for example in Figs. 4A, 4B, 5, 7A; also, the structure in of the prior art (Sinangil) is substantially identical to the structure of the claim. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II)). Regarding claim 12, Sinangil, for example in Figs. 1-9, discloses wherein the plurality of pull-up devices comprise a plurality of p-type transistors, and wherein: each of the plurality of p-type transistors comprises a first source/drain (S/D) terminal, a second S/D terminal, and a gate terminal, and one of the first S/D terminal and the second S/D terminal is electrically coupled to the charge pump circuit (see for example in Figs. 4A, 4B, 5, 7A). Regarding claim 13, Sinangil, for example in Figs. 1-9, discloses wherein the plurality of pull-down devices comprise a plurality of n-type transistors (see for example in Figs. 4A, 4B, 5, 7A). Regarding claim 14, Sinangil, for example in Figs. 1-9, discloses wherein the plurality of pass devices comprise a plurality of n-type transistors, and wherein: each of the plurality of n-type transistors comprises a first source/drain (S/D) terminal, a second S/D terminal, and a gate terminal, and the gate terminal is electrically coupled to the voltage supply (see for example in Figs. 4A, 4B, 5, 7A). Allowable Subject Matter Claims 1-4, 6, 15-19, 21-23 are allowed. Applicant are reminded that when presenting amendments to claims. In order to be fully responsive, an attempt should be made to point out the patentable novelty (see MPEP 714.04). Additionally, Applicant should point out where and/or how the originally filed disclosure supports the amendment(s) (see MPEP 2163 (II)(A)). Response to Arguments Applicant's arguments filed 17 November 2025have been fully considered but are moot because a new ground(s) of rejection is made in view of Sinangil (US 9,208,900 B2). Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to THA-O H BUI whose telephone number is (571)270-7357. The examiner can normally be reached M-F 7:00AM - 3:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ALEXANDER SOFOCLEOUS can be reached at 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /THA-O H BUI/Primary Examiner, Art Unit 2825 12/15/2025
Read full office action

Prosecution Timeline

Jan 11, 2022
Application Filed
May 15, 2023
Non-Final Rejection — §102
Aug 11, 2023
Response Filed
Nov 14, 2023
Final Rejection — §102
Mar 08, 2024
Applicant Interview (Telephonic)
Mar 08, 2024
Examiner Interview Summary
Mar 13, 2024
Request for Continued Examination
Mar 26, 2024
Response after Non-Final Action
Jun 04, 2024
Non-Final Rejection — §102
Oct 11, 2024
Examiner Interview Summary
Oct 11, 2024
Applicant Interview (Telephonic)
Oct 30, 2024
Response Filed
Nov 15, 2024
Final Rejection — §102
May 20, 2025
Request for Continued Examination
May 21, 2025
Response after Non-Final Action
May 27, 2025
Non-Final Rejection — §102
Oct 24, 2025
Examiner Interview Summary
Oct 24, 2025
Applicant Interview (Telephonic)
Nov 17, 2025
Response Filed
Dec 15, 2025
Final Rejection — §102 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

7-8
Expected OA Rounds
88%
Grant Probability
92%
With Interview (+4.3%)
2y 4m
Median Time to Grant
High
PTA Risk
Based on 965 resolved cases by this examiner. Grant probability derived from career allow rate.

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