DETAILED ACTION
This office action is in response to amendment filed 6/2/2025.
Claims 1-17 and 21-23 are pending. Claims 18-20 have been canceled. Claims 1, 6 and 11 have been amended. Claims 2-4 and 8 have been withdrawn.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following claimed features must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Claim 1 reciting “an integrated circuit device … wherein the active conductive pattern comprises conductive portions which are correspondingly connected to a first plurality of electrical contacts provided on the first gate electrode, first source region, and first drain region” is not shown in any of the drawing. FIGs. 3-5 shows integrated circuit device but fails to show the “corresponding” connection between conductive portions and each of the first gate electrode, the first source region, and the first drain region. For example, the integrated circuit device as depicted in FIG. 3 shows active conductive pattern 323E including two conductive portions connected to electrical contacts provided on the gate electrode and one of the source/drain region, while the other one of the source/drain region is shown to be connected to the dummy conductive pattern 323T. Therefore, FIG. 3 does not show “the active conductive pattern comprises conductive portions which are correspondingly connected to a first plurality of electrical contacts provided on the first gate electrode, first source region, and first drain region” as recited in claim 1. FIGs. 4A-4E & FIGs. 5A-5F similarly fail to show every claimed feature.
Claim 5 reciting “a first thermal contact … is on the first gate electrode; a second thermal contact … is on the first source region; and a third thermal contact … is on the first drain region” in combination with the integrated circuit device of claim 1 is not shown in any of the drawing.
Claim 11 reciting “the integrated circuit … wherein the active conductive pattern comprises conductive portions which are correspondingly connected to a second plurality of electrical contacts for applying electrical signals to the second gate electrode, second source region, and second drain region” is not shown in any of the drawing for reasons similar to claim 1 above. More specifically, FIGs. 3-5 shows integrated circuit device but fails to show the “corresponding” connection between conductive portions and each of the second gate electrode, the second source region, and second drain region.
Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 5-7 and 9-13 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 reciting “an integrated circuit … wherein the active conductive pattern comprises conductive portions which are correspondingly connected to a first plurality of electrical contacts provided on the first gate electrode, first source region, and first drain region” lacks adequate support in the original disclosure. Applicant’s original disclosure describes an integrated circuit (e.g. shown in FIGs. 3-5) comprising active conductive portions (e.g. 323E in FIG. 3) connected to at most the gate electrode (e.g. 312 in FIG. 3) and only one of the source/drain region in an active area. However, the other one of the source/drain region is connected to dummy conductive pattern (e.g. 323T in FIG. 3) through thermal contacts (e.g. 318T in FIG. 3). There is no explicit support for each of the gate electrode, source region and drain region of the same active area to be correspondingly connected to the active conductive pattern as recited in the amended claim.
Claim 11 reciting “the integrated circuit … wherein the active conductive pattern comprises conductive portions which are correspondingly connected to a second plurality of electrical contacts for applying electrical signals to the second gate electrode, second source region, and second drain region” lacks adequate support in the original disclosure for similar reasons to as explained above.
Other claims are rejected for depending on a rejected claim.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 6 reciting “a first conductive material … in the first plurality of electrical contacts has a first parasitic capacitance Ce” and “a second conductive material … in the first plurality of thermal contacts has a second parasitic capacitance Ct” render the claim indefinite. It is unclear how is capacitance of a “conductive material” defined. A “capacitance” as commonly understood in the art refers to the ability of an object to store charged between two conducting components. However, it is unclear can does the conductive material itself be considered to have a capacitance. Furthermore, Applicant’s specification characterizes the thermal contacts to be composed of various thermally conductive insulating materials (see ¶ [026]). As such, it is unclear how is the “second parasitic capacitance” of the thermal contacts being defined for the thermally conductive insulating material.
Other claims are rejected for depending on a rejected claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 5-7, 9, 12-16, and 21-23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Paul et al. US 2020/0027898 A1 (Paul).
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In re claim 1, Paul discloses (e.g. FIGs. 4-7) an integrated circuit device comprising:
a semiconductor substrate (including SOI and handle wafer);
a first active area 422,602 in a first surface of the semiconductor substrate;
a first gate electrode 608 (also gate of FET 402, ¶ 58,73);
a first source region (¶ 58,73) in the first active area on a first side of the first gate electrode 608;
a first drain region (¶ 58,73) in the first active area on a second side of the first gate electrode 608;
an active conductive pattern (including M1-M5 of interconnect structure), wherein the active conductive pattern comprises conductive portions M1,426 (s/d/g terminals, ¶ 58) which are correspondingly connected to a first plurality of electrical contacts 604a,606a (vias under M1, ¶ 60,73) provided on the first gate electrode, first source region, and first drain region; and
a dummy conductive pattern 404b,702 (of M1, ¶ 59,76) connected to a first plurality of thermal contacts 404a (or vias connecting 404a to 422a,b, ¶ 60) or 610 or 706 or 710 provided on the first active area 422,602.
In re claim 5, Paul discloses (e.g. FIGs. 7A-7B) further comprising:
a first thermal contact 706,710 of the first plurality of thermal contacts is on the first gate electrode 608 (706,710 are disposed on a different level from the gate 608, and are thus considered to be “on” the first gate electrode 608);
a second thermal contact 706,710 of the first plurality of thermal contacts is on the first source region (region of 602 including 604 in FIG. 7); and
a third thermal contact 706,710 of the first plurality of thermal contacts is on the first drain region (region of 602 including 606 in FIG. 7, ¶ 81).
In re claim 6, as best understood, Paul discloses (e.g. FIGs. 4-7) wherein:
“a first conductive material between the first active area 422,602 and the active conductive pattern (M1-M5) in the first plurality of electrical contacts 604a,606a (contacts of source, drain, gate under M1, ¶ 60,73) has a first parasitic capacitance” Ce (capacitance between s/d/g contacts 604a,606a); and
“a second conductive material between the first active area 422,602 and the active conductive pattern (M1-M5) in the first plurality of thermal contacts 404a,610,706,710 has a second parasitic capacitance” Ct (parasitic capacitance between thermal contacts 404a,610,706,710 across the gate), wherein an expression Ce>Ct is satisfied (the source and drain contacts are disposed closer to the gate than thermal contacts 404a,610,706,710; thus the parasitic capacitance between the source contact and drain contact located on opposing sides of the gate is greater than the parasitic capacitance between the thermal contacts located on opposing sides of the gate).
In re claim 7, Paul discloses (e.g. FIGs. 4A, 5 & 7) wherein: the dummy conductive pattern (M1-M5 connected to 404,702) comprises a plurality of interconnected conductive patterns separated by a plurality of insulating layers (heat conducted through M1-M5 to 502, ¶ 68), wherein the plurality of interconnected conductive patterns M1-M5 are interconnected through a plurality of vias (vias between M1-M5) providing a first plurality of thermal connections between the first plurality of thermal contacts and the dummy conductive pattern (¶ 67-70).
In re claim 9, Paul discloses (e.g. FIG. 4-7) further comprising: a shallow trench isolation (STI) region ring 424 surrounding a portion of the first active area 422 (or SiO2 surrounding 606 in FIG. 7); and an insulating layer (1st passivation layer) separating the first active area 422,602 from a portion of the semiconductor substrate (handle wafer) extending below the first active area.
In re claim 12, Paul disclose (e.g. FIGs. 4-7) further comprising:
a heat dissipating structure 406 provided on a second surface of the semiconductor substrate opposite the first surface; and
a through-semiconductor-via 440 (extending through the height of the active layer) providing a thermal connection between the dummy conductive pattern 404b,702 and the heat dissipating structure 406 (¶ 61).
In re claim 13, Paul discloses (e.g. FIGs. 4A & 7B) further comprising:
a molding composition (no specific “molding composition” has been claimed that would structurally distinguish over various insulating material and passivation layer surrounding the device 402,602) surrounding a portion of the integrated circuit device 402,602;
a heat dissipating structure 406 provided on a second surface of the semiconductor substrate opposite the first surface; and
a through-molding-via 440 providing a thermal connection between the dummy conductive pattern 404b,702 and the heat dissipating structure 406 (¶ 61).
In re claim 14, Paul discloses (e.g. FIG. 4-7) an integrated circuit device comprising:
a semiconductor substrate (SOI);
an active area 422,602 formed in the semiconductor substrate;
a gate electrode 608 (¶ 58,73);
a source region (¶ 58,73) in the active area on a first side of the gate electrode 608;
a drain region (¶ 58,73) in the active area on a second side of the gate electrode 608;
a plurality of thermal contacts 404a,610,706,710 provided on the active area;
a dummy conductive pattern 404b,702 having a thermal connection to the plurality of thermal contacts (¶ 58,80-81); and
a through-silicon-via (TSV) 440 having a thermal connection to the dummy conductive pattern 404b,702 (440 extending through the height of the silicon island 422,602 to connect opposing sides).
In re claim 15, Paul discloses (e.g. FIGs. 4-7) further comprising: a thermal conductive layer 406 provided on a back surface of the semiconductor substrate, wherein the thermal conductive layer 406 has a thermal connection to the through silicon via 440.
In re claim 16, Paul discloses (e.g. FIGs. 4-7) further comprising: a heat sink 406 (or external heat sink, not shown, ¶ 59, 84) provided on a back surface of the semiconductor substrate, wherein the heat sink has a thermal connection to the through silicon via 440.
In re claim 21, Paul discloses (e.g. FIGs. 4-7) an integrated circuit device comprising:
a semiconductor substrate (SOI);
an active area 422,602 formed in the semiconductor substrate;
a gate electrode 608 (¶ 58,73);
a plurality of source/drain (S/D) regions (¶ 58,73);
a plurality of thermal contacts 404a,610,706,710 provided on the active area;
a dummy conductive pattern 404b,702 having a thermal connection to the plurality of thermal contacts (¶ 58,80-81);
a through-silicon-via (TSV) 440 having a thermal connection to the dummy conductive pattern 404b,702 (440 extending through the height of the silicon island 422,602 to connect opposing sides).
a molding compound (no specific “molding composition” has been claimed that would structurally distinguish over various insulating material and passivation layer surrounding the device 402,602) surrounding the active area; and
a through molding via 440 (other ones of 440) thermally connected to the dummy conductive pattern 404b,702.
Vias 440 extend through both the SOI substrate and surrounding molding compound (insulating/passivation layer) and is thus considered both as a TSV and as a through molding via.
In re claim 22, Paul discloses (e.g. FIGs. 4C & 7B) the plurality of S/D regions are between the TSV (e.g. left 440) and the through molding via (e.g. right 440) in a direction parallel to a top surface of the substrate.
In re claim 23, Paul discloses (e.g. FIGs. 4-7) further comprising at least one thermal dissipation structure 406 on surface of the semiconductor substrate opposite the gate electrode 608, wherein each of the TSV 440 and the through molding via 440 is thermally connected to the at least one thermal dissipation structure 406 (¶ 62).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Paul as applied to claim 9 above, and further in view of Tsunemi et al. 2017/0084531 A1 (Tsunemi).
In re claim 11, although not shown, Paul discloses the integrated circuit may include CMOS or multiple FETs as needed to ,e.g. withstand higher voltages or handle greater current (¶ 94).
Tsunemi teaches an integrated circuit on SOI characterized by improved heat release, wherein the device may comprises a single FET as shown in FIG. 1 comprises plural FETs as shown in FIGs. 13, 14 or 16 (¶ 225).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide a second FETs adjacent Paul’s first FET in an integrated circuit as taught by Tsunemi for higher withstand voltages or handling higher current as taught by Paul.
As such, the additional FET structure having same structure as that shown in FIGs. 4-7 in another one of 422,602, further comprising:
a second active area (a surface region of another one of 422 or 602 next to the gate) in the semiconductor substrate that is in electrical contact with a region of the semiconductor substrate below the second active area (e.g. a bottom region of the 422,602 below the surface region);
a second gate electrode (another one of 608 or gate of another FET 402, ¶ 58) extending across the second active area;
a second source region (¶ 58,73) in the second active area on a first side of the second gate electrode 608; and
a second drain region (¶ 58,73) in the second active area on a second side of the second gate electrode 608;
wherein the active conductive pattern (including M1-M5 of interconnect structure) comprises conductive portions M1,426 (s/d/g terminals, ¶ 58) which are correspondingly connected to a second plurality of electrical contacts 604a,606a (vias under M1, ¶ 60,73) for applying electrical signals to the second gate electrode, second source region, and second drain region; and
wherein the dummy conductive pattern 404b,702 (of M1, ¶ 59,76) is connected to a second plurality of thermal contacts 404a (or vias connecting 404a to 422a,b, ¶ 60) or 610 or 706 or 710 for removing heat from the second active area (the other one of 422,602), wherein the second plurality of thermal contacts are electrically isolated from receiving the electrical signals (¶ 58).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Paul as applied to claim 16 above, and further in view of Micovic et al. US 9,496,197 B1 (Micovic).
In re claim 17, Paul discloses the claimed invention including mounting a heat sink (¶ 59, 84) on the back surface thermally connected to via 440. Paul does not explicitly disclose the heat sink includes a fin structure for increasing convective heat transfer from the heat sink to an ambient environment.
However, Micovic discloses (FIGs. 1A-1B) an integrated circuit device having heat sinks 34 and 44 mounted on two opposing sides that are thermally connected to thermal vias 32,40,42, wherein the heat sinks includes fin structures 36,46 for increasing convective heat transfer from the heat sink to an ambient environment (Column 7, lines 22-35).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate fin structure in the external heat stink mounted on Paul’s integrated circuit to improve heat transfer as taught by Micovic.
Claims 1, 5-7 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ohmi US 2009/0283901 A1 in view of Gu et al. US 2017/0084531 A1 (Gu).
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In re claim 1, Ohmi discloses (e.g. FIGs. 3-4) an integrated circuit device comprising:
a semiconductor substrate 301;
a first active area 302 in a first surface of the semiconductor substrate 301;
a first gate electrode 311;
a first source region 310 in the first active area on a first side of the first gate electrode 311;
a first drain region 309 in the first active area on a second side of the first gate electrode 311;
an active conductive pattern 318, wherein the active conductive pattern 318 comprise conductive portions (portions connected electrical conductors) which are correspondingly connected to a first plurality of electrical contacts 313,314 provided on the first source region 310, and first drain region 309; and
a dummy conductive pattern 318 (portion connected to thermal vias 320) connected to a first plurality of thermal contacts 320 provided on the first active area.
No specific “dummy conductive pattern” has been claimed that would structurally distinguish over metallic wirings 318 that are connected to thermal vias 320.
Ohmi discloses the integrated circuit is a CMOS comprising an nMOS gate 305 and a pMOS gate 311 (¶ 80) and wherein the first pMOS source region 310 and the first pMOS drain region 309 being correspondingly connected to the conductive portions of the active conductive pattern 318. Ohmi does not explicitly disclose the first pMOS gate electrode 311 is also connected to a conductive portion of the active conductive pattern 318.
However, Gu discloses a CMOS integrated circuit (see FIG. 3) comprising a pair of complementary MOSFETs wherein the source regions 354,364, the drain regions 356,366, and the gate electrodes 306,308 are provided with electrical contacts 382,385,388,391,394,397 that are each respectively and correspondingly connected to conductive portions 383,386,389,392,395,398 of active conductive pattern of the overlying metallization structure (¶ 84).
Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that integrated circuit of Ohmi can be modified to further include a conductive portion connected to an electrical contact provided on the first gate electrode 311 of the CMOS circuit for the purpose of providing electrical connection to the gate electrode of the CMOS device as taught by Gu. Furthermore, a person of ordinary skill in the art would have been able to carry out the modification. Finally, the modification achieves the predictable result of being able to provide the desired electrical connections to the CMOS circuit. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the metallization structure of Ohmi to further include conductive portions 386,395 and electrical contacts 385,394 of Gu over the gate electrodes according to known methods to yield the predictable result of providing electrical routing to the gate electrodes as taught by Gu.
In re claim 5, Ohmi discloses (e.g. FIG. 3) further comprising:
a first thermal contact 320 (above 311) of the first plurality of thermal contacts is on the first gate electrode 311;
a second thermal contact 320 (connected to 313 through 318) of the first plurality of thermal contacts is on the first source region 310; and
a third thermal contact 320 (connected to 314 through 318) of the first plurality of thermal contacts is on the first drain region 309.
In re claim 6, as best understood, Ohmi discloses (e.g. FIGs. 3-4) wherein:
“a first conductive material 313,314 between the first active area 302 and the active conductive pattern 318 in the first plurality of electrical contacts has a first parasitic capacitance Ce”; and
“a second conductive material 320 between the first active area 302 and the active conductive pattern 318 in the first plurality of thermal contacts has a second parasitic capacitance Ct”, wherein an expression Ce>Ct is satisfied. As best understood, this is met due to the electrical contacts being made of electrically conductive material while the thermal contacts are made of electrically insulating material as disclosed by Applicant.
In re claim 7, Ohmi discloses (e.g. FIG. 3) wherein: the dummy conductive pattern 318 comprises a plurality of interconnected conductive patterns 318 separated by a plurality of insulating layers (interlayer insulation film, ¶ 82), wherein the plurality of interconnected conductive patterns 318 are interconnected through a plurality of vias (320 on upper levels) providing a first plurality of thermal connections between the first plurality of thermal contacts (320 on lower levels) and the dummy conductive pattern 318.
In re claim 10, Ohmi discloses (e.g. FIGs. 3-4) wherein: the first plurality of thermal contacts 320 (SiCN, ¶ 90) comprise a material selected from the group consisting of aluminum nitride (AlN), aluminum oxide (Al2O3), silicon nitride (SiN), diamond (C), and mixtures and combinations thereof.
Response to Arguments
Applicant's arguments filed 6/2/2025 have been fully considered but they are not persuasive.
Drawing objections
Applicant argues specification amendments overcome the outstanding drawing objections (Remark, page 11). This is not persuasive. The drawing remain deficient for showing all of the claimed features recited in claims 1 and 5 as detailed above.
35 USC § 112(b) rejections
Applicant argues the claim amendments overcome the outstanding § 121(b) rejections (Remark, page 11). This is not persuasive. Claim 6 remains indefinite as to how is “parasitic capacitance” defined for “a first/second conductive material … in the first plurality of electrical/thermal contacts”.
Rejections over Paul US 2020/0027898)
Regarding claims rejected over Paul, Applicant argues the combination of different figures from FIGs. 4-7 as being improper for anticipatory rejection (Remarks, pages 12-13).
This is not persuasive. While Paul teaches three different embodiments in FIGs. 4-7, features that are common across the different embodiments would have same structures and configurations. Each of the embodiments (with many common features) separately anticipates the claimed invention under different interpretations without any modifications based on another embodiment. The applicable interpretations are as detailed in the claim rejections set forth above. For example, the embodiment shown in FIGs. 4A-4C alone anticipates claims 1, 14 and 21 without any additional features from FIGs. 5-7. Similarly, the embodiments shown in FIGs. 5-7 also separately anticipates claims 1, 14 and 21, where features that are common to FIGs. 4A-4C are considered to be bodily incorporated.
Applicant’s arguments do not clearly point out how each of the separate embodiments of Paul as applied above fail to teach the claimed invention.
Applicant's arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references.
Applicant’s other arguments have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached Monday-Friday: 9AM-5PM ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WILLIAM KRAIG can be reached on 5712728660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YU CHEN/Primary Examiner, Art Unit 2896
YU CHEN
Examiner
Art Unit 2896