DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 21, 2026 has been entered.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the wherein a distance between top surfaces of the plurality of dielectric layers and the substrate is greater than a distance between the top surfaces of the plurality of bit-line contacts and the substrate along a Z direction in claim 1 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
Regarding claim 1. Claim 1 recites the limitation “wherein a distance between top surfaces of the plurality of dielectric layers and the substrate is greater than a distance between the top surfaces of the plurality of bit-line contacts and the substrate along a Z direction” in the last paragraph of the claim language.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1,3-6,8-9 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 1. Claim 1 recites the limitation “wherein a distance between top surfaces of the plurality of dielectric layers and the substrate is greater than a distance between the top surfaces of the plurality of bit-line contacts and the substrate along a Z direction, and the Z direction is perpendicular to the X direction and the Y direction” in the last paragraph of the claim language.
Applicant does not have support in the originally filed specifications for the limitations recited above.
Furthermore, applicant does not disclose any references to any Z direction, nor does applicant disclose a Z direction.
Claims 3-6, 8 and 9 are rejected for dependence upon a 112(a) rejected instance claim.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1, 3-6, 8, 9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1. Claim 1 recites the limitation “wherein a distance between top surfaces of the plurality of dielectric layers and the substrate is greater than a distance between the top surfaces of the plurality of bit-line contacts and the substrate along a Z direction, and the Z direction is perpendicular to the X direction and the Y direction ” in the last paragraph of the claim language.
It is unclear to the examiner how the distance between top surfaces of the plurality of dielectric layers and the substrate is greater than a distance between the top surfaces of the plurality of bit-line contacts and the substrate along a Z direction when applicant does not disclose in the specifications nor drawings of any measurements in the Z direction nor does applicant disclose that the drawing are to scale.
It is unclear to the examiner as to what applicant is attempting to claim here.
Claims 3-6, 8 and 9 are rejected for dependence upon a 112(b) rejected instance claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3-6, 8, 9 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (U.S. 2021/0296237), and further in view of Nakahata et al (U.S. 2001/0019142) .
Regarding claim 1. Kim et al discloses a memory device (FIG. 23A; [0022]), comprising:
a substrate (FIG. 23A, item 301) having a plurality (FIG. 1A; [0007], i.e. a substrate to define a plurality of active regions) of active areas (FIG. 23A, item ACT; [0044], i.e. [0046], i.e. A first impurity region 312a may be disposed in a portion of each of the cell active portions ACT);
a plurality of bit-line structures (FIG. 1A and 23A, item BL; [0050], i.e. The bit lines BL may include a bit-line polysilicon pattern 330 and a bit-line metal-containing pattern 332, which are sequentially stacked), disposed on the substrate (FIG. 23A, item 301) in parallel along a X direction (FIG. 1A, item D3; FIG. 23A, item A-A’);
a plurality of bit-line contacts (FIG. 1A and 23A, item DC), respectively disposed at overlaps ([0052], i.e. Bit-line contacts DC may be disposed in the first recess region R1 crossing the bit lines BL) of the plurality of bit-line structures (FIG. 1A and 23A, item BL) and the plurality of active areas (FIG. 23A, item ACT), and electrically connecting ([0052], i.e. The bit-line contact DC may electrically connect the first impurity region 312a to the bit line BL) the plurality of bit-line structures (FIG. 1A and 23A, item BL) and the plurality of active areas (FIG. 23A, item ACT); and
a plurality of protective structures (FIG. 1A and 23A, item 22), disposed at least on a first sidewall (FIG. 1A and 23A, left side item DC, item R1) and a second sidewall (FIG. 1A and 23A, right side item DC, item R1; [0053], i.e. the protection spacer 22 may have an ‘L’-shaped section. An upper portion (e.g., provided with the first impurity region 312a) of the substrate 301, which is provided near the bottom of the first recess region R1 and is in contact with the bit-line contact DC) of the plurality of bit-line contacts (FIG. 1A and 23A, item DC) wherein top surfaces (FIG. 1A and 23A, top surfaces of item 22) of the plurality of protective structures (FIG. 1A and 23A, item 22) and top surfaces (FIG. 1A and 23A, top surfaces of item DC) of the plurality of bit-line contacts (FIG. 1A and 23A, item DC) are flush (FIG. 23A shows top surfaces of items DC and top surfaces of items 22 are flushed) wherein the plurality of bit-line contacts (FIG. 23A, item DC; [0052], i.e. The bit-line contacts DC may be formed as portions of the bit-line polysilicon pattern 330) comprise doped polysilicon ([0050], i.e. The bit-line polysilicon pattern 330 may be formed of or include doped polysilicon); and
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a plurality of buried word lines (FIG. 23A, item WL) disposed in the substrate (FIG. 23A, item 301) in parallel along a Y direction ([0045], i.e. The word lines WL may be parallel to each other and extend in a second direction D2; FIG. 23A, item B-B’), wherein each bit- line contact (FIG. 23A, item DC) is disposed between two adjacent buried word lines (FIG. 23A, item WL; [0047], i.e. A word-line capping pattern 310 may be disposed on each of the word lines WL),
wherein each protective structure (FIG. 1A, item 22) is disposed at exceeding half of a width (annotated FIG. 1A, shows item 22 exceeding half width of WL) of the two adjacent buried word lines (FIG. 1A, item WL); and
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a plurality of dielectric layers (FIG. 23A, items 341 and AG; [0052], i.e. The lower gap-fill insulating pattern 341 may be formed of or include silicon nitride or silicon oxynitride; [0058], i.e. he air gap region AG may be filled with a gaseous material (e.g., the air) or vacuum, whose dielectric constant is lower than that of silicon oxide) respectively disposed on a third sidewall (FIG. 23A, item third sidewall) and a fourth sidewall (FIG. 23A, item fourth sidewall) of the plurality (FIG. 23A, item DC; [0052], i.e. A lower gap-fill insulating pattern 341 may be disposed in a portion of the first recess region R1, in which the bit-line contact).
wherein a distance between top surfaces (FIG. 23A, items AG) of the plurality of dielectric layers (FIG. 23A, items 341 and AG; [0052], [0058]) and the substrate (FIG. 23A, item 301) is greater than a distance between (annotated FIG. 23A shows a distance between top surfaces of the plurality of dielectric layers and the substrate is greater than a distance between the top surfaces of the plurality of bit-line contacts and the substrate) the top surfaces (FIG. 23A, top surfaces of item DC) of the plurality of bit-line contacts (FIG. 23A, item DC) and the substrate (FIG. 23A, item 301) along a Z direction (FIG. 23A, Z direction), and the Z direction (FIG. 23A, Z direction) is perpendicular (FIG. 23A shows Z direction is perpendicular to A-A’ and B-B’) to the X direction (FIG. 23A, item A-A’) and the Y direction (FIG. 23A, item B-B’).
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Kim et al fails to explicitly disclose the bit line contacts comprises N-type doped polysilicon or silicon germanium.
However, Nakahata et al teaches the bit line contacts comprises silicon germanium ([0213], i.e. silicon-germanium in place of polysilicon films)
Since Kim et al and Nakahata et al teach polysilicon bit line contacts, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the memory device as disclosed to modify Kim et al with the teachings of the bit line contacts comprises silicon germanium as disclosed by Nakahata et al. The use of silicon-germanium in place of polysilicon films in Nakahata et al provides for similar effect (Nakahata et al, [0213]).
Regarding claim 3. Kim et al and Nakahata et al discloses all the limitations of the memory device according to claim 1 above.
Kim et al further discloses wherein each protective structure (FIG. 1A and 23A, item 22) extends from ([0022], [0052]-[0053]) the first sidewall (FIG. 1A and 23A, left side item DC, item R1) or the second sidewall (FIG. 1A and 23A, left side item DC, item R1) of a corresponding bit-line contact (FIG. 1A and 23A, item DC) into a corresponding buried word line (FIG. 23A, item 310; [0054] i.e. word line capping pattern).
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Regarding claim 4. Kim et al and Nakahata et al discloses all the limitations of the memory device according to claim 1 above.
Kim et al further discloses wherein each active area (FIG. 1A, item ACT) is across (FIG.1A shows wherein each active area is across two buried word lines and one bit-line structure) two buried word lines (FIG. 1A, item WL) and one bit-line structure (FIG. 1A, item BL).
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Regarding claim 5. Kim et al and Nakahata et al discloses all the limitations of the memory device according to claim 1 above.
Kim et al further discloses further comprising a plurality of capacitor contacts (FIG. 1A, item BC) respectively disposed on two terminals of a long side of the plurality of active areas (FIG. 1A, item ACT), and respectively disposed in a space surrounded by the plurality of buried wordlines (FIG. 1A, item WL) and the plurality of bit-line contacts (FIG. 1A, item DC).
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Regarding claim 6. Kim et al and Nakahata et al discloses all the limitations of the memory device according to claim 1 above.
Kim et al further discloses wherein a width (FIG. 1A, width of item 22)of the plurality of protective structures (FIG. 1A, item 22) in the Y direction (FIG. 1A, item D2) is less than or equal (FIG. 1A, shows a width of item 22 is less than or equal to a width of item DC) to a width (FIG. 1A, width of item DC) of the plurality of bit-line contacts (FIG. 1A, width of item DC) in the Y direction (FIG. 1A, item D2).
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Regarding claim 8. Kim et al and Nakahata et al discloses all the limitations of the memory device according to claim 1 above.
Kim et al further discloses wherein each protective structure (FIG. 23A, item 22) surrounds ([0053]) the first sidewall (FIG. 23A, item first sidewall), the second sidewall (FIG. 23A, item second sidewall), the third sidewall (FIG. 23A, item third sidewall), and the fourth sidewall (FIG. 23A, item fourth sidewall) of a corresponding bit-line contact (FIG. 23A, item DC) in a form of an enclosed path ([0053], i.e. he protection spacer 22 may have a hollow closed-curve shape (e.g., circular or elliptical shape), when viewed in a plan view).
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Regarding claim 9. Kim et al and Nakahata et al discloses all the limitations of the memory device according to claim 1 above.
Kim et al further discloses wherein the plurality of protective structures (FIG. 23A, item 22) comprise a dielectric material ([0022]), and the dielectric material comprises silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof ([0082], i.e. the protection spacer 22 may be formed of or include at least one of silicon oxide, silicon oxynitride, or silicon nitride).
Response to Arguments
Applicant's arguments filed January 21, 2026 have been fully considered but they are not persuasive.
Regarding 102 rejection with Kim et al (U.S. 2021/0296237).
On page 9 of Applicant’s remarks, applicant appears to be arguing that Kim et al FIG. 1B fails to disclose applicant’s amended claim 1.
Examiner respectfully points out that FIG. 23A of Kim et al was used and not FIG. 1B and that Kim et al and Nakahata et al discloses applicant’s amended claim 1.
On page 10 of Applicant’s remarks, applicant appears to be arguing that Kim et al FIG. 23B fails to disclose applicant’s amended claim 1.
Examiner respectfully points out that FIG. 23A of Kim et al was used and not FIG. 23B and that Kim et al and Nakahata et al discloses applicant’s amended claim 1.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Park et al (U.S. 10,734,390) discloses method of manufacturing memory device.
Yang et al (U.S. 2022/0223599) discloses semiconductor memory structure and method for forming the same.
Ke et al (U.S. 2021/0350834) discloses DYNAMIC RANDOM ACCESS MEMORY AND METHOD FOR MANUFACTURING THE SAME.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SCOTT E BAUMAN whose telephone number is (469)295-9045. The examiner can normally be reached M-F, 9-5 CST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S.E.B./ Examiner, Art Unit 2815 /JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815
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