DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
This office action is response amendment filed May 26, 2026. Claims 1-4,8,10-13 ,23-24 and 27-32 are pending. Claims 14, 21 and 22 are withdrawn. Claim 22 has been amended. Claims 5-7, 9, 15-20, 25, 26 have been cancelled.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 11 and 32 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al (U.S. 2021/0408117), and Yin et al (U.S. 2009/0057745).
Regarding claim 11. Wu et al discloses a memory device (FIG. 2N, item 200), comprising:
a first transistor (FIG. 2N, item 210) including a gate electrode (FIG. 2N, item 120A and 120B) formed over a surface (FIG. 2N, surface of item 100) a semiconductor substrate (FIG. 2N, item 100), a first drain electrode (FIG. 2N, item 122A), a second drain electrode (FIG. 2N, item 122B) and a source electrode (FIG. 2N, item 124) formed in one layer (FIG. 2N, item 122A, 122B and 124 are in the same layer), arranged in an X-axis direction (FIG. 2N, left/right) that is parallel (FIG. 2N, surface of item 100) to the surface (FIG. 2N, surface of item 100) of the semiconductor substrate (FIG. 2N, item 100), and disposed above the gate electrode (FIG. 2N, item 120A and 120B) in a Z-axis direction (FIG. 2N, up/down) that is transverse to the X-axis direction (FIG. 2N, left/right), wherein the source electrode (FIG. 2N, item 124) is disposed between the first drain electrode (FIG. 2N, item 122A) and the second drain electrode (FIG. 2N, item 122B), a channel feature (FIG. 2N, item 140) disposed between the gate electrode (FIG. 2N, item 120A and 120B) and said one layer (FIG. 2N, item 122A, 122B and 124 are in the same layer) where the first drain electrode (FIG. 2N, item 122A), the second drain electrode (FIG. 2N, item 122B) and the source electrode (FIG. 2N, item 124) are formed, and extending (FIG. 2N, item 140 extends from item 122A to item 122B) from the first drain electrode (FIG. 2N, item 122A) to the second drain electrode (FIG. 2N, item 122B), and a gate dielectric layer (FIG. 2N, item 104) disposed between the gate electrode (FIG. 2N, item 120A and 120B) and the channel feature (FIG. 2N, item 140); and a first capacitor (FIG. 2N, item 150) electrically connected to the source electrode (FIG. 2N, item 124) of the first transistor (FIG. 2N, item 210); wherein the channel feature (FIG. 2N, item 140) has a first channel portion (FIG. 2N, item 140C1) extending between and interconnecting the first drain electrode (FIG. 2N, item 122A) and the source electrode (FIG. 2N, item 124), and a second channel portion (FIG. 2N, item 140C2) extending between and interconnecting the second drain electrode (FIG. 2N, item 122B) and the source electrode (FIG. 2N, item 140C1), and the gate electrode (FIG. 2N, item 120A and 120B) overlaps both of the first channel portion (FIG. 2N, item 140C1) and the second channel portion (FIG. 2N, item 140C2) of the channel feature (FIG. 2N, item 140).
Wu et al fails to explicitly disclose a gate electrode formed in one piece, and a projection of the source electrode in the Z-axis direction is fully contained within the gate electrode.
However, Yin et al teaches a gate electrode (FIG. 2, item 110) formed in one piece ([0047], i.e. a direction in which the bottom gate electrodes 110 extend may be referred to as a word line direction),
and a projection (FIG. 2, item 140) of the source electrode (FIG. 2, item 140) in the Z-axis direction ([0057], i.e. The source electrode 140 and the drain electrode 145 may be extended across the bottom gate electrodes 110) contained within the gate electrode (FIG. 2, item 110).
Since Wu et al and Yin et al teach transistors, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the memory device as disclosed to modify Wu et al with the teachings of a gate electrode formed in one piece, and a projection of the source electrode in the Z-axis direction is fully contained within the gate electrode as disclosed by Yin et al. The use of a direction in which the bottom gate electrodes extend may be referred to as a word line direction and the source electrode and the drain electrode may be extended across the bottom gate electrodes in Kuo provides for a nonvolatile memory device having a higher programming and/or erasing efficiency (Yin et al, [0021]).
Regarding claim 32. Wu et al and Yin et al discloses all the limitations of the memory device according to claim 11 above.
Wu et al further discloses
wherein the first drain electrode (FIG. 2N, item 122A) has a first edge (FIG 2N, item first edge) and a second edge (FIG 2N, item second edge) that are opposite to each other in the X-axis direction (FIG. 2N, left/right), and the first edge (FIG 2N, item first edge) is closer to the source electrode (FIG. 2N, item 124) than the second edge; and wherein an edge (FIG 2N, item an edge) of the gate electrode (FIG. 2N, item 120A and 120B) is aligned (FIG 2N, shows an edge is aligned with the first edge) with the first edge (FIG 2N, item first edge) of the first drain electrode (FIG. 2N, item 122A) in the Z-axis direction (FIG. 2N, item up/down),
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Yin et al further disclose the gate electrode (FIG. 2, item 110) overlaps the second drain electrode (FIG. 2, item 145a on right) in the Z-axis direction ([0057], i.e. The source electrode 140 and the drain electrode 145 may be extended across the bottom gate electrodes 110).
Claims 11-13, and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Petti et al (U.S. 2023/0077181) with priority to U.S. Provisional Patent Application No. 63/240,715 filed Sep. 3, 2021, and Yin et al (U.S. 7,994,588).
Regarding claim 11. Petti et al discloses a memory device (FIG. 1), comprising:
a first transistor (FIG. 1, item 11-5, 11-4) including
a gate electrode (FIG. 1, item 28) formed in one piece over a surface (FIG. 1, item a semiconductor substrate (FIG. 1, item 12), a first drain electrode (FIG. 1, item 11-4, item BL), a second drain electrode (FIG. 1, item 11-5, item BL) and a source electrode (FIG. 1, item SL) formed in one layer (FIG. 1, item 11; [0037]-[0038]), arranged in an X-axis direction (FIG. 1, item Z), and disposed above the gate electrode (FIG. 1, item 28) in a Z-axis direction (FIG. 1, item X) that is transverse to the X-axis direction (FIG. 1, item Z), wherein the source electrode (FIG. 1, item SL) is disposed between the first drain electrode (FIG. 1, item 11-4, item BL) and the second drain electrode (FIG. 1, item 11-5, item BL),
a channel feature (FIG. 1, item 25) disposed between the gate electrode (FIG. 1, item 28) and said one layer (FIG. 1, item 11; [0037]-[0038]) where the first drain electrode (FIG. 1, item 11-4, item BL), the second drain electrode (FIG. 1, item 11-5, item BL) and the source electrode (FIG. 1, item SL) are formed, and extending ([0039]-[0040]) from the first drain electrode (FIG. 1, item 11-4, item BL) to the second drain electrode (FIG. 1, item 11-5, item BL), and
a gate dielectric layer (FIG. 1, item 26) disposed between ([0039]-[0040]) the gate electrode (FIG. 1, item 28) and the channel feature (FIG. 1, item 25); and
a first capacitor ([0062]) electrically ([0062]) connected to the source electrode (FIG. 1, item SL) of the first transistor (FIG. 1, item 11-4, 11-5); wherein the channel feature (FIG. 1, item 25) has a first channel portion (FIG. 1, item 11-4, item 25) extending between and interconnecting the first drain electrode (FIG. 1, item 11-4, item BL) and the source electrode (FIG. 1, item SL), and a second channel portion (FIG. 1, item 11-5, item 25) extending between and interconnecting the second drain electrode (FIG. 1, item 11-5, item BL) and the source electrode (FIG. 1, item SL), and the gate electrode (FIG. 1, item 28) overlaps both of the first channel portion (FIG. 1, item 11-4, item 25) and the second channel portion (FIG. 1, item 11-5, item 25) of the channel feature (FIG. 1, item 25).
Petti et al fails to explicitly disclose X-axis is parallel to the surface of the semiconductor wafer and a projection of the source electrode in the Z-axis direction is fully contained within the gate electrode
However, Yin et al teaches a first drain (FIG. 2, item 145a on left), second drain (FIG. 2, item 145a on right) and a source electrode (FIG. 2, item 140) in the X-axis ([0047], i.e. a direction in which the bottom gate electrodes 110 extend may be referred to as a word line direction) is parallel (FIG. 2 shows items 145a on left, 145a on right, and 140 are parallel to the surface of item 105) to the surface (FIG. 2, surface of item 105) of the semiconductor wafer (FIG. 2, item 105) and a projection (FIG. 1, item 140) of the source electrode (FIG. 2, item 140) in the Z-axis direction ([0057], i.e. The source electrode 140 and the drain electrode 145 may be extended across the bottom gate electrodes 110) contained within the gate electrode (FIG. 2, item 110).
Since Petti et al and Yin et al teach transistors, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the memory device as disclosed to modify Petti et al with the teachings of parallel to the surface of the semiconductor wafer and a projection of the source electrode in the Z-axis direction is fully contained within the gate electrode as disclosed by Yin et al. The use of the horizontally redundant thin film transistors (TFTS) are disclosed having a U-shaped split gate in Kuo provides for horizontally redundant has large W/L and Ion /Ioff ratios, and occupies a small area (Kuo, [ABSTRACT]).
Regarding claim 12. Petti et al and Yin et al discloses all the limitations of the memory device according to claim 11 above.
Petti et al further discloses further comprising: a second transistor (FIG. 1, item 11-6, 11-7) including a gate electrode (FIG. 1, item 28) formed on the semiconductor substrate (FIG. 1, item 12), a first drain electrode (FIG. 1, item 11-6, item BL), a second drain electrode (FIG. 1, item 11-7, item BL) and a source electrode (FIG. 1, item SL) formed in said one layer (FIG. 1, item 11; [0037]-[0038]), arranged in the X-axis direction (FIG. 1, item Z), and disposed above the gate electrode (FIG. 1, item 28), wherein the source electrode (FIG. 1, item SL) of the second transistor (FIG. 1, item 11-6, 11-7) is disposed between the first drain electrode (FIG. 1, item 11-6, item BL) of the second transistor (FIG. 1, item 11-6, 11-7) and the second drain electrode (FIG. 1, item 11-7, item BL) of the second transistor (FIG. 1, item 11-6, 11-7), a channel feature (FIG. 1, item 25) disposed between the gate electrode (FIG. 1, item 28) and said one layer (FIG. 1, item 11; [0037]-[0038]), and extending from the first drain electrode (FIG. 1, item 11-6, item BL) to the second drain electrode (FIG. 1, item 11-7, item BL), and a gate dielectric layer (FIG. 1, item 26) disposed between the gate electrode (FIG. 1, item 28) and the channel feature (FIG. 1, item 25); and
a second capacitor ([0062]) electrically connected ([0062]) to the source electrode (FIG. 1, item SL) of the second transistor(FIG. 1, item 11-6, 11-7); wherein, for the second transistor (FIG. 1, item 11-6, 11-7), the channel feature (FIG. 1, item 25) has a first channel portion (FIG. 1, item 11-6, item 25) extending between and interconnecting the first drain electrode (FIG. 1, item 11-6, item BL) and the source electrode (FIG. 1, item SL), and a second channel portion (FIG. 1, item 11-7, item 25) extending between and interconnecting the second drain electrode (FIG. 1, item 11-7, item BL) and the source electrode (FIG. 1, item SL), and the gate electrode (FIG. 1, item 28) overlaps both of the first channel portion (FIG. 1, item 11-6, item 25) and the second channel portion (FIG. 1, item 11-7, item 25) of the channel feature (FIG. 1, item 25); and
wherein the channel features (FIG. 1, item 25) of the first transistor (FIG. 1, item 11-4, 11-5) and the second transistor (FIG. 1, item 11-6, 11-7) are formed in one piece (FIG. 1, item 25).
Regarding claim 13. Petti et al and Yin at al discloses all the limitations of the memory device according to claim 12 above.
Petti et al further discloses wherein the second drain electrode (FIG. 1, item 11-5, item BL) of the first transistor (FIG. 1, item 11-4, 11-5) and the first drain electrode (FIG. 1, item 11-6, item BL) of the second transistor (FIG. 1, item 11-6, 11-7) are formed in one piece (FIG. 9(g), item 112; [0103]).
Regarding claim 27. Petti et al and Yin et al discloses all the limitations of the memory device according to claim 13 above.
petti et al further discloses wherein a projection of a combination of the second drain electrode (FIG. 1, item 11-4, item BL) of the first transistor (FIG. 1, item 11-4, 11-5) and the first drain electrode (FIG. 1, item 11-6, item BL) of the second transistor (FIG. 1, item 11-6, 11-7) along the Z-axis direction (FIG. 1, item X) extends from the gate electrode (FIG. 1, item 28) of the first transistor (FIG. 1, item 11-4, 11-5) to the gate electrode (FIG. 1, item 28) of the second transistor (FIG. 1, item 11-6, 11-7).
Allowable Subject Matter
Claims 1-4, 8, 10, 23, 24, 28-31 allowed.
Response to Arguments
Applicant's arguments filed May 29, 2026 have been fully considered but they are not persuasive.
Applicant’s arguments with respect to claim(s) 11-13, 27 and 32 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/S.E.B./ Examiner, Art Unit 2815 /JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815
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