Prosecution Insights
Last updated: October 01, 2026
Application No. 17/585,252

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF

Non-Final OA §103§112
Filed
Jan 26, 2022
Priority
Jul 08, 2021 — provisional 63/219,673
Examiner
CRAMER, HALEE PAIGE
Art Unit
2891
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
5 (Non-Final)
74%
Grant Probability
Favorable
5-6
OA Rounds
0m
Est. Remaining
81%
With Interview

Examiner Intelligence

Grants 74% — above average
74%
Career Allowance Rate
46 granted / 62 resolved
+6.2% vs TC avg
Moderate +6% lift
Without
With
+6.5%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
16 currently pending
Career history
79
Total Applications
across all art units

Statute-Specific Performance

§103
58.1%
+18.1% vs TC avg
§102
22.2%
-17.8% vs TC avg
§112
18.5%
-21.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 62 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/15/2026 has been entered. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-3 and 5-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites the limitation " the first metal is different from the second metal and is in contact with end portions of the topmost surface of the first silicide layer." This limitation in the claim is unclear as “the first metal” refers to the metal of “the first metal layer” as well as the metal of “the first silicide layer”. Therefore, the limitation could be referring to the first metal of the metal layer is in contact with end portions of the first silicide layer, or the first metal of a portion of the first silicide layer is in contact with end portions of the first silicide layer. For examination purposes, the Examiner will interpret the limitation as “the metal layer is in contact with end portions of the topmost surface of the first silicide layer” as interpreted from the Applicant’s Drawings and previous Claim set. Claims 2-3 and 5-11 are also rejected under 35 U.S.C. 112(b) as they depend from and include all of the limitations of Claim 1. The following is a quotation of 35 U.S.C. 112(d): (d) REFERENCE IN DEPENDENT FORMS. —Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers. The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph: Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers. Claim 5 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Claim 5 recites the limitation, “bottommost surface of the second silicide layer is narrower than the topmost surface of the first silicide layer.” This limitation can be found in Claim 1, from which Claim 5 depends. Therefore, Claim 5 is of improper dependent form for failing to further limit the subject matter of the claim. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-3, 5-10, and 12-18 are rejected under 35 U.S.C. 103 as being unpatentable over Tsui et al. (US 20130020623 A1) hereinafter “Tsui” in view of Adusumilli et al. (US 20180226352 A1) hereinafter “Adusumilli” and Lin et al. (US 20160260633 A1) hereinafter “Lin”. Regarding Claim 1, Figure 6 of Tsui teaches: A semiconductor device (200), comprising: a device feature (232); a first silicide layer (246) having a first metal (Paragraph 0022; Titanium) wherein the first silicide layer is embedded in the device feature (Figure 6) and has a topmost surface (top vertically of 246); a dielectric layer (248) disposed over the device feature (238) and having a recess (250; Figure 5) extending through the dielectric layer; a metal plug (252) disposed within the recess, wherein the metal plug is configured to electrically couple (Paragraph 0030) the device feature to an interconnect structure (256; Figure 7) via the first silicide layer (246) Tsui does not teach: a second silicide layer having a second metal Figure 13 of Adusumilli teaches: a semiconductor device (900), a second silicide layer (1102) having a second metal (Paragraph 0062). It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a second silicide layer having a second metal because Adusumilli teaches contact resistance variability is reduced by the formation of textured silicides in the contact (Adusumilli Paragraph 0004). Tsui does not teach: wherein a bottommost surface of the second silicide layer is positioned above a topmost surface of the first silicide layer, and the bottommost surface of the second silicide layer is in direct contact with a topmost surface of the first silicide layer; wherein the first metal is different from the second metal. However, when the second silicide layer as described in Adusumilli is combined with the structure of Tsui, a structure will be yielded such that a bottommost surface of the second silicide layer is positioned above a topmost surface of the first silicide layer, and the bottommost surface of the second silicide layer is in direct contact with a topmost surface of the first silicide layer; wherein the first metal is different from the second metal. Tsui does not teach: the metal plug is configured to electrically couple the device feature to an interconnect structure via a combination of the first silicide layer and second silicide layer. The combination of the second silicide layer of Adusumilli with the structure of Tsui will yield a structure such that wherein the metal plug is configured to electrically couple the device feature to an interconnect structure via a combination of the first silicide layer and second silicide layer. Tsui does not teach: a metal layer comprising at least the first metal and extending along inner sidewalls of the recess Figure 13 of Adusumilli teaches: a metal layer of Titanium Nitride is deposited on the second silicide layer (1102) (Paragraph 0063; Not pictured) It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a metal layer comprising at least the first metal and extending along inner sidewalls of the recess because Adusumilli teaches a Titanium Nitride layer is deposited in the recess on the second silicide layer to act as a liner/barrier layer for the following metal fill layer (Adusumilli Paragraph 0063). Tsui does not teach: the metal layer is in contact with end portions of the topmost surface of the first silicide layer (See 35 U.S.C. 112(b) rejection of Claim 1 above.) and the bottommost surface of the second silicide layer is narrower than the topmost surface of the first silicide layer Figure 1 of Lin teaches: a method of forming a contact plug (120) comprising forming a first silicide layer (104) by annealing a metal layer (106) such that the metal layer remains on sidewalls of the contact plug and the metal layer is in contact with end portions of the topmost surface of the first silicide layer (Figure 1) It would be obvious to one of ordinary skill in the art to have the metal layer is in contact with end portions of the topmost surface of the first silicide layer because Lin teaches a method of forming self-aligned silicide regions that increase the conductivity of affected areas of substrate thus forming a more suitable contact (Lin Paragraph 0027). Further, the combination of the structure of Tsui with the second silicide layer and metal layer of Adusumilli and utilizing the method of forming the first silicide layer of Lin, a structure will be yielded such that the bottommost surface of the second silicide layer is narrower than the topmost surface of the first silicide layer. Regarding Claim 2, the combination of Tsui, Adusumilli, and Lin teaches all of the limitations of the claimed invention. Figure 6 of Tsui teaches: the first metal includes titanium (Paragraph 0022; 246 contains titanium) and that silicide features (246) can include nickel (Paragraph 0022) Tsui does not teach: second metal includes nickel. Therefore, the combination of the second silicide layer of Adusumilli, with the materials of Tsui will yield a structure such that the second metal includes nickel. Regarding Claim 3, Figure 6 of Tsui teaches: the device feature (232) has a first upper surface (top surface vertically of 232) and wherein the first upper surface and the topmost surface (top surface vertically of 246) of the first silicide layer (246) share a common surface (Figure 6). Regarding Claim 5, the combination of Tsui, Adusumilli, and Lin teaches all of the limitations of the claimed invention. Tsui does not teach: the bottommost surface of the second silicide layer is narrower than the topmost surface of the first silicide layer. However, the combination of the structure of Tsui with the second silicide layer and metal layer of Adusumilli and utilizing the method of forming the first silicide layer of Lin, a structure will be yielded such that the bottommost surface of the second silicide layer is narrower than the topmost surface of the first silicide layer. Regarding Claim 6, the combination of Tsui, Adusumilli, and Lin teaches all of the limitations of the claimed invention. Tsui does not teach: the second silicide layer further comprises a second portion extending along the inner sidewalls of the recess. Figure 13 of Adusumilli teaches: the second silicide layer (1102) further comprises a second portion (upper vertical portions of 1102) extending along the inner sidewalls of the recess (Paragraph 0060; where recesses are formed exposing the source-drain contact regions) It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the second silicide layer further comprises a second portion extending along the inner sidewalls of the recess because Adusumilli teaches a structure with a silicide formed along the inner sidewalls of the recess reduces variability in contact resistance (Adusumilli Paragraph 0004). Regarding Claim 7, the combination of Tsui, Adusumilli, and Lin teaches all of the limitations of the claimed invention. Tsui does not teach: a nitride layer having the first metal and disposed between the metal plug and the recess. Figure 13 of Adusumilli teaches: a metal layer of Titanium Nitride is deposited on the second silicide layer (1102) (Paragraph 0063; Not pictured) between the metal plug (1202) and the recess (Paragraph 0060). It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a nitride layer having the first metal and disposed between the metal plug and the recess because Adusumilli teaches a Titanium Nitride layer is deposited in the recess on the second silicide layer to act as a liner/barrier layer for the following metal fill layer (Adusumilli Paragraph 0063). Regarding Claim 8, the combination of Tsui, Adusumilli, and Lin teaches all of the limitations of the claimed invention. Tsui does not teach: the nitride layer is in contact with at least a portion of an upper surface of the second silicide layer. Figure 13 of Adusumilli teaches: a metal layer of Titanium Nitride is deposited on the second silicide layer (1102) (Paragraph 0063; Not pictured) It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the nitride layer is in contact with at least a portion of an upper surface of the second silicide layer because Adusumilli teaches a Titanium Nitride layer is deposited in the recess on the second silicide layer to act as a liner/barrier layer for the following metal fill layer (Adusumilli Paragraph 0063). Regarding Claim 9, Figure 6 of Tsui teaches: the device feature (232) includes a silicon-based structure (Paragraph 0018 where 238 is formed in silicon substrate 210) or region that serves as a drain/source terminal (238) of a transistor. Regarding Claim 10, the device feature (232) includes a poly-silicon structure (Paragraph 0013) that serves as a gate terminal (228) of a transistor. Regarding Claim 12, Figure 6 of Tsui teaches: A semiconductor device (200), comprising: a transistor (232) comprising at least one terminal (238) that contains silicon (Paragraph 0018; Where 238 is formed in silicon substrate 210); a metal plug (252) electrically coupled to the at least one terminal (Paragraph 0029); a first silicide layer (246) disposed between the metal plug and the at least one terminal, and having a first metal (Paragraph 0022; Titanium) and a topmost surface (top vertically of 246). Tsui does not teach: a second silicide layer disposed between the metal plug and the at least one terminal, and having a second metal, Figure 13 of Adusumilli teaches: a semiconductor device (900), comprising a terminal (905), a metal plug (1202), and a second silicide layer (1102) disposed between the metal plug and the at least one terminal and having a second metal (Paragraph 0062) It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a second silicide layer comprising a first portion disposed between the metal plug and the at least one terminal, and having a second metal because Adusumilli teaches contact resistance variability is reduced by the formation of textured silicides in the contact (Adusumilli Paragraph 0004). Tsui does not teach: wherein a bottommost surface of the second silicide layer is positioned above and in direct contact with a topmost surface of the first silicide layer; wherein the first metal is different from the second metal. However, when the second silicide layer as described in Adusumilli is combined with the structure of Tsui, a structure will be yielded such that a bottommost surface of the second silicide layer is positioned above and in direct contact with a topmost surface of the first silicide layer, and wherein the first metal is different from the second metal. Tsui does not teach: the bottommost surface of the second silicide layer is narrower than the topmost surface of the first silicide layer Figure 1 of Lin teaches: a method of forming a contact plug (120) comprising forming a first silicide layer (104) by annealing a metal layer (106) such that the metal layer remains on sidewalls of the contact plug It would be obvious to one of ordinary skill in the art to utilize this method of forming a first silicide layer because Lin teaches a method of forming self-aligned silicide regions that increase the conductivity of affected areas of substrate thus forming a more suitable contact (Lin Paragraph 0027). Further, the combination of the structure of Tsui, utilizing the method of Lin, with the second silicide layer of Adusumilli a structure will be yielded such that the bottommost surface of the second silicide layer is narrower than the topmost surface of the first silicide layer. Regarding Claim 13, the combination of Tsui, Adusumilli, and Lin teaches all of the limitations of the claimed invention. Figure 6 of Tsui teaches: the first silicide layer includes titanium silicide (Paragraph 0022) and that silicide features (246) can include nickel silicide (Paragraph 0022) Tsui does not teach: the second silicide layer includes nickel silicide (NiSi) Therefore, the combination of the second silicide of Adusumilli with the materials of Tsui will yield a structure such that the second silicide layer includes nickel silicide (NiSi). Regarding Claim 14, Figure 6 of Tsui teaches: the first silicide layer (246) is embedded within the terminal (238), with an upper surface exposed from an upper surface of the terminal (Figure 6). Regarding Claim 15, the combination of Tsui, Adusumilli, and Lin teaches all of the limitations of the claimed invention. Tsui does not teach: the second silicide layer, in direct contact with the first silicide layer, further comprises a second portion extending along sidewalls of the metal plug. Figure 13 of Adusumilli teaches: the second silicide layer (1102) is in direct contact with the first silicide layer (1002) and comprises a portion extending along sidewalls of the metal plug (1202). It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the second silicide layer, in direct contact with the first silicide layer, further comprises a second portion extending along sidewalls of the metal plug because Adusumilli teaches a structure with a silicide formed along sidewalls of a metal plug reduces variability in contact resistance (Adusumilli Paragraph 0004). Regarding Claim 16, the combination of Tsui, Adusumilli, and Lin teaches all of the limitations of the claimed invention. Tsui does not teach: the second silicide layer, in direct contact with the first silicide layer, has sidewalls inwardly recessed from sidewalls of the first silicide layer, respectively. However, the combination of the second silicide layer of Adusumilli with the structure of Tsui, will yield a structure such that the second silicide layer, in direct contact with the first silicide layer, has sidewalls inwardly recessed from sidewalls of the first silicide layer, respectively. Regarding Claim 17, Figures 2-6 of Tsui teaches: A method for fabricating semiconductor devices (200), comprising: forming a recess (250) extending through a dielectric layer (248) to expose a portion of a silicon-based device feature (238); forming a first silicide layer (246) at a position of the exposed portion of the silicon-based device feature, wherein the first silicide layer contains a first metal (Paragraph 0022; Titanium) and has a topmost surface (top vertically of 246); and forming a metal plug (252) within the recess. Tsui does not teach: forming a second silicide layer over the first silicide layer, wherein the second silicide layer contains a second metal Figure 13 of Adusumilli teaches: a semiconductor device (900), comprising a second silicide layer (1102) having a second metal (Paragraph 0062) It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a second silicide layer over the first silicide layer because Adusumilli teaches contact resistance variability is reduced by the formation of textured silicides in the contact (Adusumilli Paragraph 0004). Tsui does not teach: a bottommost surface of the second silicide layer is positioned above and in direct contact with a topmost surface of the first silicide layer; wherein the first metal is different from the second metal However, when the second silicide layer as described in Adusumilli is combined with the structure of Tsui, a structure will be yielded such that a bottommost surface of the second silicide layer is positioned above and in direct contact with a topmost surface of the first silicide layer and wherein the first metal is different from the second metal. Tsui does not teach: the bottommost surface of the second silicide layer is narrower than the topmost surface of the first silicide layer Figure 1 of Lin teaches: a method of forming a contact plug (120) comprising forming a first silicide layer (104) by annealing a metal layer (106) such that the metal layer remains on sidewalls of the contact plug It would be obvious to one of ordinary skill in the art to utilize this method of forming a first silicide layer because Lin teaches a method of forming self-aligned silicide regions that increase the conductivity of affected areas of substrate thus forming a more suitable contact (Lin Paragraph 0027). Further, the combination of the structure of Tsui, utilizing the method of Lin, with the second silicide layer of Adusumilli a structure will be yielded such that the bottommost surface of the second silicide layer is narrower than the topmost surface of the first silicide layer. Regarding Claim 18, the combination of Tsui, Adusumilli, and Lin teaches all of the limitations of the claimed invention. Figure 6 of Tsui teaches: the first silicide layer includes titanium silicide (Paragraph 0022) and that silicide features (246) can include nickel silicide (Paragraph 0022) Tsui does not teach: the second silicide layer includes nickel silicide (NiSi) Therefore, the combination of the second silicide of Adusumilli with the materials of Tsui will yield a structure such that the second silicide layer includes nickel silicide (NiSi). Claim 11 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Tsui et al. (US 20130020623 A1) hereinafter “Tsui” in view of Adusumilli et al. (US 20180226352 A1) hereinafter “Adusumilli”, Lin et al. (US 20160260633 A1) hereinafter “Lin,” as evidenced by Nishmoto et al. (US 20100226004 A1) hereinafter “Nishmoto” and Ramasubramanian et al. (US 20120115026 A1) hereinafter “Ramasubramanian”. Regarding Claim 11, the combination of Tsui, Adusumilli, and Lin teaches all of the limitations of the claimed invention. Figure 6 of Tsui teaches: the first silicide layer (246) has a first resistivity (Paragraph 0022; resistivity of titanium silicide) Tsui does not teach: the second silicide layer has a second resistivity, and wherein the second resistivity is less than the first resistivity. However, the combination of the second silicide layer of Adusumilli with the silicide materials of Tsui, will yield a structure such that the second silicide layer has a second resistivity, and wherein the second resistivity is less than the first resistivity. Further, evidentiary reference Nishmoto teaches the resistivity of titanium silicide (TiSi2) is as low as 15 to 20 µΩ∙cm (Nishmoto Paragraph 0084), and evidentiary reference Ramasubramanian teaches the resistivity of nickel silicide (NiSi) is 10 to 60 µΩ∙cm (Ramasubramanian Paragraph 0031). Regarding Claim 21, the combination of Tsui, Adusumilli, and Lin teaches all of the limitations of the claimed invention. Figure 6 of Tsui teaches: the first silicide layer (246) has a first resistivity (Paragraph 0022; resistivity of titanium silicide) Tsui does not teach: the second silicide layer has a second resistivity, and wherein the second resistivity is less than the first resistivity. However, the combination of the second silicide layer of Adusumilli with the silicide materials of Tsui, will yield a structure such that the second silicide layer has a second resistivity, and wherein the second resistivity is less than the first resistivity. Further, evidentiary reference Nishmoto teaches the resistivity of titanium silicide (TiSi2) is as low as 15 to 20 µΩ∙cm (Nishmoto Paragraph 0084), and evidentiary reference Ramasubramanian teaches the resistivity of nickel silicide (NiSi) is 10 to 60 µΩ∙cm (Ramasubramanian Paragraph 0031). Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Tsui et al. (US 20130020623 A1) hereinafter “Tsui” in view of Adusumilli et al. (US 20180226352 A1) hereinafter “Adusumilli,” Lin et al. (US 20160260633 A1) hereinafter “Lin,” and Wang et al. (US 20150364560 A1) hereinafter “Wang”. Regarding Claim 19, the combination of Tsui, Adusumilli, and Lin teaches all of the limitations of the claimed invention. Tsui does not teach: the step of forming a second silicide layer over the first silicide layer further comprises: depositing a silicon layer lining the recess; depositing a metal layer, containing the second metal, that lines the recess; and annealing the silicon layer and the metal layer to form the second silicide layer. Figure 6 of Wang teaches: a silicide (604) is formed over a sidewall (504), by depositing an amorphous silicon layer (not shown), depositing a metal layer (not shown) over the amorphous silicon layer, then annealing (Paragraph 0021) It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a silicon layer be deposited to line the recess, as the deposition of a silicon layer followed by a metal layer and an annealing process, is known to create silicide layers (Wang Paragraph 0021). Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Tsui et al. (US 20130020623 A1) hereinafter “Tsui” in view of Adusumilli et al. (US 20180226352 A1) hereinafter “Adusumilli,” Lin et al. (US 20160260633 A1) hereinafter “Lin,” Wang et al. (US 20150364560 A1) hereinafter “Wang” and Or et al. (US 20060051966 A1) hereinafter “Or.” Regarding Claim 20, the combination of Tsui, Adusumilli, and Lin teaches all of the limitations of the claimed invention. Tsui does not teach: the step of forming a second silicide layer over the first silicide layer further comprises: depositing a silicon layer lining the recess; respectively; depositing a metal layer, containing the second metal, that lines the recess; and annealing the silicon layer and the metal layer to form the second silicide layer. Figure 6 of Wang teaches: a silicide (604) is formed over a sidewall (504), by depositing an amorphous silicon layer (not shown), depositing a metal layer (not shown) over the amorphous silicon layer, then annealing (Paragraph 0021) It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a silicon layer be deposited to line the recess, as the deposition of a silicon layer followed by a metal layer and an annealing process, is known to create silicide layers (Wang Paragraph 0021). Tsui does not teach: etching portions of the silicon layer that extend along inner sidewalls of the recess, Figures 5E-5G of Or teach: an etch is performed on silicon layer (585) to expose silicon layers beneath (Paragraph 0111) It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to etch portions of the silicon layer that extend along inner sidewalls of the recess because conventional furnace annealing is performed on the metal and silicon layers to form metal silicide in regions in which the metal layer is in contact with silicon, therefore creating silicide regions where desired (Or Paragraph 0112). Response to Arguments Applicant’s arguments, see Applicant’s Remarks, filed 04/15/2026, with respect to the rejections of Claims 1, 12, and 17 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Tsui, Adusumilli, and Lin. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Halee Cramer whose telephone number is (571)270-1641. The examiner can normally be reached Monday - Friday 7:30am - 4:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HALEE CRAMER/Examiner, Art Unit 2891 /MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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Prosecution Timeline

Show 7 earlier events
Aug 15, 2025
Response after Non-Final Action
Aug 26, 2025
Non-Final Rejection mailed — §103, §112
Nov 25, 2025
Response Filed
Jan 16, 2026
Final Rejection mailed — §103, §112
Apr 15, 2026
Response after Non-Final Action
May 07, 2026
Request for Continued Examination
May 11, 2026
Response after Non-Final Action
Jul 24, 2026
Non-Final Rejection mailed — §103, §112 (current)

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Prosecution Projections

5-6
Expected OA Rounds
74%
Grant Probability
81%
With Interview (+6.5%)
3y 3m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 62 resolved cases by this examiner. Grant probability derived from career allowance rate.

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