DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Applicant’s amendments to the Claims, submitted 11/25/2025, have been entered. Claims 1-20 remain pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-10, and 12-18 are rejected under 35 U.S.C. 103 as being unpatentable over Tsui et al. (US 20130020623 A1) hereinafter “Tsui” in view of Adusumilli et al. (US 20180226352 A1) hereinafter “Adusumilli”.
Regarding Claim 1, Figure 6 of Tsui teaches: A semiconductor device (200), comprising: a device feature (232); a first silicide layer (246) having a first metal (Paragraph 0022; Titanium) wherein the first silicide layer is embedded in the device feature (Figure 6) and has a topmost surface (top vertically of 246).
Tsui does not teach: a second silicide layer having a second metal
Figure 13 of Adusumilli teaches: a semiconductor device (900), a second silicide layer (1102) having a second metal (Paragraph 0062).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a second silicide layer having a second metal because Adusumilli teaches contact resistance variability is reduced by the formation of textured silicides in the contact (Adusumilli Paragraph 0004).
Tsui does not teach: wherein a bottommost surface of the second silicide layer is positioned above a topmost surface of the first silicide layer, and the bottommost surface of the second silicide layer is in direct contact with a topmost surface of the first silicide layer; wherein the first metal is different from the second metal.
However, when the second silicide layer as described in Adusumilli is combined with the structure of Tsui, a structure will be yielded such that a bottommost surface of the second silicide layer is positioned above a topmost surface of the first silicide layer, and the bottommost surface of the second silicide layer is in direct contact with a topmost surface of the first silicide layer; wherein the first metal is different from the second metal.
Regarding Claim 2, the combination of Tsui and Adusumilli teaches all of the limitations of the claimed invention.
Figure 6 of Tsui teaches: the first metal includes titanium (Paragraph 0022; 246 contains titanium) and that silicide features (246) can include nickel (Paragraph 0022)
Tsui does not teach: second metal includes nickel.
Therefore, the combination of the second silicide layer of Adusumilli, with the materials of Tsui will yield a structure such that the second metal includes nickel.
Regarding Claim 3, Figure 6 of Tsui teaches: the device feature (232) has a first upper surface (top surface vertically of 232) and wherein the first upper surface and the topmost surface (top surface vertically of 246) of the first silicide layer (246) share a common surface (Figure 6).
Regarding Claim 4, the combination of Tsui and Adusumilli teaches all of the limitations of the claimed invention.
Figure 6 of Tsui teaches: a dielectric layer (248) disposed over the device feature (238) and having a recess (250; Figure 5) extending through the dielectric layer; a metal plug (252) disposed within the recess, wherein the metal plug is configured to electrically couple (Paragraph 0030) the device feature to an interconnect structure (256; Figure 7) via the first silicide layer (246)
Tsui does not teach: the metal plug is configured to electrically couple the device feature to an interconnect structure via a combination of the first silicide layer and second silicide layer.
The combination of the second silicide layer of Adusumilli with the structure of Tsui will yield a structure such that wherein the metal plug is configured to electrically couple the device feature to an interconnect structure via a combination of the first silicide layer and second silicide layer.
Tsui does not teach: a metal layer comprising at least the first metal and extending along inner sidewalls of the recess
Figure 13 of Adusumilli teaches: a metal layer of Titanium Nitride is deposited on the second silicide layer (1102) (Paragraph 0063; Not pictured)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a metal layer comprising at least the first metal and extending along inner sidewalls of the recess because Adusumilli teaches a Titanium Nitride layer is deposited in the recess on the second silicide layer to act as a liner/barrier layer for the following metal fill layer (Adusumilli Paragraph 0063).
Regarding Claim 6, the combination of Tsui and Adusumilli teaches all of the limitations of the claimed invention.
Tsui does not teach: the second silicide layer further comprises a second portion extending along the inner sidewalls of the recess.
Figure 13 of Adusumilli teaches: the second silicide layer (1102) further comprises a second portion (upper vertical portions of 1102) extending along the inner sidewalls of the recess (Paragraph 0060; where recesses are formed exposing the source-drain contact regions)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the second silicide layer further comprises a second portion extending along the inner sidewalls of the recess because Adusumilli teaches a structure with a silicide formed along the inner sidewalls of the recess reduces variability in contact resistance (Adusumilli Paragraph 0004).
Regarding Claim 7, the combination of Tsui and Adusumilli teaches all of the limitations of the claimed invention.
Tsui does not teach: a nitride layer having the first metal and disposed between the metal plug and the recess.
Figure 13 of Adusumilli teaches: a metal layer of Titanium Nitride is deposited on the second silicide layer (1102) (Paragraph 0063; Not pictured) between the metal plug (1202) and the recess (Paragraph 0060).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a nitride layer having the first metal and disposed between the metal plug and the recess because Adusumilli teaches a Titanium Nitride layer is deposited in the recess on the second silicide layer to act as a liner/barrier layer for the following metal fill layer (Adusumilli Paragraph 0063).
Regarding Claim 8, the combination of Tsui and Adusumilli teaches all of the limitations of the claimed invention.
Tsui does not teach: the nitride layer is in contact with at least a portion of an upper surface of the second silicide layer.
Figure 13 of Adusumilli teaches: a metal layer of Titanium Nitride is deposited on the second silicide layer (1102) (Paragraph 0063; Not pictured)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the nitride layer is in contact with at least a portion of an upper surface of the second silicide layer because Adusumilli teaches a Titanium Nitride layer is deposited in the recess on the second silicide layer to act as a liner/barrier layer for the following metal fill layer (Adusumilli Paragraph 0063).
Regarding Claim 9, Figure 6 of Tsui teaches: the device feature (232) includes a silicon-based structure (Paragraph 0018 where 238 is formed in silicon substrate 210) or region that serves as a drain/source terminal (238) of a transistor.
Regarding Claim 10, the device feature (232) includes a poly-silicon structure (Paragraph 0013) that serves as a gate terminal (228) of a transistor.
Regarding Claim 12, Figure 6 of Tsui teaches: A semiconductor device (200), comprising: a transistor (232) comprising at least one terminal (238) that contains silicon (Paragraph 0018; Where 238 is formed in silicon substrate 210); a metal plug (252) electrically coupled to the at least one terminal (Paragraph 0029); a first silicide layer (246) disposed between the metal plug and the at least one terminal, and having a first metal (Paragraph 0022; Titanium) and a topmost surface (top vertically of 246).
Tsui does not teach: a second silicide layer disposed between the metal plug and the at least one terminal, and having a second metal,
Figure 13 of Adusumilli teaches: a semiconductor device (900), comprising a terminal (905), a metal plug (1202), and a second silicide layer (1102) disposed between the metal plug and the at least one terminal and having a second metal (Paragraph 0062)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a second silicide layer comprising a first portion disposed between the metal plug and the at least one terminal, and having a second metal because Adusumilli teaches contact resistance variability is reduced by the formation of textured silicides in the contact (Adusumilli Paragraph 0004).
Tsui does not teach: wherein a bottommost surface of the second silicide layer is positioned above and in direct contact with a topmost surface of the first silicide layer; wherein the first metal is different from the second metal.
However, when the second silicide layer as described in Adusumilli is combined with the structure of Tsui, a structure will be yielded such that a bottommost surface of the second silicide layer is positioned above and in direct contact with a topmost surface of the first silicide layer, and wherein the first metal is different from the second metal.
Regarding Claim 13, the combination of Tsui and Adusumilli teaches all of the limitations of the claimed invention.
Figure 6 of Tsui teaches: the first silicide layer includes titanium silicide (Paragraph 0022) and that silicide features (246) can include nickel silicide (Paragraph 0022)
Tsui does not teach: the second silicide layer includes nickel silicide (NiSi)
Therefore, the combination of the second silicide of Adusumilli with the materials of Tsui will yield a structure such that the second silicide layer includes nickel silicide (NiSi).
Regarding Claim 14, Figure 6 of Tsui teaches: the first silicide layer (246) is embedded within the terminal (238), with an upper surface exposed from an upper surface of the terminal (Figure 6).
Regarding Claim 15, the combination of Tsui and Adusumilli teaches all of the limitations of the claimed invention.
Tsui does not teach: the second silicide layer, in direct contact with the first silicide layer, further comprises a second portion extending along sidewalls of the metal plug.
Figure 13 of Adusumilli teaches: the second silicide layer (1102) is in direct contact with the first silicide layer (1002) and comprises a portion extending along sidewalls of the metal plug (1202).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the second silicide layer, in direct contact with the first silicide layer, further comprises a second portion extending along sidewalls of the metal plug because Adusumilli teaches a structure with a silicide formed along sidewalls of a metal plug reduces variability in contact resistance (Adusumilli Paragraph 0004).
Regarding Claim 16, the combination of Tsui and Adusumilli teaches all of the limitations of the claimed invention.
Tsui does not teach: the second silicide layer, in direct contact with the first silicide layer, has sidewalls inwardly recessed from sidewalls of the first silicide layer, respectively.
However, the combination of the second silicide layer of Adusumilli with the structure of Tsui, will yield a structure such that the second silicide layer, in direct contact with the first silicide layer, has sidewalls inwardly recessed from sidewalls of the first silicide layer, respectively.
Regarding Claim 17, Figures 2-6 of Tsui teaches: A method for fabricating semiconductor devices (200), comprising: forming a recess (250) extending through a dielectric layer (248) to expose a portion of a silicon-based device feature (238); forming a first silicide layer (246) at a position of the exposed portion of the silicon-based device feature, wherein the first silicide layer contains a first metal (Paragraph 0022; Titanium) and has a topmost surface (top vertically of 246); and forming a metal plug (252) within the recess.
Tsui does not teach: forming a second silicide layer over the first silicide layer, wherein the second silicide layer contains a second metal
Figure 13 of Adusumilli teaches: a semiconductor device (900), comprising a second silicide layer (1102) having a second metal (Paragraph 0062)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a second silicide layer over the first silicide layer because Adusumilli teaches contact resistance variability is reduced by the formation of textured silicides in the contact (Adusumilli Paragraph 0004).
Tsui does not teach: a bottommost surface of the second silicide layer is positioned above and in direct contact with a topmost surface of the first silicide layer; wherein the first metal is different from the second metal
However, when the second silicide layer as described in Adusumilli is combined with the structure of Tsui, a structure will be yielded such that a bottommost surface of the second silicide layer is positioned above and in direct contact with a topmost surface of the first silicide layer and wherein the first metal is different from the second metal.
Regarding Claim 18, the combination of Tsui and Adusumilli teaches all of the limitations of the claimed invention.
Figure 6 of Tsui teaches: the first silicide layer includes titanium silicide (Paragraph 0022) and that silicide features (246) can include nickel silicide (Paragraph 0022)
Tsui does not teach: the second silicide layer includes nickel silicide (NiSi)
Therefore, the combination of the second silicide of Adusumilli with the materials of Tsui will yield a structure such that the second silicide layer includes nickel silicide (NiSi).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Tsui et al. (US 20130020623 A1) hereinafter “Tsui” in view of Adusumilli et al. (US 20180226352 A1) hereinafter “Adusumilli”, as evidenced by Nishmoto et al. (US 20100226004 A1) hereinafter “Nishmoto” and Ramasubramanian et al. (US 20120115026 A1) hereinafter “Ramasubramanian”.
Regarding Claim 11, the combination of Tsui and Adusumilli teaches all of the limitations of the claimed invention.
Figure 6 of Tsui teaches: the first silicide layer (246) has a first resistivity (Paragraph 0022; resistivity of titanium silicide)
Tsui does not teach: the second silicide layer has a second resistivity, and wherein the second resistivity is less than the first resistivity.
However, the combination of the second silicide layer of Adusumilli with the silicide materials of Tsui, will yield a structure such that the second silicide layer has a second resistivity, and wherein the second resistivity is less than the first resistivity.
Further, evidentiary reference Nishmoto teaches the resistivity of titanium silicide (TiSi2) is as low as 15 to 20 µΩ∙cm (Nishmoto Paragraph 0084), and evidentiary reference Ramasubramanian teaches the resistivity of nickel silicide (NiSi) is 10 to 60 µΩ∙cm (Ramasubramanian Paragraph 0031).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Tsui et al. (US 20130020623 A1) hereinafter “Tsui” in view of Adusumilli et al. (US 20180226352 A1) hereinafter “Adusumilli” and Wang et al. (US 20150364560 A1) hereinafter “Wang”.
Regarding Claim 19, the combination of Tsui and Adusumilli teaches all of the limitations of the claimed invention.
Tsui does not teach: the step of forming a second silicide layer over the first silicide layer further comprises: depositing a silicon layer lining the recess; depositing a metal layer, containing the second metal, that lines the recess; and annealing the silicon layer and the metal layer to form the second silicide layer.
Figure 6 of Wang teaches: a silicide (604) is formed over a sidewall (504), by depositing an amorphous silicon layer (not shown), depositing a metal layer (not shown) over the amorphous silicon layer, then annealing (Paragraph 0021)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a silicon layer be deposited to line the recess, as the deposition of a silicon layer followed by a metal layer and an annealing process, is known to create silicide layers (Wang Paragraph 0021).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Tsui et al. (US 20130020623 A1) hereinafter “Tsui” in view of Adusumilli et al. (US 20180226352 A1) hereinafter “Adusumilli,” Wang et al. (US 20150364560 A1) hereinafter “Wang” and Or et al. (US 20060051966 A1) hereinafter “Or.”
Regarding Claim 20, the combination of Tsui and Adusumilli teaches all of the limitations of the claimed invention.
Tsui does not teach: the step of forming a second silicide layer over the first silicide layer further comprises: depositing a silicon layer lining the recess; respectively; depositing a metal layer, containing the second metal, that lines the recess; and annealing the silicon layer and the metal layer to form the second silicide layer.
Figure 6 of Wang teaches: a silicide (604) is formed over a sidewall (504), by depositing an amorphous silicon layer (not shown), depositing a metal layer (not shown) over the amorphous silicon layer, then annealing (Paragraph 0021)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a silicon layer be deposited to line the recess, as the deposition of a silicon layer followed by a metal layer and an annealing process, is known to create silicide layers (Wang Paragraph 0021).
Tsui does not teach: etching portions of the silicon layer that extend along inner sidewalls of the recess,
Figures 5E-5G of Or teach: an etch is performed on silicon layer (585) to expose silicon layers beneath (Paragraph 0111)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to etch portions of the silicon layer that extend along inner sidewalls of the recess because conventional furnace annealing is performed on the metal and silicon layers to form metal silicide in regions in which the metal layer is in contact with silicon, therefore creating silicide regions where desired (Or Paragraph 0112).
Allowable Subject Matter
Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 5, the prior art of record does not teach, suggest, or motivate one having ordinary skill in the art to have the metal layer is in contact with end portions of the topmost surface of the first silicide layer, along with the limitations of Claims 4 and 1.
Response to Arguments
Applicant's arguments filed 11/25/2025 have been fully considered but they are not persuasive.
Regarding Claim 1, and similarly Claims 12 and 17, the Applicant argues that the combination of Tsui and Adusumilli does not teach the amended claim language of “the bottommost surface of the second silicide layer is in direct contact with a topmost surface of the first silicide layer”. The Examiner respectfully disagrees and asserts that the combination of Tsui and Adusumilli does teach the amended claim language. As stated in the 35 U.S.C. 103 rejection of Claim 1 above, Tsui teaches an embedded first silicide layer (246) having a topmost surface. Adusumilli teaches a second silicide layer (1102) formed on the sidewalls of a first silicide layer (1002), as well as the lateral bottom surface of the recess (Figure 11). The combination of the second silicide layer, of Adusumilli, formed to fully surround sidewalls and bottom surfaces of a recess, with the embedded first silicide layer, of Tsui, will yield a structure such that the bottommost surface of the second silicide layer is in direct contact with a topmost surface of the first silicide layer. Therefore, the Examiner does not find the Applicant’s arguments to be persuasive and will continue to rely upon the combination of Tsui and Adusumilli to teach the amended claim language of Claim 1, and similarly Claims 12 and 17.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Halee Cramer whose telephone number is (571)270-1641. The examiner can normally be reached Monday - Friday 7:30am - 4:30pm.
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/HALEE CRAMER/Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891