DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 35 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/24/2026 has been entered.
Remarks
The 03/10/2026 amendments of claims 1, 9, 11, 13, 15-17, 21 and 24-25 have been noted and entered.
The 03/10/2026 addition of the new claim 26 has been noted and entered.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/16/2026 and 04/23/2026 was filed after the mailing date of the application on 01/27/2022. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Arguments
Applicant’s arguments, see Remarks pages 8-11, filed 03/10/2026, with respect to the rejection(s) of claim(s) 1-7,9-17,21 and 23-25 under 35 U.S.C. 103 have been fully considered and are persuasive in light of the newly added amendments. However, upon further consideration, a new ground(s) of rejection is made in view of Liao et al, US 20170203959 A1 (Liao) and Lounis et al. TCAD simulations of planar pixel sensors. The 20th Anniversary International Workshop on Vertex Detectors – Vertex 2011 Rust, Lake Neusiedl, Austria (June 19 – 24, 2011) (Lounis).
New Grounds of Rejection
New grounds of rejection, prior art references Liao et al, US 20170203959 A1 (Liao) and Lounis et al. TCAD simulations of planar pixel sensors. The 20th Anniversary International Workshop on Vertex Detectors – Vertex 2011 Rust, Lake Neusiedl, Austria (June 19 – 24, 2011) (Lounis), appear below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claims 1-5, 7, 13-16 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Vincent et al, US 20150270233 A1 (Vincent) in view of Huang et al, US 10269728 B2 (Huang ‘728) in further view of Liao et al, US 20170203959 A1 (Liao) in further view of Lounis et al. TCAD simulations of planar pixel sensors. The 20th Anniversary International Workshop on Vertex Detectors – Vertex 2011 Rust, Lake Neusiedl, Austria (June 19 – 24, 2011) (Lounis).
Regarding claim 1; Vincent teaches a semiconductor device (Vincent: Fig (10): 130), comprising:
a first semiconductor die (52); and
a redistribution structure (66) disposed over a first side of the first semiconductor die (52) and comprising a plurality of layers (66),
wherein at least a first one of the plurality of layers comprises a first power/ground plane (94) embedded in a dielectric material ([0013]: “FIGS. 10 and 11 are cross-sectional views illustrating FO-WLPs produced to include metal fill features within the routing-free dielectric blocks located within the redistribution layers”) and configured to provide a first supply voltage (84) for the first semiconductor die (52),
wherein the first power/ground plane (94) encloses: a plurality of first conductive structures (86) that are each operatively coupled to the first semiconductor die (52) and a plurality of second conductive structures (132),
wherein the plurality of first conductive structures (86) are surrounded by the plurality of second conductive structures (132) (Looking at Figures (10) and (2) shows that the first conductive structures (86) are surrounded by a plurality of second conductive structures (132) in the same layer (66)), and
wherein the first power/ground plane includes a region in which each one of the plurality of second conductive structures is surrounded by other ones of the plurality of second conductive structures in a top view of the first plurality of layers,
wherein the plurality of second conductive structures (132) each have a floating voltage (see paragraph [0033]: “In certain embodiments, the metal fill features assume the form of floating dummy plates, which are electrically isolated from the interconnect lines surrounding the routing-free dielectric block.”) and,
wherein the first power/ground plane further encloses a guard ring that partially or fully surrounds the plurality of first conductive structures and the plurality of second conductive structures,
wherein a minimum spacing between the guard ring and a neighboring conductive structure of the plurality of first conductive structures is equal to or greater than about 20 µm.
Vincent does not teach wherein the first power/ground plane includes a region in which each one of the plurality of second conductive structures is surrounded by other ones of the plurality of second conductive structures in a top view of the first plurality of layers.
Huang ‘728 teaches wherein the first power/ground plane includes a region (see the region signified by (800) in Fig (17C) of Huang ‘728 shared in this OA) in which each one of the plurality of second conductive structures (GND) is surrounded by other ones of the plurality of second conductive structures (GND) in a top view of the first of the plurality of layers. Vincent and Huang ‘728 are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of this application, to a person having ordinary skill in the art to modify Vincent by making each one of the plurality of second conductive structures is surrounded by other ones of the plurality of second conductive structures in a top view as disclosed in Huang ‘728 to make establishing the electrical connections easier leading to a more efficient device construction process.
Vincent in view of Huang ‘728 does not teach wherein the first power/ground plane further encloses a guard ring that partially or fully surrounds the plurality of first conductive structures and the plurality of second conductive structures.
However, Liao teaches wherein the first power/ground plane (Liao: Annotated Fig (14B): 21) further encloses a guard ring (23) that partially or fully surrounds the plurality of first conductive structures (First Conductive Structures) and the plurality of second conductive structures (Second Conductive Structures).
Vincent in view of Huang ‘728 and Liao are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Vincent in view of Huang ‘728 by constructing the guard rings as disclosed in Liao to improve the insulation of the conductive structures and thus reduce the possibilities of short circuits or cross talk in the circuit leading to a more reliable device.
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Vincent in view of Huang ‘728 in further view of Liao does not teach wherein a minimum spacing between the guard ring and a neighboring conductive structure of the plurality of first conductive structures is equal to or greater than about 20 µm.
Lounis teaches wherein a minimum spacing between the guard ring (Lounis: Annotated Fig (1): Guard Ring) and a neighboring conductive structure (Conductive Structure) of the plurality of first conductive structures (Conductive Structures) is equal to or greater than about 20 µm (Fig (2): the figure shows the correlation between the distance away from guard ring and electric potential/electric field that can lead to breakdown potential level being reached. The figure clearly indicates that more distance between the guard ring and the conductive features lowers the electric potential/electric field build up in the device).
Vincent in view of Huang ‘728 in further view of Liao and Lounis are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Vincent in view of Huang ‘728 in further view of Liao by constructing the guard rings such that the distance between the guard ring and the conductive structures is more than 20 µm as disclosed in Lounis to reduce the chances of having a high electric potential cause a breakdown or leakage current in the device leading to a more reliable device.
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Regarding claim 2; Vincent in view of Huang ‘728 in view of Liao in further view of Lounis discloses all the semiconductor device of claim 1.
Further, Vincent teaches wherein the redistribution structure (Vincent: Fig (4): 66) is configured to provide a conductive pattern (94+84+86) that allows a pin-out contact pattern (68) for the semiconductor device (52) being packaged, and wherein the pin-out contact pattern (68) is different than a pattern of first connectors (64).
Regarding claim 3; Vincent in view of Huang ‘728 in view of Liao in further view of Lounis discloses all the semiconductor device of claim 2.
Further, Vincent teaches wherein the first connectors (Vincent: Fig (10): 64) are disposed on the first side of the first semiconductor die (52).
Regarding claim 4; Vincent in view of Huang ‘728 in view of Liao in further view of Lounis discloses all the semiconductor device of claim 2.
Further, Vincent teaches wherein the pin-out contact pattern (Vincent: Fig (10): 68) is disposed on a first side of the redistribution structure (66) being opposite to a second side of the redistribution structure (66) that faces the first side (54) of the first semiconductor die (52).
Regarding claim 5; Vincent in view of Huang ‘728 in view of Liao in further view of Lounis discloses all the semiconductor device of claim 2.
Further, Vincent teaches wherein the pin-out contact pattern (Vincent: Fig (10): 68) is electrically connected to second connectors (84) that are disposed on the first side (82) of the redistribution structure (66), and wherein the second connectors (84) are electrically coupled to a substrate (52).
Regarding claim 7; Vincent in view of Huang ‘728 in view of Liao in further view of Lounis discloses all the semiconductor device of claim 1.
However, Vincent in view of Huang ‘728 in further view of Liao in further view of Lounis does not teach further comprising: a third semiconductor die disposed laterally adjacent the first semiconductor die; wherein at least a third one of the plurality of layers comprises a third power/ground plane embedded in the dielectric material and configured to provide a third supply voltage for the third semiconductor die; and wherein the third power/ground plane encloses: a plurality of fifth conductive structures that are each operatively coupled to the third semiconductor die; and a plurality of sixth conductive structures scattered around the plurality of fifth conductive structures.
However, it would have been obvious to one of ordinary skill in the art at the time of filing this application to modify Vincent by adding a third semiconductor die adjacent to the first semiconductor die by repeating the steps disclosed in Vincent over and over again to expand the use of the technique disclosed in Vincent to use with multiple semiconductor dies which would lead to a compact packaging of semiconductor devices. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960) (Claims at issue were directed to a water-tight masonry structure wherein a water seal of flexible material fills the joints which form between adjacent pours of concrete. The claimed water seal has a "web" which lies in the joint, and a plurality of "ribs" projecting outwardly from each side of the web into one of the adjacent concrete slabs. The prior art disclosed a flexible water stop for preventing passage of water between masses of concrete in the shape of a plus sign (+). Although the reference did not disclose a plurality of ribs, the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced.).
Regarding claim 13; Vincent teaches a semiconductor device (Vincent: Fig (10): 130), comprising:
a redistribution layer (66) configured to redistribute connectors (64) of a semiconductor die (52),
wherein the redistribution layer (66) comprises a plurality of conductive structures (84+86) embedded in a dielectric material ([0013]: “FIGS. 10 and 11 are cross-sectional views illustrating FO-WLPs produced to include metal fill features within the routing-free dielectric blocks located within the redistribution layers”),
wherein a first subset of the plurality of conductive structures (84+86) are each configured to carry a first type of signal generated by the semiconductor die (52),
wherein a second subset of the plurality of conductive structures (132) are configured to collectively surround the first subset of the plurality of conductive structures (84+86, Looking at Figures (10) and (2) shows that the first conductive structures 84+86 are surrounded by a plurality of conductive structures 132),
the second subset of the plurality of conductive structures being floating ([0033]: “…the metal fill features assume the form of floating dummy plates, which are electrically isolated from the interconnect lines surrounding the routing-free dielectric block…”).
wherein the redistribution layer includes a portion over which each one of the second subset of the plurality of conductive structures is surrounded by other ones of the second subset of the plurality of conductive structures in a top view of the redistribution layer,
wherein a guard ring partially or fully surrounds the first subset of the plurality of conductive structures and the second subset of the plurality of conductive structures,
wherein a minimum spacing between the guard ring and a neighboring conductive structure of the first subset of the plurality of conductive structures is equal to or greater than about 20 µm.
Vincent does not teach wherein the redistribution layer includes a portion over which each one of the second subset of the plurality of conductive structures is surrounded by other ones of the second subset of the plurality of conductive structures in a top view of the redistribution layer.
Huang ‘728 teaches wherein the redistribution layer (Huang ‘728: Fig (17C): 800) includes a portion over which each one of the second subset of the plurality of conductive structures (GND) is surrounded by other ones of the second subset of the plurality of conductive structures (GND) in a top view of the redistribution layer (800).
Vincent and Huang ‘728 are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of this application, to a person having ordinary skill in the art to modify Vincent by making each one of the plurality of second conductive structures is surrounded by other ones of the plurality of second conductive structures in a top view as disclosed in Huang ‘728 to make establishing the electrical connections easier leading to a more efficient device construction process.
Vincent in view of Huang ‘728 does not teach wherein a guard ring partially or fully surrounds the first subset of the plurality of conductive structures and the second subset of the plurality of conductive structures.
However, Liao teaches wherein the first power/ground plane further encloses a guard ring (Liao: Annotated Fig (14B): 23) partially or fully surrounds the first subset of the plurality of conductive structures (First Conductive Structures) and the second subset of the plurality of conductive structures (Second Conductive Structures).
Vincent in view of Huang ‘728 and Liao are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Vincent in view of Huang ‘728 by constructing the guard rings as disclosed in Liao to improve the insulation of the conductive structures and thus reduce the possibilities of short circuits or cross talk in the circuit leading to a more reliable device.
Vincent in view of Huang ‘728 in further view of Liao does not teach wherein a minimum spacing between the guard ring and a neighboring conductive structure of the plurality of first conductive structures is equal to or greater than about 20 µm.
Lounis teaches wherein a minimum spacing between the guard ring (Lounis: Annotated Fig (1): Guard Ring) and a neighboring conductive structure (Conductive Structure) of the plurality of first conductive structures (Conductive Structures) is equal to or greater than about 20 µm (Fig (2): the figure shows the correlation between the distance away from guard ring and electric potential/electric field that can lead to breakdown potential level being reached. The figure clearly indicates that more distance between the guard ring and the conductive features lowers the electric potential/electric field build up in the device).
Vincent in view of Huang ‘728 in further view of Liao and Lounis are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Vincent in view of Huang ‘728 in further view of Liao by constructing the guard rings such that the distance between the guard ring and the conductive structures is more than 20 µm as disclosed in Lounis to reduce the chances of having a high electric potential cause a breakdown or leakage current in the device leading to a more reliable device.
Regarding claim 14; Vincent in view of Huang ‘728 in view of Liao in further view of Lounis discloses all the semiconductor device of claim 13.
Further, Vincent teaches wherein the plurality of conductive structures (Vincent: Fig (4),(6): 94+84+86) comprise a power/ground plane (94) configured to provide the semiconductor die (52) with a supply voltage.
Regarding claim 15; Vincent in view of Huang ‘728 in view of Liao in further view of Lounis discloses all the semiconductor device of claim 14.
Further, Vincent teaches wherein the power/ground plane (Vincent: Figs (4),(6): 94+84) surrounds the first subset of the plurality of conductive structures (86) and the second subset of the plurality of conductive structures (132).
Regarding claim 16; Vincent in view of Huang ‘728 in view of Liao in further view of Lounis discloses all the semiconductor device of claim 15.
Further, Vincent teaches wherein the power/ground plane (Vincent: Figs (4),(6): 94) further surrounds a third subset of the plurality of conductive structures (84) that are each configured to carry a second type of signal generated by the semiconductor die (52), and wherein each of the first subset of the plurality of conductive structures (84) extends along a lateral direction with a first length (84) and each of the second subset of the plurality of conductive structures extends along the lateral direction (84) with a second length, the first length being substantially shorter than the second length (84).
Regarding claim 21; Vincent teaches a semiconductor device (Vincent: Fig (10): 130), comprising:
a semiconductor die (52); and
a redistribution structure (66) disposed over a side of the semiconductor die (52) and comprising a plurality of layers (66),
wherein at least one of the plurality of layers comprises a power/ground plane (Figs (4), (6): 94) embedded in a dielectric material ([0013]: “FIGS. 10 and 11 are cross-sectional views illustrating FO-WLPs produced to include metal fill features within the routing-free dielectric blocks located within the redistribution layers”) and configured to provide a supply voltage (Fig (10): 84) for the semiconductor die (52),
wherein the power/ground plane (Figs (4), (6), (10): 94) encloses, in a top view: a plurality of first conductive structures (86) that are each formed to surround a portion of the dielectric material ([0013]: “FIGS. 10 and 11 are cross-sectional views illustrating FO-WLPs produced to include metal fill features within the routing-free dielectric blocks located within the redistribution layers”) and a plurality of second conductive structures (132) formed to surround one or more of the plurality of first conductive structures (132) in the power/ground plane (66), and
wherein each of the plurality of first conductive structures (86) is configured to carry a signal with a frequency from hundreds of megahertz to hundreds of gigahertz ([0041], Since the device claimed by Vincent contains a microelectronic component it stands to reason that it could be a device capable of processing radiofrequencies and thus it operates in the range claimed), with each of the plurality of the second conductive structures (132) being floating ([0033]: “In certain embodiments, the metal fill features assume the form of floating dummy plates, which are electrically isolated from the interconnect lines surrounding the routing-free dielectric block.”);
wherein the first power/ground plane further encloses a guard ring that partially or fully surrounds the plurality of first conductive structures and the plurality of second conductive structures,
wherein a minimum spacing between the guard ring and a neighboring conductive structure of the plurality of first conductive structures is equal to or greater than about 20 µm.
Vincent does not teach wherein the power/ground plane comprises a region having more than one of the plurality of second conductive structures while being free of any one of the plurality of first conductive structures in the top view of the power/ground plane.
Huang ‘728 teaches wherein the power/ground plane comprises a region (see the region designated by (800) in Fig (17C) of Huang ‘728 shared in this OA) having more than one of the plurality of second conductive structures (GND) while being free of any one of the plurality of first conductive structures (P2) in the top view of the power/ground plane. Vincent and Huang ‘728 are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application to one of ordinary skill in the art to modify Vincent by constructing a region in the redistribution layer where the second conductive structures are not surrounded by the first conductive features as disclosed in Huang ‘728 to make routing the connections to the chips easier leading to a more efficient device construction process.
Vincent in view of Huang ‘728 does not teach wherein the first power/ground plane further encloses a guard ring that partially or fully surrounds the plurality of first conductive structures and the plurality of second conductive structures.
However, Liao teaches wherein the first power/ground plane (Liao: Annotated Fig (14B): 21) further encloses a guard ring (23) that partially or fully surrounds the plurality of first conductive structures (First Conductive Structures) and the plurality of second conductive structures (Second Conductive Structures).
Vincent in view of Huang ‘728 and Liao are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Vincent in view of Huang ‘728 by constructing the guard rings as disclosed in Liao to improve the insulation of the conductive structures and thus reduce the possibilities of short circuits or cross talk in the circuit leading to a more reliable device.
Vincent in view of Huang ‘728 in further view of Liao does not teach wherein a minimum spacing between the guard ring and a neighboring conductive structure of the plurality of first conductive structures is equal to or greater than about 20 µm.
Lounis teaches wherein a minimum spacing between the guard ring (Lounis: Annotated Fig (1): Guard Ring) and a neighboring conductive structure (Conductive Structure) of the plurality of first conductive structures (Conductive Structures) is equal to or greater than about 20 µm (Fig (2): the figure shows the correlation between the distance away from guard ring and electric potential/electric field that can lead to breakdown potential level being reached. The figure clearly indicates that more distance between the guard ring and the conductive features lowers the electric potential/electric field build up in the device).
Vincent in view of Huang ‘728 in further view of Liao and Lounis are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Vincent in view of Huang ‘728 in further view of Liao by constructing the guard rings such that the distance between the guard ring and the conductive structures is more than 20 µm as disclosed in Lounis to reduce the chances of having a high electric potential cause a breakdown or leakage current in the device leading to a more reliable device.
Claims 6, 9-12 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Vincent et al, US 20150270233 A1 (Vincent) in view of Huang et al, US 10269728 B2 (Huang ‘728) in further view of Liao et al, US 20170203959 A1 (Liao) in further view of Lounis et al. TCAD simulations of planar pixel sensors. The 20th Anniversary International Workshop on Vertex Detectors – Vertex 2011 Rust, Lake Neusiedl, Austria (June 19 – 24, 2011) (Lounis) in further view of Huang, US 11107775 B1 (Huang ‘775)
Regarding claim 6; Vincent in view of Huang ‘728 in further view of Liao in further view of Lounis discloses all the limitations of the semiconductor device of claim 1.
However, Vincent in view of Huang ‘728 does not teach further comprising: a second semiconductor die disposed on a second side of the first semiconductor die opposite to the first side of the first semiconductor die; wherein at least a second one of the plurality of layers comprises a second power/ground plane embedded in the dielectric material and configured to provide a second supply voltage for the second semiconductor die; and wherein the second power/ground plane encloses: a plurality of third conductive structures that are each operatively coupled to the second semiconductor die; and a plurality of fourth conductive structures scattered around the plurality of third conductive structures.
Huang ‘775 teaches further comprising: a second semiconductor die (Huang ‘775: Fig (1): 201) disposed on a second side of the first semiconductor die (101) opposite to the first side of the first semiconductor die (101); wherein at least a second one of the plurality of layers comprises a second power/ground plane (203) embedded in the dielectric material (205) and configured to provide a second supply voltage for the second semiconductor die (201); and wherein the second power/ground plane (203) encloses: a plurality of third conductive structures (207) that are each operatively coupled to the second semiconductor die (201); and a plurality of fourth conductive structures (411) scattered around the plurality of third conductive structures (207).
Vincent in view of Huang ‘728 in further view of Liao in further view of Lounis and Huang ‘775 are considered analogous art. Thus, it would have obvious to one of ordinary skill in the art to modify Vincent in view of Huang ‘728 in further view of Liao in further view of Lounis by introducing the second semiconductor die and the supporting network of connectors as disclosed in Huang ‘775 to expand the use of the packaging technique used in Vincent to more complex devices achieving compact packaging for more semiconductor devices.
Regarding claim 9; Vincent in view of Huang ‘728 in further view of Liao in further view of Lounis discloses all the limitations of the semiconductor device of claim 1.
However, Vincent in view of Huang ‘728 in further view of Liao in further view of Lounis does not teach wherein the first power/ground plane further encloses a power/ground reference structure laterally spaced from the plurality of first conductive structures and the plurality of second conductive structure.
Huang ‘775 teaches wherein the first power/ground (Huang ‘775: Fig (1): 203) plane further encloses a power/ground reference structure (211) laterally spaced from the plurality of first conductive structures (207) and the plurality of second conductive structures (411).
Vincent in view of Huang ‘728 in further view of Liao in further view of Lounis and Huang ‘775 are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to one of ordinary skill in the art to modify Vincent in view of Huang ‘728 in further view of Liao in further view of Lounis by introducing the power/ground reference structure disclosed in Huang ‘775 to increase the number of ways the redistribution layer can connect different devices and to increase the effects of shielding the signal carrying wires from crosstalk or parasitic electrical effects.
Regarding claim 10; Vincent in view of Huang ‘728 in further view of Liao in further view of Lounis in further view of Huang ‘775 discloses all the limitations of the semiconductor device of claim 9.
However, Vincent in view of Huang ‘728 does not teach wherein the guard ring is either connected to or isolated from the first power/ground plane.
Huang ‘775 teaches wherein the guard ring (215) is either connected to or isolated from the first power/ground plane (203). Vincent in view of Huang ‘728 and Huang ‘775 are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to one of ordinary skill in the art to modify Vincent in view of Huang ‘728 by introducing the guard ring structure disclosed in Huang ‘775 to improve the isolation of the connection to lower the chances of short-circuiting the contacts leading to a more reliable device.
Regarding claim 11; Vincent in view of Huang ‘728 in further view of Liao in further view of Lounis in further view of Huang ‘775 discloses all the limitations of the semiconductor device of claim 9.
However, Vincent in view of Huang ‘728 in further view of Liao in further view of Lounis does not teach wherein the power/ground reference structure is tied to the first supply voltage.
Huang ‘775 teaches wherein the power/ground reference structure (Huang ‘775: Fig (1): 211) is tied to the first supply voltage.
Vincent in view of Huang ‘728 in further view of Liao in further view of Lounis and Huang ‘775 are considered analogous art. Thus, it would have been obvious to one of ordinary skill in the art to modify Vincent in view of Huang ‘728 in further view of Liao in further view of Lounis by introducing the power/ground reference structure disclosed in Huang ‘775 to increase the number of ways the redistribution layer can connect different devices and to increase the effects of shielding the signal carrying wires from crosstalk or parasitic electrical effects.
Regarding claim 12; Vincent in view of Huang ‘728 in further view of Liao in further view of Lounis in further view of Huang ‘775 discloses all the limitations of the semiconductor device of claim 11.
However, Vincent in view of Huang ‘728 in further view of Liao in further view of Lounis does not teach wherein the power/ground reference structure is either connected to or isolated from the guard ring.
Huang ‘775 teaches wherein the power/ground reference structure (Huang ‘775: Fig (1): 211) is either connected to or isolated from the guard ring (411).
Vincent in view of Huang ‘728 in further view of Liao in further view of Lounis and Huang ‘775 are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to one of ordinary skill in the art to modify Vincent in view of Huang ‘728 in further view of Liao in further view of Lounis by introducing the guard ring structure disclosed in Huang ‘775 to improve the isolation of the connection to lower the chances of short-circuiting the contacts leading to a more reliable device.
Regarding claim 23; Vincent in view of Huang ‘728 in further view of Liao in further view of Lounis discloses all the limitations of the semiconductor device of claim 21.
However, Vincent in view of Huang ‘728 in further view of Liao in further view of Lounis does not teach wherein the first power/ground plane further encloses a power/ground reference structure laterally spaced from the plurality of first conductive structures and the plurality of second conductive structures, and wherein the power/ground reference structure is tied to the first supply voltage.
Huang ‘775 teaches wherein the first power/ground (Huang: Fig (1): 203) plane further encloses a power/ground reference structure (211) laterally spaced from the plurality of first conductive structures (207) and the plurality of second conductive structures (411), and wherein the power/ground reference structure (211) is tied to the first supply voltage.
Vincent in view of Huang ‘728 in further view of Liao in further view of Lounis and Huang ‘775 are considered analogous art. Thus, it would have been obvious to one of ordinary skill in the art to modify Vincent in view of Huang ‘728 in further view of Liao in further view of Lounis by introducing the power/ground reference structure disclosed in Huang ‘775 to increase the number of ways the redistribution layer can connect different devices and to increase the effects of shielding the signal carrying wires from crosstalk or parasitic electrical effects.
Claims 17 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Vincent et al, US 20150270233 A1 (Vincent) in view of Huang et al, US 10269728 B2 (Huang ‘728) in further view of Liao et al, US 20170203959 A1 (Liao) in further view of Lounis et al. TCAD simulations of planar pixel sensors. The 20th Anniversary International Workshop on Vertex Detectors – Vertex 2011 Rust, Lake Neusiedl, Austria (June 19 – 24, 2011) (Lounis) in further view of Lee et al, US 20210225708 A1 (Lee)
Regarding claim 17; Vincent in view of Huang ‘728 in further view of Liao in further view of Lounis discloses all the limitations of the semiconductor device of claim 13.
However, Vincent in view of Huang ‘728 in further view of Liao in further view of Lounis does not teach wherein a spacing between neighboring ones of the first subset of the plurality of conductive structures is equal to or greater than about 20 micrometers (µm).
Lee teaches wherein a spacing between neighboring ones of the first subset of the plurality of conductive structures (Lee: Fig (1I): WBspild) is equal to or greater than about 20 micrometers (µm) ([0009]: “… for example, W.sub.spild is greater than 50, 40 or 30 micrometers, and W.sub.sptsv is smaller than 50, 40 or 30 micrometers.”).
Vincent in view of Huang ‘728 in further view of Liao in further view of Lounis and Lee are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application to a person having ordinary skill in the art to modify Vincent in view of Huang ‘728 in further view of Liao in further view of Lounis to make the spacing between neighboring ones of the first subset of conductive structures to be equal to or greater than about 20 micrometers as disclosed in Lee to minimize the risk of short circuits and cross talk between the conductive structures.
Regarding claim 25; Vincent in view of Huang ‘728 in further view of Liao in further view of Lounis discloses all the limitations of the semiconductor device of claim 21.
However, Vincent in view of Huang ‘728 in further view of Liao in further view of Lounis does not teach wherein each of the plurality of the first conductive structures have a spacing of about 20 µm or greater.
Lee teaches wherein each of the plurality of first conductive structures (Lee: Fig(1I): WBspild) have a spacing of about 20 µm ([0009]: “… for example, W.sub.spild is greater than 50, 40 or 30 micrometers, and W.sub.sptsv is smaller than 50, 40 or 30 micrometers.”).
Vincent in view of Huang ‘728 in further view of Liao in further view of Lounis and Lee are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application to a person having ordinary skill in the art to modify Vincent in view of Huang ‘728 in further view of Liao in further view of Lounis to make the spacing between neighboring ones of the first subset of conductive structures to be equal to or greater than about 20 micrometers as disclosed in Lee to minimize the risk of short circuits and cross talk between the conductive structures.
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Vincent et al, US 20150270233 A1 (Vincent) in view of Huang et al, US 10269728 B2 (Huang ‘728) in further view of Liao et al, US 20170203959 A1 (Liao) in further view of Lounis et al. TCAD simulations of planar pixel sensors. The 20th Anniversary International Workshop on Vertex Detectors – Vertex 2011 Rust, Lake Neusiedl, Austria (June 19 – 24, 2011) (Lounis). in further view of Meyer-Berg et al, US 20130099383 A1 (Meyer-Berg)
Regarding claim 24; Vincent in view of Huang ‘728 in further view of Liao in further view of Lounis discloses all the limitations of the semiconductor device of claim 21.
However, Vincent in view of Huang ‘728 in further view of Liao in further view of Lounis does not teach wherein each of the plurality of the first conductive structures has a horseshoe-like structure.
Meyer-Berg teaches wherein each of the plurality of first conductive structures (Meyer-Berg: Fig (6): 603b) has a horseshoe-like. Vincent in view of Huang ‘728 in further view of Liao in further view of Lounis and Meyer-Berg are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Vincent in view of Huang ‘728 in further view of Liao in further view of Lounis by making the contact structure in a horseshoe-like shape as disclosed by Meyer-Berg to make establishing electrical connections with the contact structure easier.
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Vincent et al, US 20150270233 A1 (Vincent) in view of Huang et al, US 10269728 B2 (Huang ‘728) in further view of Liao et al, US 20170203959 A1 (Liao) in further view of Lounis et al. TCAD simulations of planar pixel sensors. The 20th Anniversary International Workshop on Vertex Detectors – Vertex 2011 Rust, Lake Neusiedl, Austria (June 19 – 24, 2011) (Lounis) in further view of Takata et al, US 5700975 A (Takata).
Regarding claim 26; Vincent in view of Huang ‘728 in further view of Liam in further view of Lounis discloses all the limitations of the semiconductor device of claim 21.
Vincent in view of Huang ‘728 in further view of Liam in further view of Lounis does not teach wherein the redistribution structure is configured to provide a conductive pattern that allows a pin-out contact pattern for the semiconductor device being packaged, and wherein the pin-out contact pattern is different than a pattern of first connectors.
Takata teaches wherein the redistribution structure (Takata: Annotated Fig (5) shared in this OA: 123, 124) is configured to provide a conductive pattern that allows a pin-out contact pattern (123) for the semiconductor device (100) being packaged, and wherein the pin-out contact pattern (123) is different than a pattern of first connectors (First Connectors).
Vincent in view of Huang ‘728 in further view of Liam in further view of Lounis and Takata are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Vincent in view of Huang ‘728 in further view of Liam in further view of Lounis by using the pin-out structure disclosed in Takata to increase the flexibility of design allowing for more convenient electrical connections to be established when constructing the device leading to a more reliable and efficient device manufacturing process.
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Conclusion
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/M.K./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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