DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 12-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dziura et al, US Patent Application Publication 2017/0167862 in view of Liu et al, US Patent Application Publication 2009/0063077 (both as cited in previous Office Action).
Regarding claim 12, Dziura teaches a system comprising:
an illumination source 110 configured to provide an amount of x-ray illumination light directed to a measurement spot 102 including one or more structures 320 fabricated on a semiconductor wafer (such as aspect ratio hole 320,321,322 in figures 8A-8C);
a detector 116 configured to detect an amount of x-ray light reflected from or transmitted through the semiconductor wafer in response to the amount of x-ray illumination light; and
a computing system 130 with 150 configured to determine values of one or more parameters of interest based on a fitting analysis of the detected amount of x-ray light with a geometrically parameterized response model of the one or more structures [0015, 0078],
wherein the geometrically parameterized response model characterizes an in-plane shape of the one or more structures with a geometric model, wherein the one or more structures includes a hole structure characterized by the geometrically parameterized response model ([0033], figures 1, 2, and 8A-8C).
Dziura fails to teach the geometric model for 2D repeating structure having more than two degrees of freedom, each degree parameter necessary to determine if the structure ultimately meets the design requirements.
However, certain structures fabricated in a semiconductor device will require a more complex geometric model (having more than two degrees of freedom) in order to determine if the structures having been fabricated according to the correct specification. Figure 3C of Lee teaches an instance wherein the a geometric model having more than two degrees of freedom.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lee with that of Dziura because certain structures fabricated in a semiconductor device will require a more complex geometric model in order to determine if the structures having been fabricated according to the correct specification.
Regarding claim 13, Lee teaches the geometric model includes a closed curve having a shape defined in a two dimensional plane by three of more independent parameters (figure 2C and [0038])
Regarding claims 14-16, Lee teaches the geometric model includes a closed curve comprising a piecewise assembly of two or more conic sections, wherein the piecewise assembly of two or more conic sections includes a plurality of elliptical sections, each of the plurality of elliptical sections described by independent radial and ellipicity parameters, wherein the piecewise assembly of conic sections includes a plurality of parabolic sections each described by two independent parameters (figure 2C and [0038])
Regarding claim 17, Dziura teaches the one or more structures includes a three-dimensional NAND structure or a dynamic random access memory (DRAM) structure [0032]
Regarding claim 18, Dziura teaches the values of the one or more parameters of interest are determined at a process step of a fabrication process flow of the one or more structures, and wherein an indication of the values of the one or more parameters of interest is communicated to the fabrication tool that causes the fabrication tool to adjust a value of one or more process control parameters of the fabrication tool at the process step [0003-0004]
Regarding claim 19, Lee teaches independent values of the geometric model vary as a function of depth into the one or more structures under measurement (figure 2B).
Regarding claim 20, Dziura teaches a system comprising:
an illumination source 110 configured to provide an amount of x-ray illumination light directed to a measurement spot 102 including one or more structures fabricated on a semiconductor wafer (such as aspect ratio hole 320,321,322 in figures 8A-8C);
a detector 116 configured to detect an amount of x-ray light reflected from or transmitted through the semiconductor wafer in response to the amount of x-ray illumination light; and
a non-transient, computer-readable medium storing instructions 130 with 150 that, when executed by one or more processors, causes the one or more processors to determine values of one or more parameters of interest based on a fitting analysis of the detected amount of x-ray light with a geometrically parameterized response model of the one or more structures [0015, 0078], wherein the geometrically parameterized response model characterizes an in-plane shape of the one or more structures with a geometric model, includes a hole structure characterized by the geometrically parameterized response model, wherein the one or more structures includes a hole structure characterized by the geometrically parameterized response model [0033]
Dziura fails to teach the geometric model for 2D repeating structure having more than two degrees of freedom, each degree parameter necessary to determine if the structure ultimately meets the design requirements.
However, certain structures fabricated in a semiconductor device will require a more complex geometric model (having more than two degrees of freedom) in order to determine if the structures having been fabricated according to the correct specification. Figure 3C of Lee teaches an instance wherein the a geometric model having more than two degrees of freedom.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lee with that of Dziura because certain structures fabricated in a semiconductor device will require a more complex geometric model in order to determine if the structures having been fabricated according to the correct specification.
Regarding claims 21 and 22, Dziura teaches the amount of x-ray illumination light is directed to the measurement spot at a plurality of angles of incidence, azimuth angles, or both (figures 7 and 8) and the amount of x-ray illumination light is directed to the measurement spot at a plurality of different energy levels (as shown in figures 8B and 8C, wherein the levels are at a different angle).
Regarding claim 23, Dziura and Liu fail to teach the geometric model includes a closed curve comprising a piecewise assembly of three or more conic sections.
However, this limitation is directed towards an article worked upon in the apparatus, which is the pattern shape of the substrate being worked on by the apparatus. According to the MPEP, Sections 2114 and 2115, while features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function and materials worked upon. The manner of operating the device does not differentiate apparatus claims from the prior art since “"[A]pparatus claims cover what a device is, not what a device does." Material or articles work upon does not limit apparatus claims as well Therefore, this limitation doesn’t determine the patentability of this apparatus.
Response to Arguments
Applicant's arguments filed 4 May 2026 have been fully considered but they are not persuasive.
In response to Applicant’s arguments that the cited prior art of record fails to teach the amended limitation of “includes a hole structure characterized by the geometrically parameterized response model”, it is noted that figures 8A-8C of Dziura teaches the use of hole structures in figures 8A-8C. Further, [0036] of Liu also teaches that figure 2C teaches the characterization of two-dimensional repeating structures for optical metrology modeling, with [0038] teaching FIG. 2C shows an exemplary technique for characterizing the top-view of a two-dimensional repeating structure. Unit cell 330 includes a feature 332, which is an island with a peanut shape viewed from the top. One modeling approach includes approximating the feature 332 with a combination of ellipses and polygons. While Applicant has argues that ellipses and polygons the opposite of a hole shape, it is noted that holes may be of any shape that is required for design optimization of the electronic device formed.
Therefore, the rejections of claim 12 and 20 under 35 USC 103 using the cited prior art of Dziura and Liu using the cited prior art of record is maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to QUOVAUNDA JEFFERSON whose telephone number is (571)272-5051. The examiner can normally be reached M-F 7AM-4PM.
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/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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