Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 1, 3-6, and 8-20 are pending and rejected. Claims 2 and 7 are cancelled. Claims 1, 4, 8, and 14 are amended.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 6/25/2025 has been entered.
Claim Objections
Claim 16 is objected to because of the following informalities: “then” in line 2 should be “than”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 14-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 14, the claim states a method for forming a silicon-carbide layer, where the SiN layer prevents a nucleation delay in the silicon-carbide layer formed after the silicon-nitride layer, and subsequently forming at least one layer over the SiN, where the SiN prevents a delay in a nucleation and a growth of the silicon-carbide layer on the at least one metal in comparison to the at least one dielectric, where the at least one formed layer includes material selected from materials including silicon carbide, silicon carbon nitride, silicon oxycarbonitride, and silicon oxycarbide, the silicon-carbide layer being a spacer layer, making it unclear whether the silicon-carbide layer is considered to include the listed material for the at least one layer. Specifically, it is unclear whether the silicon-carbide layer of the preamble includes materials such as silicon carbon nitride, silicon oxycarbonitride, and silicon oxycarbide such that forming the at least one layer over the silicon nitride will result in forming the claimed silicon-carbide layer. For the purposes of examination, the silicon-carbide layer is considered to include silicon carbide, silicon oxycarbonitride, and silicon oxycarbide. Since the dependent claims do not remedy the clarity of claim 14, they are also rendered indefinite. Appropriate action is required without adding new matter.
Regarding claim 15, the claim recites the limitation "the same chamber as the subsequent silicon oxycarbide deposition" in line 2. There is insufficient antecedent basis for this limitation in the claim. As written, only the at least one metal material and at least one dielectric material is formed in a deposition chamber. Therefore, it is unclear whether only the SiN and SiOC layer are required to be formed in the same chamber or whether they are required to be formed in the same chamber as the at least one metal and at least one dielectric material. For the purposes of examination, either interpretation will meet the limitations of the claim.
Further, in claim 14, the at least one material is not required to be a silicon oxycarbide layer, making it unclear whether claim 15 requires the deposition of silicon oxycarbide or whether when a different material is formed as the at least one layer, the limitations of claim 15 are optional. For the purposes of examination, the claim is being interpreted as though silicon oxycarbide is deposited as the at least one layer.
Appropriate action is required without adding new matter.
Regarding claim 16, the claim requires that the SiN film is formed in a different chamber than the subsequent silicon oxycarbide deposition, but in claim 14, the at least one material is not required to be a silicon oxycarbide layer, making it unclear whether claim 16 requires the deposition of silicon oxycarbide or whether when a different material is formed as the at least one layer, the limitations of claim 16 are optional. For the purposes of examination, the claim is being interpreted as though silicon oxycarbide is deposited as the at least one layer.
Appropriate action is required without adding new matter.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 4-6, and 8-11 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai, US 2020/0365698 A1 in view of Yu, US 6,764,952 B2.
Regarding claims 1 and 8, Tsai teaches forming FinFET devices with source/drain contacts with reduced resistance/capacitance (abstract). They teach that the device is formed on a substrate 101 having first trenches 103, where the substrate is a semiconductor (0010 and Fig. 1A). They teach etching the substrate to form trenches and fins 107 from portions of the substrate that remain unremoved (0016 and Fig. 1). They teach that the trenches are filled with a dielectric material to form the first isolation regions 105 (0019 and Fig. 1A). They teach forming dummy gate dielectrics 109 which comprise materials such as silicon dioxide or silicon oxynitride (0024 and Fig. 1A). They teach forming the dummy gate electrodes 111 which may comprise a conductive material such as Cu, W, Co, Ni, or combinations of these (0025 and Fig. 1A). Once the dummy stacks 115 have been patterned, spacers 113 are blanket deposited over the previously formed structure (0027 and Fig. 1A). They teach forming one or more spacer layers that may comprise SiN, SiOC, and the like (0027). They teach that the one or more spacer layers may be formed from different materials (0027). Therefore, they teach blanket depositing spacer layers over a conductive material (dummy electrode) and a dielectric material (dummy gate dielectric and dielectric isolation regions) so as to concurrently deposit the materials, where the spacer layers can be SiN and/or SiOC, and where the dummy electrode is selected from materials including copper.
They do not teach forming a silicon nitride layer as a first gate spacer and a subsequent silicon oxycarbide layer as the second gate spacer layer.
Yu teaches two sequential treatments within a CVD chamber on a copper layer to clean and passivate the copper surface prior to deposition of a copper diffusion barrier layer or a dielectric layer (abstract). They teach that the process improves film adhesion for a dielectric layer or a copper diffusion barrier layer on the copper surface (abstract). They teach that copper is deposited on a semiconductor device or substrate to form a copper metal layer, where the copper is deposited on a dielectric layer and metallic diffusion barrier (Col. 3, lines 36-43). They teach a first treatment to clean the copper surface and then forming a thin silicon nitride layer, i.e., Si3N4 (abstract, Col. 2, lines 1-12, and Fig. 1-3). They teach that the silicon nitride layer prevents oxidation or contamination of the copper surface and acts as a passivation and glue layer (Col. 2, lines 1-13 and Col. 5, lines 21-31). They teach that after depositing the silicon nitride layer, a silicon nitride (Si3N4), silicon carbide (SiC), or a silicon oxycarbide (SiCxOyH) layer is formed as a copper diffusion barrier layer (Col. 5, line 52 through Col. 6, line 25, Fig. 1, and Fig. 4). They teach that a copper diffusion barrier layer comprising any composition, including oxygen, can be deposited onto the passivated copper surface (Col. 5, lines 62-67). Therefore, Yu teaches depositing a silicon nitride layer over a copper metal surface to prevent oxidation and contamination of the copper surface so as to passivate the surface and act as an adhesion layer for a subsequently deposited SiOC layer.
From the teachings of Yu, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified the process of Tsai to have deposited a first SiN spacer layer followed by a SiOC spacer layer because Tsai teaches depositing spacer layers including one or more of SiN and SiOC, where the spacer layers can be different and where the spacer layers are deposited onto a dummy gate electrode which is formed from metal materials including copper and Yu teaches that such a deposition process prevents oxidation and contamination of a copper surface so as to passivate the surface and act as an adhesion layer for a subsequently deposited SiOC layer such that it will be expected to provide the desired and predictable result of forming desirable spacer layers while also providing the benefit of improved adhesion while preventing oxidation and contamination of the metal surface. Therefore, in the process of Tsai in view of Yu, a silicon nitride layer is formed over a combination of at least one dielectric material and at least one metal material such that the silicon nitride contacts both of at least one dielectric material and the at least on metal material and subsequently, a silicon oxycarbide layer is formed over the silicon nitride layer, where the silicon oxycarbide layer is a spacer layer.
Further, while they do not teach that the silicon nitride layer is used to prevent a delay in a nucleation and growth of the silicon oxycarbide layer on at least one metal material in comparison with a nucleation and growth of the silicon oxycarbide layer on the at least one dielectric material, since they provide the process of claim 1, the process is also expected to inherently result in preventing such a delay. Further, since the silicon nitride layer is deposited on the surfaces and then the SiOC layer is formed as required by claim 1, it is considered to inherently be an initiation-layer so as to produce a substantially uniform silicon-oxycarbide layer over both of that at least one dielectric material and at least one metal material substantially concurrently. According to MPEP 2112.01 I, “Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977)”.
Regarding claims 4 and 9, Tsai in view of Yu suggest the process of claims 1 and 8. Tsai further teaches forming the spacer layers over the fins, which are formed from etching the semiconductor substrate where the substrate is a semiconductor material (0010, 0016, 0023, Fig. 1A, and Fig. 1B). They teach blanket depositing the spacer layer (0027). Therefore, the silicon nitride will directly contact the semiconductor material and be substantially simultaneously formed over the semiconductor material with the formation of the SiN layer over the dielectric and metal material.
Regarding claim 5, Tsai in view of Yu suggest the process of claim 1. Tsai further teaches that the metal material, i.e., dummy electrode, is copper, tungsten, Ti, Co, Ta, etc. (0025). While Yu suggests applying SiN first when the metal is copper, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have also formed the SiN layer first followed by the SiOC layer when using other metals as the dummy gate electrode because Yu teaches that it prevents oxidation and contamination of the copper layer such that it will also be expected to prevent oxidation and contamination of the other metal layers.
Regarding claim 6, Tsai in view of Yu suggest the process of claim 1. Tsai further teaches that the dielectric material, i.e., dummy gate dielectric, is silicon dioxide, zirconium dioxide, lanthanum oxide, hafnium oxide, aluminum oxide, etc. (0024).
Regarding claim 10, Tsai in view of Yu suggest the process of claim 8. Tsai further teaches that the spacer layer is SiOC (0027), such that it is considered to be undoped.
Regarding claim 11, Tsai in view of Yu suggest the process of claim 8. They do not teach a differential thickness between the silicon oxycarbide layer over the dielectric material and the metal material, however, since they provide the process of claim 8, the resulting differential thickness is expected to be within the claimed range. According to MPEP 2112.01 I, “Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977)”.
Claims 14-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai, US 2020/0365698 A1 in view of Yu, US 6,764,952 B2, Chang, US 2018/0174885 A1, and Rajagopalan, US 2006/0046479 A1.
Regarding claim 14, as discussed above Tsai in view of Yu suggest a method for forming a silicon-carbide layer (silicon oxycarbide layer), the method comprising: forming layers on a substrate of at least one metal material and at least one dielectric material; forming silicon nitride over a combination of the at least one metal material and the at least one dielectric material on the substrate such that the silicon nitride contacts both of the at least one dielectric material and the at least one metal material, the forming of the silicon-nitride layer over the combination of the at least one dielectric material and the at least one metal material; and subsequently forming at least one layer over the silicon nitride, the at least one formed layer including materials selected from materials including silicon oxycarbide, the silicon-carbide layer being a spacer laver.
They do not teach forming the metal layer and the dielectric layers in a deposition chamber.
Chang teaches an apparatus including a deposition chamber that is used to perform various steps in the manufacturing of FinFETS or other integrated circuits on wafter (abstract and 0033). They teach that the deposition chamber can be used to perform a conformal deposition process such as ALD used in the manufacturing of FinFETs on the wafers (0033).
Rajagopalan teaches methods for processing a substrate for depositing an adhesion layer between a conductive material and a dielectric layer (abstract). They teach depositing a dual damascene structure in which copper is deposited into interconnects and contacts/vias (0026, 0031-0032, and Fig. 1A-D). They teach depositing the damascene structure by providing a substrate to a processing chamber to deposit various dielectric and metallic layers (0026-0032 and Fig. 1A-D).
From the teachings of Chang and Rajagopalan, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have deposited the metal and dielectric layer in a deposition chamber such as that of Chang because Chang teaches a deposition chamber that can be used to perform various steps in the manufacturing of FinFETs, where the chamber performs deposition and because Rajagopalan teaches that various metallic and dielectric layers can be formed in a deposition chamber such that it will be expected to provide a desirable chamber for forming the layers while not requiring removal of the substrate which could result in exposure to the atmosphere causing potential contamination.
Further, while they do not teach that the silicon nitride layer is used to prevent a delay in a nucleation and growth of the silicon oxycarbide layer on at least one metal material in comparison with a nucleation and growth of the silicon oxycarbide layer on the at least one dielectric material, since they provide the process of claim 14, the process is also expected to inherently result in preventing such a delay. Further, since the silicon nitride layer is deposited on the surfaces and then the SiOC layer is formed as required by claim 1, it is considered to inherently be an initiation-layer. According to MPEP 2112.01 I, “Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977)”.
Regarding claims 15 and 16, Tsai in view of Yu, Chang, and Rajagopalan suggest the process of claim 14. Tsai teaches forming the spacers by methods including PECVD (0027).
Yu teaches providing the silicon nitride layer by a plasma process (Col. 4, line 63 through Col. 5, line 31).
They do not specify whether the plasma is direct or remote.
Rajagopalan teaches performing a silicon nitride deposition process by providing organosilicon compounds to a processing chamber, providing a nitrogen-containing compound to the processing chamber, and an optional inert gas such as helium or nitrogen to the processing chamber and generating plasma (0057-0058). They teach that alternatively, all plasma generation may be performed remotely, with the generated radicals introduced into the processing chamber for plasma treatment of a deposited material or deposition of a material layer (0058). Since they indicate that remote plasma generation is an alternative to the other described plasma process, the other described plasma process is understood to be a direct plasma process. Therefore, Rajagopalan teaches that silicon nitride can be deposited by a direct or remote plasma process.
From the teachings of Rajagopalan, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have deposited the silicon nitride layer by either direct or remote plasma because Rajagopalan teaches that either method is successful in depositing a silicon nitride layer such that it will be expected to provide the silicon nitride layer as desired.
As to the chambers, Yu teaches that the semiconductor processing steps are performed in a CVD chamber or sequentially in one or more of these types of CVD chambers (Col. 3, lines 19-35). They teach that one or more of the processing steps may be performed in one CVD chamber and some may be performed in a another , where two CVD chambers may be of the same type or different types (Col. 3, lines 19-35). They teach depositing the silicon oxycarbide layer using plasma (Col. 6, lines 16-25).
Chang teaches using the deposition chamber for various steps in the manufacturing of FinFETs (0033).
Rajagopalan also teaches depositing silicon carbide using plasma (0104).
From this, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention that the silicon nitride layer can be deposited in the same chamber as the subsequent silicon oxycarbide layer using a direct-plasma operation or in a different chamber than the silicon oxycarbide when using a remote plasma operation because Yu teaches that such process steps can be done in the same or different chambers and Chang teaches that a single chamber can be used to perform various steps in forming a FinFET.
Regarding claims 17 and 18, Tsai in view of Yu, Chang, and Rajagopalan suggest the process of claim 14.
Tsai teaches that the spacers 113 may be formed to have a thickness of between about 5 angstroms and about 500 angstroms (about 0.5 to 50 nm), where when using two layers, the layers are together indicated as being spacer 113, suggesting that when using two layers, the total thickness of the layers is about 0.5 to 50 nm (0028 and Fig. 1B).
Yu further teaches that the silicon nitride layer has a thickness of approximately 30 to 200 A, i.e., 3-20 nm (Col. 4, lines 27-40).
From this, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the SiN spacer layer to have a thickness in the range of about 3-20 nm and the SiOC spacer to have a thickness of 30 nm or less because Yu teaches that such a SiN thickness is desirable for an adhesion/passivating layer on a metal surface and the thickness is within the range desired by Tsai such that it will be expected to provide a desirable spacer thickness and adhesion/passivating layer thickness. Therefore, the thickness of the silicon nitride layer is considered to overlap the ranges of claims 17 and 18, where about 20 nm is considered to overlap the range of claim 17 at the end point. According to MPEP 2144.05, “in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists.” In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976).
Regarding claim 20, Tsai in view of Yu, Chang, and Rajagopalan suggest the process of claim 14. Tsai further teaches that the spacer layer is SiOC (0027), therefore, the silicon carbide layer is understood to be undoped because there is no indication of doping.
Claims 3, 12, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Tsai in view of Yu as applied to claims 1 and 8 above, and further in view of Chen, US 2020/0035804 A1.
Regarding claims 3 and 13, Tsai in view of Yu suggest the process of claims 1 and 8.
Yu further teaches that the silicon oxycarbide layer of the copper diffusion barrier has the formula SiCxOyH (Col. 6, lines 16-25 and Fig. 4), such that the silicon carbide layer will further comprise hydrogen and be in the form of a silicon oxycarbide layer.
They do not teach that the SiOC spacer layer includes hydrogen.
Chen teaches a semiconductor structure that includes a semiconductor substrate, a gate structure, a first gate spacer, an interlayer dielectric layer, a contact stop layer, and an air gap (abstract). They teach blanket depositing gate spacer layer GS1 over a dummy gate structure DG, a fin 250, and an isolation dielectric layer 260 (0023 and Fig. 10). They teach forming a gate spacer layer GSL2 over gate spacer GSL1 and forming gate spacer layer GSL3 on gate spacer layer GSL2 (0023 and Fig. 10). They teach conformally forming the layers on top of one another (0023 and Fig. 10). They teach that the gate spacer layers independently include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, hydrogen doped silicon oxycarbide, etc. (0023). They teach that the gate spacer layers may be formed of different materials (0023). They teach that the dummy gate structure DG is formed of a conductive material such as Co, Ru, Al, etc. (0021). They teach that the isolation dielectric layer 260 is a material such as silicon oxide, silicon nitride, silicon oxynitride, etc. (0017). They teach that the gate oxide layer 270 (over which the gate spacer layers are formed) is a material such as hafnium oxide, zirconium oxide, tantalum pentoxide, etc. (0020 and Fig. 10). Therefore, Chen teaches forming spacer layers formed from materials including silicon nitride, silicon oxycarbide, and hydrogen doped silicon oxycarbide, where the gate spacer layers are formed over both of at least one dielectric material and at least one metal material substantially concurrently (since the layers are blanket deposited over the materials).
From the teachings of Chen and Yu, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the SiOC spacer layer so that it includes hydrogen because Chen teaches that such a layer is desirable in a spacer and Yu teaches that SiN layer also works with a SiOCH layer such that it will be expected to provide a desirable spacer layer while providing desirable adhesion and passivation.
Regarding claim 12, Tsai in view of Yu suggest the process of claim 8. Tsai teaches forming the spacer layers over dielectric isolation regions and the dummy gate dielectric (0023 and Fig. 1A). They teach that the dummy gate dielectric includes materials such as silicon dioxide, SiON, hafnia, zirconia, etc. (0024). They teach that the dummy gate electrodes may comprise W, Al, Cu, AlCu, W, Ti, AlN, etc., and combinations thereof (0025). Therefore, the spacer layers can be formed over a combination of metals when a combination is used to form the dummy gate electrode.
They do not teach forming the spacers over a combination of dielectric materials.
Chen teaches that the isolation dielectric layer 260 is a material such as silicon oxide, silicon nitride, silicon oxynitride, etc. (0017).
From the teachings of Chen and Tsai, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the isolation regions from silicon oxide, silicon nitride, or silicon oxynitride, and the dummy gate dielectric from hafnia or zirconia so as to provide different dielectric materials because Chen and Tsai indicate that such materials are desirable for the various layers. Therefore, the SiN layer will be formed over a combination of different dielectric materials in the isolation region and dummy gate dielectric and different metals providing the dummy gate electrode.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Tsai in view of Yu, Chang, and Rajagopalan as applied to claim 14 above, and further in view of Chen, US 2020/0035804 A1.
Regarding claim 19, Tsai in view of Yu, Chang, and Rajagopalan suggest the process of claim 14.
They do not teach that the SiN layer is formed to have a thickness greater than about 200 nm. As noted above Yu suggests forming the SiN adhesion/passivation layer to have a thickness of approximately 30 to 200 A, i.e., 3-20 nm (Col. 4, lines 27-40). Tsai teaches that the spacers 113 may be formed to have a thickness of between about 5 angstroms and about 500 angstroms (about 0.5 to 50 nm), where when using two layers, the layers are together indicated as being spacer 113, suggesting that when using two layers, the total thickness of the layers is about 0.5 to 50 nm (0028 and Fig. 1B).
Chen teaches that gate spacer layer GSL1, gate spacer layer GSL2, and gate spacer layer GSL3 respectively have a thickness range from about 5 angstrom to about 1000 angstroms, i.e., about 0.5 nm to about 100 nm (0023).
From the teachings of Chen, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified the process of Tsai in view of Yu, Chang, and Rajagopalan to have formed the SiN layer to have ta thickness in the range of about 0.5 nm to about 100 nm because Chen teaches that when forming multiple spacer layers formed from the materials taught by Tsai such a thickness is suitable for each layer. Alternatively, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have optimized the thickness of the SiN film to be within the claimed range from the overlapping thickness ranges of Tsai and Chen because Tsai indicates that the upper limit to the thickness of the spacer layers is 50 nm, where more than one can be used, suggesting that the SiN thickness should be less than 50 nm and Chen teaches that a single spacer layer can have a thickness of 0.5 to 100 nm such that it will be expected to provide a suitable range from which to optimize the thickness of the spacer layers. Therefore, the thickness will overlap the claimed range or be optimized to be within the claimed range. According to MPEP 2144.05, “in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists.” According to MPEP 2144.05 II A, “Generally, differences in concentration or temperature will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such concentration or temperature is critical. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Response to Arguments
Applicant’s arguments dated 6/25/2025 have been fully considered.
Regarding Applicant’s request for an interview, due to time constraints, an interview was not able to be held prior to mailing the office action. Applicant is invited to call the Examiner to set up an interview of to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
In light of the amendments to the claims, the rejection has been modified as indicated above, where Tsai and Chen indicate that it is known to use a combination of SiN and SiOC spacer layers, where Yu suggest providing the SiN layer first to passivate the metal surface and to improve adhesion.
Conclusion
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/CHRISTINA D MCCLURE/Examiner, Art Unit 1718