DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendments filed 9/30/2025 are noted.
Claims 1-11 remain pending; claims 12-16 are newly added.
Claims 1-16 have been fully considered in examination.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/30/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 14-16 are objected to because of the following informalities:
Claims 14-16 currently read “The semiconductor device according to claim…” but should read “The method for manufacturing the semiconductor device according to claim…”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 6-7 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over US 20120187395 A1 (of record), hereinafter “Koezuka” in view of US 20140027767 A1 (of record), hereinafter “Suzawa”.
Regarding claim 6, Koezuka teaches a method for manufacturing a semiconductor device (Figs. 2A-2E; [0040]), comprising:
a step of forming a first metal oxide film 104 ([0055]; Fig. 2A);
a step of performing heat treatment on the first metal oxide film 104 at higher than or equal to 500 0C and lower than 600 °C (550°C [0085]);
a step of forming a first conductive film 110 [0112] over and in contact with (see Fig. 2D) the first metal oxide film 104 (see Fig. 2D);
a step of processing the first conductive film 110 and the first metal oxide film 104 into an island shape by a lithography method [0116,0117] (see Fig. 2E),
a step of forming a second insulating film 112 [0131] (Fig. 3A) and a second conductive film 114 [0131] (Fig. 3B) inside an opening (opening in the first conductive film 110 (see Fig. 2E; [0116]),
wherein the first metal oxide film 104 is formed by a sputtering method [0083] using an In-M-Zn oxide target [0083], where M is any one or more of gallium, aluminum, yttrium, and tin (Ga [0083]; see further [0079] for other target materials), and
wherein the first conductive film 110 is formed by a sputtering method [0113] using a tantalum target [0113] in an atmosphere containing nitrogen (where TaN is formed by the sputtering method of [0113]).
While Koezuka does teach an opening in the first conductive film 110, Koezuka does not teach a step of forming a first insulating film over the first conductive film 110, and processing the first insulating film to form an opening (including the opening in 110).
Suzawa teaches a method for manufacturing a semiconductor device (Fig. 28B; see also Figs. 3A-3F; [0227]) comprising a step of forming an oxide semiconductor layer 307 [0093,0143], and a step of forming a first insulating film 315 [0093] over a first conductive film 308 [0229] (Fig. 3A) wherein the first insulating film 315 comprises an opening (see Fig. 3B; an opening formed to include an opening in the first conductive film 308; [0233]); and
a step of forming a second insulating layer 317 [0093] (Fig. 3F) and a second conductive film 319 [0093] inside the opening (Fig. 3F).
It would have been obvious to one in ordinary skill in the art before the effective filing date of the claimed invention to include the first insulating film, taught by Suzawa, in the method and device of Koezuka in order to reduce the parasitic capacitance between the second conductive film 114 and the first conductive film 110, as taught by Suzawa [0095].
Regarding claim 7, Koezuka anticipates a method for manufacturing a semiconductor device (Figs. 2A-2E; [0040]), comprising:
a step of forming a first metal oxide film 104 ([0055]; Fig. 2A);
a step of forming a second metal oxide film 106 [0089] over and in contact with (see Fig. 2B) the first metal oxide film 104 (see Fig. 2B);
a step of performing heat treatment on the first metal oxide film 104 and the second metal oxide film 106 at higher than or equal to 500 °C and lower than 600 °C (550 °C [0097]);
a step of forming a first conductive film 110 [0112] over and in contact with (see Fig. 2D) the second metal oxide film 106 (see Fig. 2D);
a step of processing the first conductive film 110, the second metal oxide film 106, and the first metal oxide film 104 into an island shape by a lithography method [0116,0117] (see Fig. 2E),
a step of forming a second insulating film 112 [0131] (Fig. 3A) and a second conductive film 114 [0131] (Fig. 3B) inside an opening (opening in the first conductive film 110 (see Fig. 2E; [0116]),
wherein the first metal oxide film 104 is formed by a sputtering method [0083] using an In-M-Zn oxide target [0083], where M is any one or more of gallium, aluminum, yttrium, and tin (Ga [0083]; see further [0079] for other target materials),
wherein the second metal oxide film 106 is formed by a sputtering method [0094] using an In-M- Zn oxide target [0094], where M is any one or more of gallium, aluminum, yttrium, and tin (Ga [0094]),
wherein the conductive film 110 is formed by a sputtering method [0113] using a tantalum target [0113] in an atmosphere containing nitrogen (where TaN is formed by the sputtering method of [0113]).
While Koezuka does teach an opening in the first conductive film 110, Koezuka does not teach a step of forming a first insulating film over the first conductive film 110, and processing the first insulating film to form an opening (including the opening in 110).
Suzawa teaches a method for manufacturing a semiconductor device (Fig. 28B; see also Figs. 3A-3F; [0227]) comprising a step of forming an oxide semiconductor layer 307 [0093,0143], and a step of forming a first insulating film 315 [0093] over a first conductive film 308 [0229] (Fig. 3A) wherein the first insulating film 315 comprises an opening (see Fig. 3B; an opening formed to include an opening in the first conductive film 308; [0233]); and
a step of forming a second insulating layer 317 [0093] (Fig. 3F) and a second conductive film 319 [0093] inside the opening (Fig. 3F).
It would have been obvious to one in ordinary skill in the art before the effective filing date of the claimed invention to include the first insulating film, taught by Suzawa, in the method and device of Koezuka in order to reduce the parasitic capacitance between the second conductive film 114 and the first conductive film 110, as taught by Suzawa [0095].
Regarding claim 14, Koezuka in view of Suzawa teaches the method for manufacturing the semiconductor device according to claim 6, and Koezuka further teaches wherein the first metal oxide film 104 comprises a non-single-crystal structure (see [0135]).
Regarding claim 15, Koezuka in view of Suzawa teaches the method for manufacturing the semiconductor device according to claim 7, and Koezuka further teaches wherein the first metal oxide film 104, and the second metal oxide film 106 comprise a non-single-crystal structure (see [0135]).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Koezuka in view of Suzawa as applied to claim 7 above, and further in view of US 20130075717 A1, hereafter “Tsang”.
Regarding claim 16, Koezuka in view of Suzawa teaches the method of manufacturing the semiconductor device according to claim 7, but does not explicitly teach wherein an atomic ratio of the M to In of the second metal oxide film 106 is higher than an atomic ratio of the M to In of the first metal oxide film 104.
Tsang teaches a semiconductor device comprising a metal oxide film, wherein when the ratio of M to In increases, the band gap of the metal oxide film increases (see [0016]).
Given Koezuka teaches the second metal oxide film 106 has a greater band gap than the first metal oxide film 104 [0092], it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the atomic ratio of M to In of the second metal oxide film 106 to be higher than the atomic ratio of M to In of the first metal oxide film 104 in the normal course of routine experimentation and optimization in order to tune the band gap difference between the metal oxide layers, as required by Koezuka (see MPEP 2144.05 (II)).
Allowable Subject Matter
Claims 1-5 and 8-13 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claims 1-2, the prior art of record neither anticipates nor renders obvious the claim limitation “wherein the first crystal has (111) orientation with respect to a surface of the first/[second] oxide”, in combination with the other limitations required by claims 1 and 2, respectively.
Claims 3-5 and 8-13 are allowable due to their dependence on claims 1 and 2, respectively.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments, filed 9/30/2025, with respect to claims 1 and 2 have been fully considered and are persuasive. The rejection of claims 1-2 and their respective dependent claims have been withdrawn (see sect. 13 above).
Applicant's arguments filed 9/30/2025 with regards to claims 6 and 7 have been fully considered but they are not persuasive.
Regarding claims 6 and 7, the applicant alleges that independent claims 6 and 7 are patentable for the same reasons discussed regarding claims 1 and 2 (see pg. 10 of Remarks). In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., the lattice orientations) are not recited in the rejected claims 6 and 7. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Accordingly, the examiner does not find the arguments persuasive and the rejection is maintained.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20140239293 A1 teaches a semiconductor device similar to the claimed invention, with similar materials and layers and further motivates having differing M to In ratios in oxide layers.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Bruce Smith III whose telephone number is (571)272-5570. The examiner can normally be reached Monday - Friday; 8 am - 5 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571)272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRUCE R. SMITH/Examiner, Art Unit 2892
/LEX H MALSAWMA/Primary Examiner, Art Unit 2892