DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 21-39 have been considered but are moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 21-39 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1, and similarly in claim 39, recites the feature of “an opening hole formed in the pixel-defining film and in the emission layer, the opening hole exposing part of the electrode pattern.” Applicant argues on page 10 that the instant application supports the claim amendments by reciting a portion of paragraph 188 of the originally filed specification. Examiner takes the position that the specification as filed fails to provide support for the newly added limitations. Fig. 10 is the only figure showing the first type of pixel, where HLD extends through PDL but does not extend through EML. Further, paragraph 188 states “EML on the entire surface of the pixel PX,” however, pixel PX is not defined or shown explicitly in the figures, therefore explicit or implicit support whether HLD is formed through the emission layer is lacking. Further, the figures lack support for such an amendment.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 21-39 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shibusawa (US PGPub 2006/0082284) in view of Myung et al. (KR2014/0086639; hereinafter “Myung”), and alternatively, further in view of Matsumoto et al. (US PGPub 2017/0141180; hereinafter “Matsumoto”).
Re claim 21: Shibusawa teaches (e.g. figs. 1-7 and labeled fig. 7 below) a display device (display panel DP; e.g. paragraph 21) having a display area (area of PE exposed by SI in the display area AA; e.g. paragraph 21; hereinafter “DA”) and a non-display area (area outside of DA; hereinafter “NDA”) extending around the display area (DA), the display device (DP) comprising: a plurality of pixels (pixels PX; e.g. paragraph 21) in the display area (DA); a first voltage line (power supply line PL2 that spans display area DA; e.g. paragraph 26) in the display area (DA); and a twenty-first voltage line (power supply line PL1 that is provided peripherally in the non-display area NDA; e.g. paragraph 26) in the non-display area (NDA), wherein: each of the pixels (PX) comprises an electrode pattern (intermediate electrode IE; e.g. paragraph 58) connected to the first voltage line (IE is connected to common voltage on PL2), a pixel-defining film (partition insulating layer SI; e.g. paragraph 40) on the electrode pattern (IE), an emission layer (organic emitting layer ORG; e.g. paragraph 42) on the pixel-defining film (SI), and a common electrode (common electrode CE; e.g. paragraph 43) on the emission layer (ORG), the pixels (PX) comprise first-type pixels (pixel labeled “PX1” below in labeled fig. 7) in which the common electrode (CE) and the electrode pattern (IE) are connected through an opening hole (TH2) formed in the pixel-defining film (SI) and in the emission layer (opening between adjacent ORG of adjacent pixels), the opening hole (TH2) exposing part of the electrode pattern (IE) and second-type pixels (pixel labeled “PX2” below in labeled fig. 7) in which the opening hole (TH2) is not formed and the common electrode (CE) and the electrode pattern (IE) are not connected (CE and IE are not connected through an opening hole TH2 in the region of PX2), and the first-type pixels (PX1) and the second-type pixels (PX2) are adjacent to each other (PX1 and PX2 are adjacent to each other), the electrode pattern (IE) is connected to the first voltage line (PL2) via a contact hole (TH1) formed in an insulating layer (I2) which is between the electrode pattern (IE) and the first voltage line (PL2).
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Shibusawa is silent as to explicitly teaching at least a portion of the common electrode in the first-type pixel is inside the contact hole.
Myung teaches (e.g. fig. 8m) at least a portion of the common electrode (208) in the first-type pixel (PX1 of Shibusawa) is inside the contact hole (TH1 of Shibusawa which corresponds to hole in 215d which is filled by 238 and 208; e.g. paragraphs 164 and 167 of the English translation of Myung).
It would have been obvious to one ordinary skill in the art, absent unexpected results, at the time of effective filing to use the common electrode contact hole overlap with the opening hole for the electrode pattern as taught by Myung in the device of Shibusawa in order to have the predictable result increasing efficiency by ensuring a low resistance contact is created between the common electrode and common electrode pad.
Alternatively, it may be considered that Shibusawa in view of Myung is silent as to explicitly teaching the opening hole formed in the pixel-defining film and in the emission layer, the opening hole exposing part of the electrode pattern.
Matsumoto teaches (e.g. fig. 5) the opening hole (contact hole CH; e.g. paragraph 41) formed in the pixel-defining film (bank 23; e.g. paragraph 41) and in the emission layer (organic film 24; e.g. paragraph 41), the opening hole (CH) exposing part of the electrode pattern (19).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the opening hole formed through the pixel defining film and the emission layer as taught by Matsumoto in the device of Shibusawa in view of Myung in order to have the predictable result of simplifying manufacture by reducing steps, such as skipping the step of patterning the organic emission film to regions only proximate to the pixel electrode.
Re claim 22: Shibusawa teaches the display device of claim 21, further comprising a sub-electrode pattern (IE of PX3; e.g. paragraph 58) in the non-display area (NDA) and connected to the twenty-first voltage line (PL1), wherein the pixels further comprise third-type pixels (pixel labeled “PX3” above in labeled fig. 7) in which the common electrode (CE) is connected to the sub-electrode pattern (IE of PX3).
Re claim 23: Shibusawa teaches the display device of claim 22, wherein the third-type pixels (PX3) are spaced apart from the first-type pixels (PX1), and wherein at least one of the second-type pixels (PX2) is between the first-type pixels (PX1) and the third-type pixels (PX3).
Re claim 24: Shibusawa teaches the display device of claim 23, wherein a plurality of the first-type pixels (PX1) are spaced apart from one another (PX1, PX2, and PX3 repeat, therefore there will be another PX1 column which has a PX2 provided between two PX1s), and wherein the second-type pixels (PX2) are between the plurality of spaced apart first-type pixels (PX1).
Re claim 25: Shibusawa teaches the display device of claim 23, wherein a plurality of the third-type pixels (PX3) are spaced apart from one another (PX1, PX2, and PX3 repeat, therefore there will be another PX3 column which has a PX2 provided between two PX3s), and wherein the third-type pixels (PX3) are between the plurality of spaced apart third-type pixels (PX3).
Re claim 26: Shibusawa teaches the display device of claim 22, wherein the third-type pixels (PX3) are on at least one side of the display area (DA), and wherein the first-type pixels (PX1) are on the inside of the display area (DA) and spaced apart from the third-type pixels (PX3).
Re claim 27: Shibusawa teaches the display device of claim 26, wherein at least one of the first- type pixels (PX1, PX2, and PX3 repeat, therefore there will be another PX3 column which has a PX1 provided between two PX3s) is between the third-type pixels (PX3).
Re claim 28: Shibusawa teaches the display device of claim 22, wherein the display area (DA) has a plurality of pixel columns in which the pixels are arranged along a first direction (up and down direction of fig. 7; hereinafter “1D”), and wherein the pixel columns have a first pixel column (column of PX1 pixels; hereinafter “1PC”) comprising at least one of the first-type pixels (PX1) and a second pixel column (column of PX2 pixels closer to PX1; hereinafter “2PC”) comprising the second-type pixels (PX2).
Re claim 29: Shibusawa teaches the display device of claim 28, wherein the first-type pixels (PX1) and the third-type pixels (PX3) are not in the second pixel column (2PC).
Re claim 30: Shibusawa teaches the display device of claim 28, wherein the pixel columns also have a third pixel column (column of PX1 and PX3 pixels; hereinafter “3PC”) comprising at least one of the first-type pixels (PX1) and at least one of the third-type pixels (PX3).
Re claim 31: Shibusawa teaches the display device of claim 30, wherein the third pixel column (3PC) further comprises at least one of the second-type pixels (2PX) between the at least one of the first-type pixels (1PX) and the at least one of the third-type pixels (3PX).
Re claim 32: Shibusawa teaches the display device of claim 31, wherein the pixel columns also have a fourth pixel column (column of PX2 pixels closer to PX3; hereinafter “4PC”) comprising at least one of the second-type pixels (2PX) between the first-type pixels (PX1), between the third-type pixels (PX3), or between the first-type pixels (PX1) and the third-type pixels (PX3), and wherein a number of second-type pixels (PX2) between the first-type pixels (PX1) and the third-type pixels (PX3) in the third pixel column (3PC) differs from a number of the second-type pixels (PX2) between the first-type pixels (PX1) and the third-type pixels (PX3) in the fourth pixel column (4PC).
Re claim 33: Shibusawa teaches the display device of claim 28, wherein the display area (DA) has a plurality of pixel rows in which the pixels are arranged in a second direction (left-right direction of fig. 7; hereinafter ”2D”) intersecting the first direction (1D), and wherein the pixel rows have a first pixel row (row with labeled PX1, PX2, and PX3; hereinafter “1PR”) comprising at least one of the first-type pixels (PX1) and a second pixel row (row below 1PR; hereinafter “2PR”) comprising at least one of the second-type pixels (PX2).
Re claim 34: Shibusawa teaches the display device of claim 33, wherein the first pixel row (1PR) further comprises at least one of the third-type pixels (PX3) and at least one of the second-type pixels (PX2) between the at least one of the third-type pixels (PX3) and the at least one of the first-type pixels (PX1).
Re claim 35: Shibusawa teaches the display device of claim 22, wherein a first-type pixel area (area of pixel with labeled PX1, PX2, PX2, and PX3; hereinafter “1PA”) where the first-type pixels (PX1) are arranged is defined in the display area (DA), and wherein at least one side of the first-type pixel area (1PA) is spaced apart from the non- display area (NDA).
Re claim 36: Shibusawa teaches the display device of claim 35, wherein a size of the first-type pixel area (1PA) is smaller than a size of the display area (DA).
Re claim 37: Shibusawa teaches the display device of claim 21, wherein each of the pixels (PX) further comprises at least one pixel electrode (PE) in the same layer as, but spaced apart from, the electrode pattern (EP), and wherein the emission layer (ORG) is between the pixel-defining film (SI) and the common electrode (CE).
Re claim 38: Shibusawa teaches the display device of claim 37, wherein the pixel-defining film (SI) has an opening (opening in SI; hereinafter “O”) exposing part of the pixel electrode (PE), and wherein in the opening (O), the emission layer (ORG) is between the common electrode (CE) and the pixel electrode (PE), but not on part of the electrode pattern (EP) exposed by the opening hole (TH2).
Re claim 39: Shibusawa teaches (e.g. figs. 1-7 and labeled fig. 7 above) a display device (display panel DP; e.g. paragraph 21) having a display area (area of PE exposed by SI in the display area AA; e.g. paragraph 21; hereinafter “DA”) and a non-display area (area outside of DA; hereinafter “NDA”), the display device (DP) comprising: a data conductive layer comprising a first voltage line (power supply line PL2 connected to common electrode CE spans display area DA; e.g. paragraph 43) in the display area (DA) and a twenty-first voltage line (power supply line PL1 that is provided peripherally in the non-display area NDA; e.g. paragraph 26) in the non-display area (NDA); a passivation film (bottom half of 12; hereinafter “PSF”) on the data conductive layer and covering the first (PL2) and twenty-first (PL1) voltage lines; a planarization film (top half of 12; hereinafter “PNF”) on the passivation film (PSF); a pixel electrode layer (the layer of pixel electrode PE and intermediate electrode IE; e.g. paragraph 58) on the planarization film (PNF) and comprising: an electrode pattern (intermediate electrode IE; e.g. paragraph 58) in the display area (DA) and connected to the first voltage line (PL2); and a sub-electrode pattern (PE under SI) in the non-display area (NDA) and connected to the twenty-first voltage line (PL1); a pixel-defining film (partition insulating layer SI; e.g. paragraph 40) on the planarization film (PNF) and the electrode pattern (IE); an emission layer (organic emitting layer ORG; e.g. paragraph 42) on the pixel-defining film (SI); and a common electrode (common electrode CE; e.g. paragraph 43) on the emission layer (ORG) and connected to the sub-electrode pattern (PE), wherein the electrode pattern (IE) comprises a first electrode pattern (bottom part of IE) not connected to the common electrode (CE) and a second electrode pattern (upper part of IE) connected to the common electrode (CE); wherein the pixel-defining film (SI) and the emission layer (opening between adjacent ORG of adjacent pixels) has an opening hole (TH2) exposing part of the second electrode pattern (upper part of IE), wherein the second electrode pattern (upper part of IE) is connected to the common electrode (CE) through the opening hole (TH2), wherein the second electrode pattern (upper part of IE) is connected to the first voltage line (PL2) via a contact hole (TH1) formed in the passivation film (PSF) and the planarization film (PNF).
Shibusawa is silent as to explicitly teaching wherein at least a portion of the common electrode overlapping the first electrode pattern is inside the contact hole.
Myung teaches (e.g. fig. 8m) wherein at least a portion of the common electrode (208) overlapping the first electrode pattern (upper part of IE of Shibusawa which corresponds to 238 of Myung) is inside the contact hole (TH1 of Shibusawa which corresponds to hole in 215d which is filled by 238 and 208; e.g. paragraphs 164 and 167 of the English translation of Myung).
It would have been obvious to one ordinary skill in the art, absent unexpected results, at the time of effective filing to use the common electrode contact hole overlap with the opening hole for the electrode pattern as taught by Myung in the device of Shibusawa in order to have the predictable result increasing efficiency by ensuring a low resistance contact is created between the common electrode and common electrode pad.
Alternatively, it may be considered that Shibusawa in view of Myung is silent as to explicitly teaching the pixel-defining film (SI) and the emission layer (opening between adjacent ORG of adjacent pixels) has an opening hole (TH2) exposing part of the second electrode pattern (upper part of IE).
Matsumoto teaches (e.g. fig. 5) the pixel-defining film (bank 23; e.g. paragraph 41) and the emission layer (organic film 24; e.g. paragraph 41) has an opening hole (contact hole CH; e.g. paragraph 41) exposing part of the second electrode pattern (19).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the opening hole formed through the pixel defining film and the emission layer as taught by Matsumoto in the device of Shibusawa in view of Myung in order to have the predictable result of simplifying manufacture by reducing steps, such as skipping the step of patterning the organic emission film to regions only proximate to the pixel electrode.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898