Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
Claim(s) 1, 2, 28, 29, 35, and 39 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US Patent No. 9613852) in further view of Leavy (PGPub No. 20060024962) and Schneegans (PGPub No. 20130026633).
Regarding claim 1, Lin teaches a method, comprising: forming an opening, having tapered walls that create a single slope (Fig. 4; 116), through a first dielectric layer (Id.; 114), through an etch stop layer (Id.; 202), through a dielectric capping layer (Id.; 112), and to a top surface of a metal capping layer in a second dielectric layer of a semiconductor device (Fig. 7; 302, 104).
Lin fails to teach filling a first portion of the opening with a first part of an interconnect structure, wherein the first part of the interconnect structure resides directly on the conductive structure metal capping layer; performing an annealing operation on the first part of the interconnect structure to remove defects from the first part of the interconnect structure, wherein a top surface of the first part of the interconnect structure is convex after performing the annealing operation; and filling a remaining portion of the opening with a second part of the interconnect structure after performing the annealing operation.
Leavy teaches filling a first portion of the opening with a first part of an interconnect structure, wherein the first part of the interconnect structure resides directly on the conductive structure metal capping layer (Fig. 3F and [0040]; 350); performing an annealing operation on the first part of the interconnect structure to remove defects from the first part of the interconnect structure ([0042]); and filling a remaining portion of the opening with a second part of the interconnect structure after performing the annealing operation (Fig. 3G and [0043]; 352). Thus, it would have been obvious to a person of ordinary skill in the art (POSITA) prior to the filing date of the claimed invention to combine the teachings of Lin and Leavy, such that the opening is filled with a first part of an interconnect structure, said part is then annealed, and finally the opening is filled with a second part of an interconnect structure in order to create a multi-level interconnect network via a damascene process that improves grain growth while mitigating formation of undesirable voiding regions and reducing resistance of the formed interconnect/conductive feature.
Lin et al. fails to explicitly teach wherein a top surface of the first part of the interconnect structure is convex after performing the annealing operation. However, one of ordinary skill in the art could consider portions of the first layer of copper 350 as shown in Figs. 3F-3H of Leavy, specifically the upward surfaces on the left and right edges, to be convex in shape.
Schneegans teaches wherein a top surface of the first part of the interconnect structure is convex after performing the annealing operation ([0023] points to performing an annealing process on a multilayer metallization 132 (interconnect structure), such that a final wafer bow if produced e.g. tensile (concave), no-bow or compressive (convex).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Lin et al. and Schneegans, such that the first part of the interconnect structure is given a convex shape as a result of the annealing process in order to minimize stress concentration and increase the structural integrity of the interconnect structure as a whole.
Regarding claim 2, Leavy teaches performing another annealing operation on the semiconductor device to remove defects from the second part of the interconnect structure ([0043] points to the second layer of copper 352 (second part) being annealed. Fig. 4 further points to a repeatable sequence where each conductive layer formed (first part; second) is individually annealed); and performing a chemical mechanical planarization (CMP) operation on the second part of the interconnect structure (Fig. 4 and [0016] point to performing a final planarization operation 414, such as chemical mechanical planarization (CMP), after depositing the conductive layers.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Lin et al. and Leavy, such that another annealing operation is performed on the semiconductor device followed by a CMP operation on the second part of the interconnect structure in order to further improve grain growth and remove excess conductive material, respectively.
Regarding claim 28, Lin teaches a method, comprising: forming an opening, having tapered walls that create a single slope (ig. 4; 116), through a first dielectric layer (Id.; 114), through an etch stop layer (Id.; 202), through a dielectric capping layer (Id.; 112) and to top surface of a conductive structure metal capping layer in a second dielectric layer of a semiconductor device (Fig. 7; 302, 104); wherein the first portion of the opening has tapered sidewalls; and wherein the second portion of the opening has tapered sidewalls (Fig. 4; 116).
Lin fails to teach filling a first portion of the opening with a first part of an interconnect structure over the metal capping layer; performing an annealing operation on the semiconductor device to remove defects from the first part of the interconnect structure; and filling a second portion of the opening with a second part of the interconnect structure after performing the annealing operation.
Leavy teaches filling a first portion of the opening with a first part of an interconnect structure over the metal capping layer (Fig. 3F and [0040]; 350); performing an annealing operation on the semiconductor device to remove defects from the first part of the interconnect structure ([0042]); and filling a second portion of the opening with a second part of the interconnect structure after performing the annealing operation (Fig. 3G and [0043]; 352). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Lin and Leavy, such that the opening is filled with a first part of an interconnect structure, said part is then annealed, and finally the opening is filled with a second part of an interconnect structure in order to create a multi-level interconnect network via a damascene process that improves grain growth while mitigating formation of undesirable voiding regions and reducing resistance of the formed interconnect/conductive feature.
Regarding claim 29, Schneegans teaches wherein a top surface of the first part of the interconnect structure is convex after the defects are removed from the first part of the interconnect structure ([0023] points to performing an annealing process (removing defects) on a multilayer metallization 132 (interconnect structure), such that a final wafer bow if produced e.g. tensile (concave), no-bow or compressive (convex).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Lin et al. and Schneegans, such that the first part of the interconnect structure is given a convex shape after removing defects from said part in order to minimize stress concentration and increase the structural integrity of the interconnect structure as a whole.
Regarding claim 35, Schneegans teaches wherein at least one of: the top surface of the first part of the interconnect structure is convex such that the top surface of the first part of the interconnect structure is curved away from a bottom surface of the interconnect structure, or the first part of the interconnect structure is in direct contact with a top surface of the metal capping layer ([0023] points to performing an annealing process on a multilayer metallization 132 (interconnect structure), such that a final wafer bow if produced e.g. tensile (concave), no-bow or compressive (convex).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Lin et al. and Schneegans, such that at least the first part of the interconnect structure is given a convex shape after removing defects from said part in order to minimize stress concentration and increase the structural integrity of the interconnect structure as a whole.
Regarding claim 39, Lin teaches wherein the opening further extends through a dielectric capping layer (Fig. 7; 116), wherein dielectric capping layer (Id.; 112) resides on the metal capping layer (Id.; 302) and sidewall spacers, wherein the sidewall spacers surround the metal capping layer and a portion of the dielectric capping layer, and wherein one of the sidewall spacers is in contact with the metal capping layer is in contact with the second dielectric layer (Id.; 108).
Claims 3, 4, and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. in further view of Paulson (US Patent No. 4392992 A) and Sasaki (US Patent No. 9748104 B2).
Regarding claim 3, Paulson teaches wherein performing the annealing operation comprises: performing the annealing operation using: a combination of gases including nitrogen (N2), helium (He), and argon (Ar) (Col.5, lines 24-27), and a temperature range of approximately 200 degrees Celsius to approximately 450 degrees Celsius (Col. 3, lines 5-7. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to apply an annealing process to the structure taught by Lin et al. according to the teachings of Paulson, where only select gases and/or mixtures of them are used at specific temperatures in order to properly remove any defects and ensure the overall quality and functionality of the interconnect structure.
Paulson fails to teach a vacuum pressure range of approximately 0.5 Tor to approximately 10 Tor.
Sasaki teaches a vacuum pressure range of approximately 0.5 Tor to approximately 10 Tor (Col. 18, lines 41-42. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to apply an annealing process to the structure taught by Lin et al. according to the teachings of Sasaki, where the process is conducted only within a select pressure range to ensure the removal of defects and the overall quality and functionality of the interconnect structure.
Regarding claim 4, Paulson teaches wherein performing the annealing operation comprises: performing the annealing operation using: hydrogen gas (H2) (Col.5, lines 24-27), a temperature range of approximately 160 degrees Celsius to approximately 450 degrees Celsius (Col. 3, lines 5-7. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to apply an annealing process to the structure taught by Lin et al. according to the teachings of Paulson, where only select gases and/or mixtures of them are used at specific temperatures in order to properly remove any defects and ensure the overall quality and functionality of the interconnect structure.
Paulson fails to teach a vacuum pressure range of approximately 0.5 Tor to approximately 10 Tor.
Sasaki teaches a vacuum pressure range of approximately 0.5 Tor to approximately 10 Tor (Col. 18, lines 41-42. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to apply an annealing process to the structure taught by Lin et al. according to the teachings of Sasaki, where the process is conducted only within a select pressure range to ensure the removal of defects and the overall quality and functionality of the interconnect structure.
Regarding claim 30, Paulson teaches wherein the defects from the first part of the interconnect structure are removed using: a combination of gases including nitrogen (N2), helium (He), and argon (Ar) (Col.5, lines 24-27), and a temperature range of approximately 200 degrees Celsius to approximately 450 degrees Celsius (Col. 3, lines 5-7. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to apply an annealing process to the structure taught by Lin et al. according to the teachings of Paulson, where only select gases and/or mixtures of them are used at specific temperatures in order to properly remove any defects and ensure the overall quality and functionality of the interconnect structure.
Paulson fails to teach a vacuum pressure range of approximately 0.5 Tor to approximately 10 Tor.
Sasaki teaches a vacuum pressure range of approximately 0.5 Tor to approximately 10 Tor (Col. 18, lines 41-42. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to apply an annealing process to the structure taught by Lin et al. according to the teachings of Sasaki, where the process is conducted only within a select pressure range to ensure the removal of defects and the overall quality and functionality of the interconnect structure.
Claims 5 and 33 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. in further view of Jeng (PGPub No. 20100120253).
Regarding claim 5, Jeng teaches forming a dielectric recapping layer (Fig. 8, 120) on the first dielectric layer (Fig. 8, 107) and on the second part of the interconnect structure after filling the remaining portion of the opening with the second part of the interconnect structure; and forming another opening through the dielectric recapping layer (Fig. 8, 120), through the first dielectric layer (Fig. 8, 105), through the etch stop layer (Fig. 8, 103), and to a conductive structure in the second dielectric layer of the semiconductor device (Fig. 8, 105). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Lin et al. with those of Jeng, where the overall structure already containing a first interconnect structure is coated in a dielectric recapping layer in order to protect the existing regions from the process of forming a new opening for an additional interconnect structure.
Jeng fails to teach forming a first part of another interconnect structure in the other opening; performing another annealing operation on the first part of the other interconnect structure to remove defects from the first part of the other interconnect structure; and filling a remaining portion of the other opening with a second part of the other interconnect structure after performing the other annealing operation.
Lin et al., specifically in further view of Leavy, teaches forming a first part of another interconnect structure in the other opening (Fig. 3F and [0040] points to forming a first layer of copper 350 (first part) in a trench region 336.); performing another annealing operation on the first part of the other interconnect structure to remove defects from the first part of the other interconnect structure ([0042] points to annealing the first layer of copper 350 (first part).); and filling a remaining portion of the other opening with a second part of the other interconnect structure after performing the other annealing operation (Fig. 3G and [0043] point to a second layer of copper 352 (second part) that is formed on the annealed first layer of copper 350.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Lin et al. and Jeng, such that an additional opening is formed and filled by an additional interconnect structure in order to create a network of interconnects upon which additional devices and/or components can be formed.
Regarding claim 33, Jeng teaches forming another opening through the dielectric recapping layer (Fig. 8, 120), through the first dielectric layer (Fig. 8, 105), through the etch stop layer (Fig. 8, 103), and to a conductive structure in the second dielectric layer of the semiconductor device (Fig. 8, 105). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Lin et al. with those of Jeng, where the overall structure already containing a first interconnect structure is coated in a dielectric recapping layer in order to protect the existing regions from the process of forming a new opening for an additional interconnect structure.
Jeng fails to teach forming a first part of another interconnect structure in the other opening; removing defects from the first part of the other interconnect structure; and filling a second portion of the other opening with a second part of the other interconnect structure after removing the defects from the first part of the other interconnect structure.
Lin et al., specifically in further view of Leavy, teaches forming a first part of another interconnect structure in the other opening (Fig. 3F and [0040] points to forming a first layer of copper 350 (first part) in a trench region 336.); removing defects from the first part of the other interconnect structure ([0042] points to annealing the first layer of copper 350 (first part).); and filling a second portion of the other opening with a second part of the other interconnect structure after removing the defects from the first part of the other interconnect structure (Fig. 3G and [0043] point to a second layer of copper 352 (second part) that is formed on the annealed first layer of copper 350.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Lin et al. and Jeng, such that an additional opening is formed and filled by an additional interconnect structure in order to create a network of interconnects upon which additional devices and/or components can be formed.
Claim 21-26 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. in further view of Park (PGPub No. 20210225759).
Regarding claim 21, Lin teaches a method, comprising: forming an etch stop layer (Fig. 4; 202) on a capping layer (Id.; 112); forming a second dielectric layer on the etch stop layer (Id.; 114); forming an opening, having tapered walls that create a single slope (Id.; 116), through the second dielectric layer (Id.; 114), through the etch stop layer (Id.; 202), through the capping layer (Id.; 112), and to a top surface of a metal capping layer in the first dielectric layer (Fig. 7; 302, 104); wherein the first portion of the opening has tapered sidewalls; and wherein the second portion of the opening has tapered sidewalls (Fig. 4; 116).
Lin fails to teach a capping layer in a first dielectric layer of a semiconductor device; filling a first portion of the opening with a first part of an interconnect structure over the conductive material metal capping layer; removing defects from the first part of the interconnect structure, wherein a top surface of the first part of the interconnect structure is convex after removing defects from the first part of the interconnect structure; and filling a second portion of the opening with a second part of the interconnect structure after removing the defects from the first part of the interconnect structure.
Park teaches a capping layer in a first dielectric layer of a semiconductor device (Figs. 2-3; 102, 101). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Lin and Park, such that the capping layer is formed in the first dielectric layer in order to create a recessed structure that surrounds and provides insulation and/or protection to a portion of the capping layer as well as the components underneath said layer.
Lin et al. fails to teach filling a first portion of the opening with a first part of an interconnect structure over the conductive material metal capping layer; removing defects from the first part of the interconnect structure, wherein a top surface of the first part of the interconnect structure is convex after removing defects from the first part of the interconnect structure; and filling a second portion of the opening with a second part of the interconnect structure after removing the defects from the first part of the interconnect structure.
Leavy teaches filling a first portion of the opening with a first part of an interconnect structure over the conductive material metal capping layer (Fig. 3F and [0040]; 350); removing defects from the first part of the interconnect structure ([0042]); and filling a second portion of the opening with a second part of the interconnect structure after removing the defects from the first part of the interconnect structure (Fig. 3G and [0043]; 352). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Lin et al. and Leavy, such that the opening is filled with a first part of an interconnect structure, said part is then annealed to remove defects, and finally the opening is filled with a second part of an interconnect structure in order to create a multi-level interconnect network via a damascene process that improves grain growth while mitigating formation of undesirable voiding regions and reducing resistance of the formed interconnect/conductive feature.
Lin et al. fails to explicitly teach wherein a top surface of the first part of the interconnect structure is convex after removing defects from the first part of the interconnect structure. However, one of ordinary skill in the art could consider portions of the first layer of copper 350 as shown in Figs. 3F-3H of Leavy, specifically the upward surfaces on the left and right edges, to be convex in shape.
Schneegans teaches wherein a top surface of the first part of the interconnect structure is convex after removing defects from the first part of the interconnect structure ([0023] points to performing an annealing process (removing defects) on a multilayer metallization 132 (interconnect structure), such that a final wafer bow if produced e.g. tensile (concave), no-bow or compressive (convex).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Lin et al. and Schneegans, such that the first part of the interconnect structure is given a convex shape after removing defects from said part in order to minimize stress concentration and increase the structural integrity of the interconnect structure as a whole.
Regarding claim 22, Leavy teaches wherein the first part of the interconnect structure resides within the first dielectric layer and intersects with the etch stop layer and the second dielectric layer (Fig. 3F points to the interlayer dielectric layer 314 (second dielectric layer), the etch stop layer 312, the layer 308 (first dielectric layer), and the copper 350 (first part). It is considered obvious that the conductive contact/structure 310 could have been formed with a smaller thickness, which would result in the direct contact/interface between the copper 350 and the conductive contact/structure 310 as shown in Fig. 3F to extend into said
layer 308 (first dielectric layer).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Lin et al. and Leavy, such that the first part of the interconnect structure resides within the first dielectric layer and intersects with the etch stop layer and the second dielectric layer in order to create an interconnect structure that is at least partially surrounded and protected by the first dielectric layer yet is also of an adequate vertical length so as to establish communication with the underlying components.
Regarding claim 23, Paulson teaches wherein the defects from the first part of the interconnect structure are removed using: a combination of gases including nitrogen (N2), helium (He), and argon (Ar) (Col.5, lines 24-27), and a temperature range of approximately 200 degrees Celsius to approximately 450 degrees Celsius (Col. 3, lines 5-7. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Lin et al. with those of Paulson, where only select gases and/or mixtures of them are used at specific temperatures in order to properly remove any defects and ensure the overall quality and functionality of the interconnect structure.
Paulson fails to teach a vacuum pressure range of approximately 0.5 Tor to approximately 10 Tor.
Sasaki teaches a vacuum pressure range of approximately 0.5 Tor to approximately 10 Tor (Col. 18, lines 41-42. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Lin et al. with those of Sasaki, where the process is conducted only within a select pressure range to ensure the removal of defects and the overall quality and functionality of the interconnect structure.
Regarding claim 24, Paulson teaches wherein the defects from the first part of the interconnect structure are removed using: hydrogen gas (H2) (Col.5, lines 24-27), and a temperature range of approximately 160 degrees Celsius to approximately 450 degrees Celsius (Col. 3, lines 5-7. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Lin et al. with those of Paulson, where only select gases and/or mixtures of them are used at specific temperatures in order to properly remove any defects and ensure the overall quality and functionality of the interconnect structure.
Paulson fails to teach a vacuum pressure range of approximately 0.5 Tor to approximately 10 Tor.
Sasaki teaches a vacuum pressure range of approximately 0.5 Tor to approximately 10 Tor (Col. 18, lines 41-42. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Lin et al. with those of Sasaki, where the process is conducted only within a select pressure range to ensure the removal of defects and the overall quality and functionality of the interconnect structure.
Regarding claim 25, Jeng teaches forming a dielectric recapping layer (Fig. 10, 120) on the second dielectric layer (Fig. 8, 107) and on the second part of the interconnect structure after filling the second portion of the opening with the second part of the interconnect structure. Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Lin et al. with those of Jeng, where the overall structure already containing a first interconnect structure is coated in a dielectric recapping layer in order to protect the existing regions from the process of forming a new opening for an additional interconnect structure.
Regarding claim 26, Jeng teaches forming another opening through the dielectric recapping layer (Fig. 8, 120), through the first dielectric layer (Fig. 8, 105), through the etch stop layer (Fig. 8, 103), and to a conductive structure in the second dielectric layer of the semiconductor device (Fig. 8, 105). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Lin et al. with those of Jeng, where the overall structure already containing a first interconnect structure is coated in a dielectric recapping layer in order to protect the existing regions from the process of forming a new opening for an additional interconnect structure.
Jeng fails to teach forming a first part of another interconnect structure in the other opening; removing defects from the first part of the other interconnect structure; and filling a second portion of the other opening with a second part of the other interconnect structure after removing the defects from the first part of the other interconnect structure.
Lin et al., specifically in further view of Leavy, teaches forming a first part of another interconnect structure in the other opening (Fig. 3F and [0040] points to forming a first layer of copper 350 (first part) in a trench region 336.); removing defects from the first part of the other interconnect structure ([0042] points to annealing (removing defects from) the first layer of copper 350 (first part).); and filling a second portion of the other opening with a second part of the other interconnect structure after removing the defects from the first part of the other interconnect structure (Fig. 3G and [0043] point to a second layer of copper 352 (second part) that is formed on the annealed first layer of copper 350.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Lin et al. and Jeng, such that an additional opening is formed and filled by an additional interconnect structure in order to create a network of interconnects upon which additional devices and/or components can be formed.
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. in further view of Liu (US Patent No. 10290580).
Regarding claim 27, Liu teaches wherein a vertical position of a bottom surface of the first part of the interconnect structure (Fig. 5, 110) is lower in the semiconductor device relative to a bottom surface of the first part of the other interconnect structure (Fig. 5, 112). Thus, it would have been obvious to POSITA prior to the filing date of the claimed invention to apply the teachings of Liu to the interconnect structures taught in Lin et al., such that one of the interconnects extends further in order to allow interactions with different layers within the structure.
Claim(s) 37 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. in further view of Feng (US Patent No. 7030016).
Regarding claim 37, Feng teaches wherein an interface between the first part of the interconnect structure and the second part of the interconnect structure is lower than a topmost surface of the first dielectric layer (Fig. 6 points to an interconnect comprising a metal layer 18 (first part), a metal layer 19 (second part), and a dielectric layer 13.). Thus, it would have been obvious to POSITA prior to the filing date of the claimed invention to combine the teachings of Lin et al. and Feng, such that the interface between the first and second parts of the interconnect structure is located below the top surface of the first dielectric layer in order to provide an even surface while maintaining a strong bond between said parts.
Claim(s) 38 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. in further view of Yang (PGPub No. 20210233843).
Regarding claim 38, Yang teaches wherein the first part of the interconnect is in contact with a first portion of the second dielectric layer, and wherein the second part of the interconnect is in contact with a second portion of the second dielectric layer (Figs. 7-9 and [0048] point to embodiments of an anti-fuse device comprising a second electrode 26 (interconnect), which may omit the formation of a diffusion barrier liner 24L, and a second interconnect dielectric material layer 22.), wherein the second portion of the dielectric layer is less than the first portion of the dielectric layer (It is considered obvious that one of ordinary skill in the art would form the first part of the interconnect (and by extension increase the size of the first portion of the dielectric layer) such that it is greater than the second part of the interconnect (and by extension the second portion of the dielectric layer) in order to create a solid foundation for the interconnect structure as a whole.). Thus, it would have been obvious to POSITA prior to the filing date of the claimed invention to combine the teachings of Lin et al. and Yang, such that the second dielectric layer comprises a larger underlying first portion and a smaller overlying second portion in order to better support and protect the corresponding portions of the interconnect structure as needed.
Response to Arguments
Applicant’s arguments, see Remarks, filed 08/17/2026, with respect to the rejection(s) of amended claim(s) 1, 21, and 28 (and by extension any dependent claims) under 35 U.S.C. §103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Lin (US Patent No. 9613852) and/or in further view of Park (PGPub No. 20210225759).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/PATRICK CULLEN/Assistant Examiner, Art Unit 2899
/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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