Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
Claim(s) 1, 2, 21, 22, 28, 29, 35, and 39 are rejected under 35 U.S.C. 103 as being unpatentable over Leavy (PGPub No. 20060024962) in further view of Lin (US Patent No. 9613852) and Schneegans (PGPub No. 20130026633).
Regarding claim 1, Leavy teaches a method, comprising: forming an opening through a first dielectric layer, through an etch stop layer, and to a conductive structure in a second dielectric layer of a semiconductor device (Fig. 3E points to a trench region 336 (opening) formed through an interlayer dielectric layer 314 (first dielectric layer), through an etch stop layer 312 and to a conductive contact 310 (conductive structure) located in layer 308 (second dielectric layer).); filling a first portion of the opening with a first part of an interconnect structure, wherein the first part of the interconnect structure resides directly on the conductive structure (Fig. 3F and [0040] points to a first layer of copper 350 (first part).); performing an annealing operation on the first part of the interconnect structure to remove defects from the first part of the interconnect structure ([0042] points to annealing the first layer of copper 350 (first part).); and filling a remaining portion of the opening with a second part of the interconnect structure after performing the annealing operation (Fig. 3G and [0043] point to a second layer of copper 352 (second part) that is formed on the annealed first layer of copper 350.).
Leavy fails to teach the opening having tapered walls that create a single slope, and wherein a top surface of the first part of the interconnect structure is convex after performing the annealing operation.
Lin teaches the opening having tapered walls that create a single slope (Fig. 4 points to a semiconductor structure 100 comprising one or more contact trenches 116.). Thus, it would have been obvious to a person of ordinary skill in the art (POSITA) prior to the filing date of the claimed invention to combine the teachings of Leavy and Lin, such that the walls of the opening are tapered to create a single slope in order to reduce stress concentration and/or provide better control during subsequent deposition/filling operation conducted in the opening.
Leavy et al. fails to explicitly teach wherein the opened has tapered sidewalls, wherein a top surface of the first part of the interconnect structure is convex after performing the annealing operation. However, one of ordinary skill in the art could consider portions of the first layer of copper 350 as shown in Figs. 3F-3H of Leavy, specifically the upward surfaces on the left and right edges, to be convex in shape.
Schneegans teaches wherein a top surface of the first part of the interconnect structure is convex after performing the annealing operation ([0023] points to performing an annealing process on a multilayer metallization 132 (interconnect structure), such that a final wafer bow if produced e.g. tensile (concave), no-bow or compressive (convex).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Leavy et al. and Schneegans, such that the first part of the interconnect structure is given a convex shape as a result of the annealing process in order to minimize stress concentration and increase the structural integrity of the interconnect structure as a whole.
Regarding claim 2, Leavy teaches performing another annealing operation on the semiconductor device to remove defects from the second part of the interconnect structure ([0043] points to the second layer of copper 352 (second part) being annealed. Fig. 4 further points to a repeatable sequence where each conductive layer formed (first part; second) is individually annealed); and performing a chemical mechanical planarization (CMP) operation on the second part of the interconnect structure (Fig. 4 and [0016] point to performing a final planarization operation 414, such as chemical mechanical planarization (CMP), after depositing the conductive layers.).
Regarding claim 21, Leavy teaches a method, comprising: forming an etch stop layer on a semiconductor device; forming a first dielectric layer on the etch stop layer; forming an opening through the first dielectric layer, through the etch stop layer, and to a conductive material in a second dielectric layer of a semiconductor device (Fig. 3E points to a trench region 336 (opening) formed through an interlayer dielectric layer 314 (first dielectric layer), through an etch stop layer 312 and to a conductive contact 310 (conductive structure) located in layer 308 (second dielectric layer).); filling a first portion of the opening with a first part of an interconnect structure over the conductive material (Fig. 3F and [0040] points to a first layer of copper 350 (first part).); removing defects from the first part of the interconnect structure ([0042] points to annealing (removing defects from) the first layer of copper 350 (first part).); and filling a second portion of the opening with a second part of the interconnect structure after removing the defects from the first part of the interconnect structure (Fig. 3G and [0043] point to a second layer of copper 352 (second part) that is formed on the annealed first layer of copper 350.).
Leavy fails to teach an opening having tapered walls that create a single slope, wherein the first portion of the opening has tapered sidewalls, wherein a top surface of the first part of the interconnect structure is convex after removing defects from the first part of the interconnect structure, and wherein the second portion of the opening has tapered sidewalls.
Lin teaches an opening having tapered walls that create a single slope, wherein the first portion of the opening has tapered sidewalls and wherein the second portion of the opening has tapered sidewalls (Fig. 4 points to a semiconductor structure 100 comprising one or more contact trenches 116.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Leavy and Lin, such that the walls of the opening are tapered to create a single slope in order to reduce stress concentration and/or provide better control during subsequent deposition/filling operation conducted in the opening.
Leavy et al. fails to explicitly teach wherein a top surface of the first part of the interconnect structure is convex after removing defects from the first part of the interconnect structure. However, one of ordinary skill in the art could consider portions of the first layer of copper 350 as shown in Figs. 3F-3H of Leavy, specifically the upward surfaces on the left and right edges, to be convex in shape.
Schneegans teaches wherein a top surface of the first part of the interconnect structure is convex after removing defects from the first part of the interconnect structure ([0023] points to performing an annealing process (removing defects) on a multilayer metallization 132 (interconnect structure), such that a final wafer bow if produced e.g. tensile (concave), no-bow or compressive (convex).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Leavy et al. and Schneegans, such that the first part of the interconnect structure is given a convex shape after removing defects from said part in order to minimize stress concentration and increase the structural integrity of the interconnect structure as a whole.
Regarding claim 22, Leavy teaches wherein the first dielectric layer and the etch stop layer resides over the second dielectric layer, wherein the first part of the interconnect structure resides within the second dielectric layer and intersects with the etch stop layer and the first dielectric layer (Fig. 3F points to the interlayer dielectric layer 314 (first dielectric layer), the etch stop layer 312, the layer 308 (second dielectric layer), the copper 350 (first part), and the conductive contact 310 (conductive structure). It is considered obvious that the conductive contact/structure 310 could have been formed with a smaller thickness, such that direct contact with the copper 350 would require said copper to extend within the second dielectric layer, in order provide greater protection and/or isolation during fabrication by allowing the layer 308 to better surround the conductive contact/structure 310.).
Regarding claim 28, Leavy teaches a method, comprising: forming an opening through a first dielectric layer, through an etch stop layer, and to a conductive structure in a second dielectric layer of a semiconductor device (Fig. 3E points to a trench region 336 (opening) formed through an interlayer dielectric layer 314 (first dielectric layer), through an etch stop layer 312 and to a conductive contact 310 (conductive structure) located in layer 308 (second dielectric layer).); filling a first portion of the opening with a first part of an interconnect structure over the conductive structure (Fig. 3F and [0040] points to a first layer of copper 350 (first part).); performing an annealing operation on the semiconductor device to remove defects from the first part of the interconnect structure ([0042] points to annealing the first layer of copper 350 (first part).); and filling a second portion of the opening with a second part of the interconnect structure after performing the annealing operation (Fig. 3G and [0043] point to a second layer of copper 352 (second part) that is formed on the annealed first layer of copper 350.).
Leavy fails to teach an opening having tapered walls that create a single slope, wherein the first portion of the opening has tapered sidewalls and wherein the second portion of the opening has tapered sidewalls.
Lin teaches an opening having tapered walls that create a single slope, wherein the first portion of the opening has tapered sidewalls and wherein the second portion of the opening has tapered sidewalls (Fig. 4 points to a semiconductor structure 100 comprising one or more contact trenches 116.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Leavy and Lin, such that the walls of the opening are tapered to create a single slope in order to reduce stress concentration and/or provide better control during subsequent deposition/filling operation conducted in the opening.
Regarding claim 29, Schneegans teaches wherein a top surface of the first part of the interconnect structure is convex after the defects are removed from the first part of the interconnect structure ([0023] points to performing an annealing process (removing defects) on a multilayer metallization 132 (interconnect structure), such that a final wafer bow if produced e.g. tensile (concave), no-bow or compressive (convex).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Leavy et al. and Schneegans, such that the first part of the interconnect structure is given a convex shape after removing defects from said part in order to minimize stress concentration and increase the structural integrity of the interconnect structure as a whole.
Regarding claim 35, Leavy in combination with Schneegans teaches wherein at least one of: the top surface of the first part of the interconnect structure is convex such that the top surface of the first part of the interconnect structure is curved away from a bottom surface of the interconnect structure ([0023] of Schneegans points to performing an annealing process on a multilayer metallization 132 (interconnect structure), such that a final wafer bow if produced e.g. tensile (concave), no-bow or compressive (convex). It is interpreted that the exact orientation of the curved first part of the interconnect structure is taught by Schneegans due to its disclosure of both a concave and convex shape.), or the first part of the interconnect structure is in direct contact with a top surface of the conductive structure (Fig. 3F of Leavy points to a first layer of copper 350 (first part) positioned in direct contact with a top surface of the conductive contact 310 (conductive structure).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Leavy et al. and Schneegans, such that at least the first part of the interconnect structure is given a convex shape after removing defects from said part in order to minimize stress concentration and increase the structural integrity of the interconnect structure as a whole.
Regarding claim 39, Lin teaches wherein the opening further extends through a dielectric capping layer, wherein dielectric capping layer resides on the conductive structure and sidewall spacers, wherein the sidewall spacers surround the conductive structure and a portion of the dielectric capping layer, and wherein one of the sidewall spacers is in contact with the conductive structure is in contact with the second dielectric layer (Fig. 4 points to the one or more contact trenches 116 (opening), a first ESL 112 (dielectric capping layer), a conductive feature 106, and a sealing layer 108 (sidewall spacers).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Leavy et al. and Lin, such that the conductive structure is surrounded by sidewall spacers, a dielectric capping layer, and an opening extending through said layer in order to provide an adequate level of electrical isolation for the conductive structure while still enabling a method of communication between said structure and any external/overlying components.
Claims 3, 4, 23, 24, and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Leavy et al. in further view of Paulson (US Patent No. 4392992 A) and Sasaki (US Patent No. 9748104 B2).
Regarding claim 3, Paulson teaches wherein performing the annealing operation comprises: performing the annealing operation using: a combination of gases including nitrogen (N2), helium (He), and argon (Ar) (Col.5, lines 24-27), and a temperature range of approximately 200 degrees Celsius to approximately 450 degrees Celsius (Col. 3, lines 5-7). Specifically, Paulson teaches that the annealing step is carried out in a dry ambient by heating to a temperature less than 1000oC (Id.), and examples of gases giving satisfactory annealing behavior are dry oxygen, forming gas, argon, helium, hydrogen, nitrogen and/or mixtures thereof (Col.5, lines 24-27). In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to apply an annealing process to the structure taught by Leavy et al. according to the teachings of Paulson, where only select gases and/or mixtures of them are used at specific temperatures in order to properly remove any defects and ensure the overall quality and functionality of the interconnect structure.
Paulson fails to teach a vacuum pressure range of approximately 0.5 Tor to approximately 10 Tor.
Sasaki teaches a vacuum pressure range of approximately 0.5 Tor to approximately 10 Tor (Col. 18, lines 41-42). Specifically, Sasaki teaches depositing film on a semiconductor wafer where the vacuum chamber the process takes place in has a pressure in a range of 1 to 10 Torr and a pre annealing is performed (Id.). In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to apply an annealing process to the structure taught by Leavy et al. according to the teachings of Sasaki, where the process is conducted only within a select pressure range to ensure the removal of defects and the overall quality and functionality of the interconnect structure.
Regarding claim 4, Paulson teaches wherein performing the annealing operation comprises: performing the annealing operation using: hydrogen gas (H2) (Col.5, lines 24-27), a temperature range of approximately 160 degrees Celsius to approximately 450 degrees Celsius (Col. 3, lines 5-7). Specifically, Paulson teaches that the annealing step is carried out in a dry ambient by heating to a temperature less than 1000oC (Id.), and examples of gases giving satisfactory annealing behavior are dry oxygen, forming gas, argon, helium, hydrogen, nitrogen and/or mixtures thereof (Col.5, lines 24-27). In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to apply an annealing process to the structure taught by Leavy et al. according to the teachings of Paulson, where only select gases and/or mixtures of them are used at specific temperatures in order to properly remove any defects and ensure the overall quality and functionality of the interconnect structure.
Paulson fails to teach a vacuum pressure range of approximately 0.5 Tor to approximately 10 Tor.
Sasaki teaches a vacuum pressure range of approximately 0.5 Tor to approximately 10 Tor (Col. 18, lines 41-42). Specifically, Sasaki teaches depositing film on a semiconductor wafer where the vacuum chamber the process takes place in has a pressure in a range of 1 to 10 Torr and a pre annealing is performed (Id.). In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to apply an annealing process to the structure taught by Leavy et al. according to the teachings of Sasaki, where the process is conducted only within a select pressure range to ensure the removal of defects and the overall quality and functionality of the interconnect structure.
Regarding claim 23, Paulson teaches wherein the defects from the first part of the interconnect structure are removed using: a combination of gases including nitrogen (N2), helium (He), and argon (Ar) (Col.5, lines 24-27), and a temperature range of approximately 200 degrees Celsius to approximately 450 degrees Celsius (Col. 3, lines 5-7). Specifically, Paulson teaches that the annealing step is carried out in a dry ambient by heating to a temperature less than 1000oC (Id.), and examples of gases giving satisfactory annealing behavior are dry oxygen, forming gas, argon, helium, hydrogen, nitrogen and/or mixtures thereof (Col.5, lines 24-27). In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Leavy et al. with those of Paulson, where only select gases and/or mixtures of them are used at specific temperatures in order to properly remove any defects and ensure the overall quality and functionality of the interconnect structure.
Paulson fails to teach a vacuum pressure range of approximately 0.5 Tor to approximately 10 Tor.
Sasaki teaches a vacuum pressure range of approximately 0.5 Tor to approximately 10 Tor (Col. 18, lines 41-42). Specifically, Sasaki teaches depositing film on a semiconductor wafer where the vacuum chamber the process takes place in has a pressure in a range of 1 to 10 Torr and a pre annealing is performed (Id.). In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Leavy et al. with those of Sasaki, where the process is conducted only within a select pressure range to ensure the removal of defects and the overall quality and functionality of the interconnect structure.
Regarding claim 24, Paulson teaches wherein the defects from the first part of the interconnect structure are removed using: hydrogen gas (H2) (Col.5, lines 24-27), and a temperature range of approximately 160 degrees Celsius to approximately 450 degrees Celsius (Col. 3, lines 5-7). Specifically, Paulson teaches that the annealing step is carried out in a dry ambient by heating to a temperature less than 1000oC (Id.), and examples of gases giving satisfactory annealing behavior are dry oxygen, forming gas, argon, helium, hydrogen, nitrogen and/or mixtures thereof (Col.5, lines 24-27). In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Leavy et al. with those of Paulson, where only select gases and/or mixtures of them are used at specific temperatures in order to properly remove any defects and ensure the overall quality and functionality of the interconnect structure.
Paulson fails to teach a vacuum pressure range of approximately 0.5 Tor to approximately 10 Tor.
Sasaki teaches a vacuum pressure range of approximately 0.5 Tor to approximately 10 Tor (Col. 18, lines 41-42). Specifically, Sasaki teaches depositing film on a semiconductor wafer where the vacuum chamber the process takes place in has a pressure in a range of 1 to 10 Torr and a pre annealing is performed (Id.). In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Leavy et al. with those of Sasaki, where the process is conducted only within a select pressure range to ensure the removal of defects and the overall quality and functionality of the interconnect structure.
Regarding claim 30, Paulson teaches wherein the defects from the first part of the interconnect structure are removed using: a combination of gases including nitrogen (N2), helium (He), and argon (Ar) (Col.5, lines 24-27), and a temperature range of approximately 200 degrees Celsius to approximately 450 degrees Celsius (Col. 3, lines 5-7). Specifically, Paulson teaches that the annealing step is carried out in a dry ambient by heating to a temperature less than 1000oC (Id.), and examples of gases giving satisfactory annealing behavior are dry oxygen, forming gas, argon, helium, hydrogen, nitrogen and/or mixtures thereof (Col.5, lines 24-27). In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to apply an annealing process to the structure taught by Leavy et al. according to the teachings of Paulson, where only select gases and/or mixtures of them are used at specific temperatures in order to properly remove any defects and ensure the overall quality and functionality of the interconnect structure.
Paulson fails to teach a vacuum pressure range of approximately 0.5 Tor to approximately 10 Tor.
Sasaki teaches a vacuum pressure range of approximately 0.5 Tor to approximately 10 Tor (Col. 18, lines 41-42). Specifically, Sasaki teaches depositing film on a semiconductor wafer where the vacuum chamber the process takes place in has a pressure in a range of 1 to 10 Torr and a pre annealing is performed (Id.). In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to apply an annealing process to the structure taught by Leavy et al. according to the teachings of Sasaki, where the process is conducted only within a select pressure range to ensure the removal of defects and the overall quality and functionality of the interconnect structure.
Claims 5, 25, 26, and 33 are rejected under 35 U.S.C. 103 as being unpatentable over Leavy et al. in further view of Jeng (PGPub No. 20100120253).
Regarding claim 5, Jeng teaches forming a dielectric recapping layer (Fig. 8, 120) on the first dielectric layer (Fig. 8, 107) and on the second part of the interconnect structure after filling the remaining portion of the opening with the second part of the interconnect structure; and forming another opening through the dielectric recapping layer (Fig. 8, 120), through the first dielectric layer (Fig. 8, 105), through the etch stop layer (Fig. 8, 103), and to another conductive structure in the second dielectric layer of the semiconductor device (Fig. 8, 105). Specifically, Jeng teaches a semiconductor device where a dielectric re-capping layer 120 is applied over the DARC (dielectric anti-reflective coating) film layer 107 ([0041]), which is layered over a dielectric layer 105 and an etch stop layer 103, with an example via 15 (Fig. 10). The re-capping method described may also be used for trench formation ([0049]), with via positions 102, 104, and 106 showing how trenches or vias will be formed and filled with a conductive material to form connections with the underlying metal layer 101 (Fig. 2; [0010]). The term “metal layer” is interpreted to mean the same as “conductive structure in the second dielectric layer” due to the fact that the metal layer is described as being made of a conductive metal such as copper, and the fact that it is shown in all relevant figures as being inside a dielectric layer similar to that of dielectric layer 105. The term “connections with the underlying metal layer” is interpreted to mean the same as “forming an opening […] through the etch stop layer” as the etch stop layer 103 is the only layer between the vias 102, 104, and 106, and the metal layer 101, so any connection to the metal layer by extension must have gone through the etch stop layer. Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Leavy et al. with those of Jeng, where the overall structure already containing a first interconnect structure is coated in a dielectric recapping layer in order to protect the existing regions from the process of forming a new opening for an additional interconnect structure.
Jeng fails to teach forming a first part of another interconnect structure in the other opening; performing another annealing operation on the first part of the other interconnect structure to remove defects from the first part of the other interconnect structure; and filling a remaining portion of the other opening with a second part of the other interconnect structure after performing the other annealing operation.
Leavy et al., specifically in further view of Leavy, teaches forming a first part of another interconnect structure in the other opening (Fig. 3F and [0040] points to forming a first layer of copper 350 (first part) in a trench region 336.); performing another annealing operation on the first part of the other interconnect structure to remove defects from the first part of the other interconnect structure ([0042] points to annealing the first layer of copper 350 (first part).); and filling a remaining portion of the other opening with a second part of the other interconnect structure after performing the other annealing operation (Fig. 3G and [0043] point to a second layer of copper 352 (second part) that is formed on the annealed first layer of copper 350.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Leavy et al. and Jeng, such that an additional opening is formed and filled by an additional interconnect structure in order to create a network of interconnects upon which additional devices and/or components can be formed.
Regarding claim 25, Jeng teaches forming a dielectric recapping layer (Fig. 10, 120) on the first dielectric layer (Fig. 8, 107) and on the second part of the interconnect structure after filling the second portion of the opening with the second part of the interconnect structure. Specifically, Jeng teaches a semiconductor device where a dielectric re-capping layer 120 is applied over the DARC (dielectric anti-reflective coating) film layer 107 ([0041]), which is layered over a dielectric layer 105 and an etch stop layer 103, with an example via 15 (Fig. 10). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Leavy et al. with those of Jeng, where the overall structure already containing a first interconnect structure is coated in a dielectric recapping layer in order to protect the existing regions from the process of forming a new opening for an additional interconnect structure.
Regarding claim 26, Jeng teaches forming another opening through the dielectric recapping layer (Fig. 8, 120), through the first dielectric layer (Fig. 8, 105), through the etch stop layer (Fig. 8, 103), and to another conductive structure in the second dielectric layer of the semiconductor device (Fig. 8, 105). Specifically, Jeng teaches a semiconductor device where a dielectric re-capping layer 120 is applied over the DARC (dielectric anti-reflective coating) film layer 107 ([0041]), which is layered over a dielectric layer 105 and an etch stop layer 103, with an example via 15 (Fig. 10). The re-capping method described may also be used for trench formation ([0049]), with via positions 102, 104, and 106 showing how trenches or vias will be formed and filled with a conductive material to form connections with the underlying metal layer 101 (Fig. 2; [0010]). The term “metal layer” is interpreted to mean the same as “conductive structure in the second dielectric layer” due to the fact that the metal layer is described as being made of a conductive metal such as copper, and the fact that it is shown in all relevant figures as being inside a dielectric layer similar to that of dielectric layer 105. The term “connections with the underlying metal layer” is interpreted to mean the same as “forming an opening […] through the etch stop layer” as the etch stop layer 103 is the only layer between the vias 102, 104, and 106, and the metal layer 101, so any connection to the metal layer by extension must have gone through the etch stop layer. Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Leavy et al. with those of Jeng, where the overall structure already containing a first interconnect structure is coated in a dielectric recapping layer in order to protect the existing regions from the process of forming a new opening for an additional interconnect structure.
Jeng fails to teach forming a first part of another interconnect structure in the other opening; removing defects from the first part of the other interconnect structure; and filling a second portion of the other opening with a second part of the other interconnect structure after removing the defects from the first part of the other interconnect structure.
Leavy et al., specifically in further view of Leavy, teaches forming a first part of another interconnect structure in the other opening (Fig. 3F and [0040] points to forming a first layer of copper 350 (first part) in a trench region 336.); removing defects from the first part of the other interconnect structure ([0042] points to annealing (removing defects from) the first layer of copper 350 (first part).); and filling a second portion of the other opening with a second part of the other interconnect structure after removing the defects from the first part of the other interconnect structure (Fig. 3G and [0043] point to a second layer of copper 352 (second part) that is formed on the annealed first layer of copper 350.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Leavy et al. and Jeng, such that an additional opening is formed and filled by an additional interconnect structure in order to create a network of interconnects upon which additional devices and/or components can be formed.
Regarding claim 33, Jeng teaches forming another opening through the dielectric recapping layer (Fig. 8, 120), through the first dielectric layer (Fig. 8, 105), through the etch stop layer (Fig. 8, 103), and to another conductive structure in the second dielectric layer of the semiconductor device (Fig. 8, 105). Specifically, Jeng teaches a semiconductor device where a dielectric re-capping layer 120 is applied over the DARC (dielectric anti-reflective coating) film layer 107 ([0041]), which is layered over a dielectric layer 105 and an etch stop layer 103, with an example via 15 (Fig. 10). The re-capping method described may also be used for trench formation ([0049]), with via positions 102, 104, and 106 showing how trenches or vias will be formed and filled with a conductive material to form connections with the underlying metal layer 101 (Fig. 2; [0010]). The term “metal layer” is interpreted to mean the same as “conductive structure in the second dielectric layer” due to the fact that the metal layer is described as being made of a conductive metal such as copper, and the fact that it is shown in all relevant figures as being inside a dielectric layer similar to that of dielectric layer 105. The term “connections with the underlying metal layer” is interpreted to mean the same as “forming an opening […] through the etch stop layer” as the etch stop layer 103 is the only layer between the vias 102, 104, and 106, and the metal layer 101, so any connection to the metal layer by extension must have gone through the etch stop layer. Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Leavy et al. with those of Jeng, where the overall structure already containing a first interconnect structure is coated in a dielectric recapping layer in order to protect the existing regions from the process of forming a new opening for an additional interconnect structure.
Jeng fails to teach forming a first part of another interconnect structure in the other opening; removing defects from the first part of the other interconnect structure; and filling a second portion of the other opening with a second part of the other interconnect structure after removing the defects from the first part of the other interconnect structure.
Leavy et al., specifically in further view of Leavy, teaches forming a first part of another interconnect structure in the other opening (Fig. 3F and [0040] points to forming a first layer of copper 350 (first part) in a trench region 336.); removing defects from the first part of the other interconnect structure ([0042] points to annealing the first layer of copper 350 (first part).); and filling a second portion of the other opening with a second part of the other interconnect structure after removing the defects from the first part of the other interconnect structure (Fig. 3G and [0043] point to a second layer of copper 352 (second part) that is formed on the annealed first layer of copper 350.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Leavy et al. and Jeng, such that an additional opening is formed and filled by an additional interconnect structure in order to create a network of interconnects upon which additional devices and/or components can be formed.
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Leavy et al. in further view of Liu (US Patent No. 10290580).
Regarding claim 27, Liu teaches wherein a vertical position of a bottom surface of the first part of the interconnect structure (Fig. 5, 110) is lower in the semiconductor device relative to a bottom surface of the first part of the other interconnect structure (Fig. 5, 112). Specifically, Liu teaches a plurality of metal interconnect structures 112 (Col. 3, lines 31-32), with some of said structures extending further down into a plurality of vias 110, which are configured to provide for vertical interconnections (Fig. 5; Col. 3, lines 23-25). Thus, it would have been obvious to POSITA prior to the filing date of the claimed invention to apply the teachings of Liu to the interconnect structures taught in Leavy et al., such that one of the interconnects extends further in order to allow interactions with different layers within the structure.
Claim(s) 37 is rejected under 35 U.S.C. 103 as being unpatentable over Leavy et al. in further view of Feng (US Patent No. 7030016).
Regarding claim 37, Feng teaches wherein an interface between the first part of the interconnect structure and the second part of the interconnect structure is lower than a topmost surface of the first dielectric layer (Fig. 6 points to an interconnect comprising a metal layer 18 (first part), a metal layer 19 (second part), and a dielectric layer 13.). Thus, it would have been obvious to POSITA prior to the filing date of the claimed invention to combine the teachings of Leavy et al. and Feng, such that the interface between the first and second parts of the interconnect structure is located below the top surface of the first dielectric layer in order to provide an even surface while maintaining a strong bond between said parts.
Claim(s) 38 is rejected under 35 U.S.C. 103 as being unpatentable over Leavy et al. in further view of Yang (PGPub No. 20210233843).
Regarding claim 38, Yang teaches wherein the first part of the interconnect is in contact with a first portion of the second dielectric layer, and wherein the second part of the interconnect is in contact with a second portion of the second dielectric layer (Figs. 7-9 and [0048] point to embodiments of an anti-fuse device comprising a second electrode 26 (interconnect), which may omit the formation of a diffusion barrier liner 24L, and a second interconnect dielectric material layer 22.), wherein the second portion of the dielectric layer is less than the first portion of the dielectric layer (It is considered obvious that one of ordinary skill in the art would form the first part of the interconnect (and by extension increase the size of the first portion of the dielectric layer) such that it is greater than the second part of the interconnect (and by extension the second portion of the dielectric layer) in order to create a solid foundation for the interconnect structure as a whole.). Thus, it would have been obvious to POSITA prior to the filing date of the claimed invention to combine the teachings of Leavy et al. and Yang, such that the second dielectric layer comprises a larger underlying first portion and a smaller overlying second portion in order to better support and protect the corresponding portions of the interconnect structure as needed.
Response to Arguments
Applicant’s arguments, see Remarks, filed 03/05/226, with respect to the rejection(s) of claim(s) 1, 2, 21, 22, 28, 29, and 35 (and by extension any dependent claims) under 35 U.S.C. §103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Leavy et al. in further view of Lin (US Patent No. 9613852).
Conclusion
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/PATRICK CULLEN/Assistant Examiner, Art Unit 2899
/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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