Prosecution Insights
Last updated: July 17, 2026
Application No. 17/648,146

Semiconductor Device and Method of Stabilizing Heat Spreader on Semiconductor Package

Final Rejection §102§103
Filed
Jan 17, 2022
Examiner
CHEN, JACK S J
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
STATS ChipPAC Pte. Ltd.
OA Round
6 (Final)
77%
Grant Probability
Favorable
7-8
OA Rounds
0m
Est. Remaining
82%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
438 granted / 572 resolved
+8.6% vs TC avg
Moderate +5% lift
Without
With
+5.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
49 currently pending
Career history
610
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
53.6%
+13.6% vs TC avg
§102
23.8%
-16.2% vs TC avg
§112
9.9%
-30.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 572 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/16/2025 has been entered. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 14-16, 20-22, 26-28, 31-32 and 34-36 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Oh et al. US Pub. No. 2009/0294941 A1. Re claim 14. Oh et al. disclose a semiconductor device, comprising: an electrical component (e.g., fig. 1; the elements within and under element 120); and a heat sink 120 disposed over the electrical component, wherein the heat sink includes a horizontal portion (e.g., fig. 1, the top horizontal portion) at least partially disposed over the electrical component (fig. 1) and further extending beyond a footprint of the electrical component (fig. 1) and at least two vertical extensions (e.g., fig. 1; the left and right vertical extensions, also see figs. 7 and 8) formed at corners of the horizontal portion (fig. 1) and extending at least partially down and in contact with at least two opposing side surfaces of the electrical component (e.g., fig. 1) to prevent lateral movement of the heat sink with respect to the electrical component, see figs. 1-13 and pages 1-5 for more details. Re claim 15. The semiconductor device of claim 14, further including a thermal interface material (e.g., fig. 1; a top portion of the 122 is considered as the thermal interface material or the interface material between 120/18) disposed between the heat sink and electrical component. Re claim 16. The semiconductor device of claim 14, wherein the at least two vertical extensions extend partially but not completely down the at least two opposing side surfaces of the electrical component (fig. 1). Re claim 19. (Original) The semiconductor device of claim 14, wherein the electrical component includes a flipchip semiconductor die 110 (fig. 1). Re claim 20. Oh et al. disclose a semiconductor device, comprising: an electrical component (e.g., fig. 1; the elements within and under element 120); and a heat sink 120 disposed over the electrical component (fig. 1), wherein the heat sink includes a horizontal portion (e.g., fig. 1, the top horizontal portion) at least partially disposed over the electrical component and further extending beyond a footprint of the electrical component (fig. 1) and at least two vertical extensions (e.g., fig. 1; the left and right vertical extensions, also see figs. 7 and 8) extending at least partially below a top surface of the electrical component and in contact with at least two side surfaces of the electrical component. See figs. 1-13 and pages 1-5 for more details. Re claim 21. The semiconductor device of claim 20, further including a thermal interface material (e.g., fig. 1; a top portion of the 122 is considered as the thermal interface material) disposed between the heat sink and electrical component. Re claim 22. The semiconductor device of claim 20, wherein the at least two vertical extensions extend partially but not completely down the at least two side surfaces of the electrical component (e.g., fig .1). Re claim 26. Oh et al. disclose a semiconductor device, comprising: an electrical component (e.g., fig. 1; the elements within and under element 120); and a heat sink 120 disposed over the electrical component (fig. 1), wherein the heat sink includes a horizontal portion (e.g., fig. 1, the top horizontal portion) at least partially disposed over the electrical component and further extending beyond a footprint of the electrical component (fig. 1) and at least two vertical extensions (e.g., fig. 1; the left and right vertical extensions, also see figs. 7 and 8) extending down to simultaneously contact at least two side surfaces of the electrical component and prevent lateral movement of the heat sink. See figs. 1-13 and pages 1-5 for more details. Re claim 27. The semiconductor device of claim 26, further including a thermal interface material (e.g., fig. 1; a top portion of the 122 is considered as the thermal interface material) disposed between the heat sink and electrical component. Re claim 28. The semiconductor device of claim 26, wherein the at least two vertical extensions extend partially but not completely down the at least two side surfaces of the electrical component (fig. 1). Re claim 31. The semiconductor device of claim 26, wherein the at least two vertical extensions of the heat sink extending down to contact the at least two side surfaces of the electrical component are located at corners of horizontal portion of the heat sink (figs. 1, 7-8). Re claim 32. The semiconductor device of claim 26, wherein the at least two vertical extensions of the heat sink extending down to contact the at least two side surfaces of the electrical component are 90 degrees with respect to a surface of the horizontal portion of the heat sink (figs. 1, 7-8). Re claim 34. The semiconductor device of claim 14, wherein the at least two vertical extensions of the heat sink extending at least partially down and in contact with the at least two opposing side surfaces of the electrical component are 90 degrees with respect to a surface of the horizontal portion of the heat sink (figs. 1, 7-8). Re claim 35. The semiconductor device of claim 20, wherein the at least two vertical extensions of the heat sink extending at least partially below the top surface of the electrical component and in contact with the at least two side surfaces of the electrical component are located at corners of the horizontal portion of the heat sink (figs. 1, 7-8). Re claim 36. The semiconductor device of claim 20, wherein the vertical extension of the heat sink extending at least partially below the top surface of the electrical component and in contact with the at least two side surfaces of the electrical component are 90 degrees with respect to a surface of the horizontal portion of the heat sink (figs. 1, 7-8). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 19, 25 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. US Pub. No. 2009/0294941 A1 in view of Dry US Pub. No. 2020/0343157 A1. Oh et al. disclose above; however, Oh et al. does not explicitly show that the electrical component includes a flipchip semiconductor die. Dry taches a similar device, which use the flipchip 14/16 (fig. 1) semiconductor die as the electrical component. Therefore, one of ordinary skill in the requisite art before the invention was made would have used any die (i.e., flip chip die) suitable to the device of Oh et al. in order to optimize the device performance (e.g., superior electrical performance, improve thermal management etc.). Response to Arguments Applicant's arguments filed 10/16/2025 have been fully considered but they are not persuasive for reasons herein above. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACK CHEN whose telephone number is (571)272-1689. The examiner can normally be reached Monday to Friday, 8am to 4pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J. Green can be reached at (571)270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JACK S CHEN/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Show 18 earlier events
Oct 09, 2025
Request for Continued Examination
Oct 12, 2025
Response after Non-Final Action
Oct 16, 2025
Response Filed
Feb 23, 2026
Non-Final Rejection mailed — §102, §103
Apr 03, 2026
Response after Non-Final Action
Apr 03, 2026
Response Filed
Apr 16, 2026
Response Filed
Jul 14, 2026
Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

7-8
Expected OA Rounds
77%
Grant Probability
82%
With Interview (+5.2%)
2y 11m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 572 resolved cases by this examiner. Grant probability derived from career allowance rate.

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