Prosecution Insights
Last updated: October 04, 2026
Application No. 17/648,146

Semiconductor Device and Method of Stabilizing Heat Spreader on Semiconductor Package

Final Rejection §102§103§112
Filed
Jan 17, 2022
Examiner
CHEN, JACK S J
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Stats Chippac Pte. Ltd.
OA Round
6 (Final)
77%
Grant Probability
Favorable
7-8
OA Rounds
0m
Est. Remaining
82%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
442 granted / 576 resolved
+8.7% vs TC avg
Moderate +6% lift
Without
With
+5.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
34 currently pending
Career history
623
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
31.9%
-8.1% vs TC avg
§102
32.3%
-7.7% vs TC avg
§112
27.3%
-12.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 576 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 14-15, 19, 22, 28, 34 and 37 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Re claim 14, the phrase “… as measured by substantially a same distance as the heat sink extends beyond the footprint of the electrical component” was not described in the original specification. Re claim 22, the phrase “… as measured by substantially a same distance as the heat sink extends beyond the footprint of the electrical component” was not described in the original specification. Re claim 28, the phrase “… as measured by substantially a same distance as the heat sink extends beyond the footprint of the electrical component” was not described in the original specification. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 20-21, 25-27, 30-32, 35-36 and 38-39 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fujino et al, US Pub. No. 2020/0321261 A1. Re claim 20. Fujino et al. disclose a semiconductor device, comprising: an electrical component 11/12/41/5/42 etc. (e.g. fig. 13, the elements within and under the heat sink 3C); and a heat sink 3C (e.g., fig. 13) disposed over the electrical component, wherein the heat sink includes a horizontal portion at least partially disposed over the electrical component (e.g., fig. 13) and further extending beyond a footprint of the electrical component (e.g., fig. 13) and at least two vertical extensions 33 extending from the horizontal portion at least partially below a top surface of the electrical component and in continuous contact with at least two side surfaces of the electrical component from the horizontal portion to an end of the at least two vertical extensions (e.g., fig. 13), see figs. 1-20 and pages 1-9 for more details. Re claim 21. The semiconductor device of claim 20, further including a thermal interface material 2 (e.g., fig. 13) disposed between the heat sink and electrical component. Re claim 25. The semiconductor device of claim 20, wherein the electrical component includes a flipchip (e.g., paragraphs 36, 37 etc.) semiconductor die. Re claim 26. Fujino et al. disclose a semiconductor device, comprising: an electrical component 11/12/41/5/42 etc. (e.g. fig. 13, the elements within and under the heat sink 3C); and a heat sink 3c (e.g., fig.13) disposed over the electrical component, wherein the heat sink includes a horizontal portion at least partially disposed over the electrical component (e.g., fig. 13) and further extending beyond a footprint of the electrical component (e.g., fig. 13) and at least two vertical extensions 33 (e.g, fig. 13) extending from the horizontal portion down to simultaneously and continuously contact at least two side surfaces of the electrical component from the horizontal portion to an end of the at least two vertical extensions and prevent lateral movement of the heat sink (e.g., fig. 13), see figs. 1-20 and pages 1-9 for more details. Re claim 27. The semiconductor device of claim 26, further including a thermal interface material 2 (e.g., fig. 13) disposed between the heat sink and electrical component. Re claim 30. The semiconductor device of claim 26, wherein the electrical component includes a flipchip (e.g., paragraphs 36, 37 etc.) semiconductor die. Re claim 31. The semiconductor device of claim 26, wherein the at least two vertical extensions 33 of the heat sink extending down to contact the at least two side surfaces of the electrical component are located at corners of the horizontal portion of the heat sink (e.g., fig. 13). Re claim 32. The semiconductor device of claim 26, wherein the at least two vertical extensions 33 of the heat sink extending down to contact the at least two side surfaces of the electrical component are 90 degrees with respect to a surface of the horizontal portion of the heat sink (e.g., fig. 13). Re claim 35. The semiconductor device of claim 20, wherein the at least two vertical extensions 33 of the heat sink extending at least partially below the top surface of the electrical component and in contact with the at least two side surfaces of the electrical component are located at corners of the horizontal portion of the heat sink (e.g., fig. 13). Re claim 36. The semiconductor device of claim 20, wherein the at least two vertical extensions 33 of the heat sink extending at least partially below the top surface of the electrical component and in contact with the at least two side surfaces of the electrical component are 90 degrees with respect to a surface of the horizontal portion of the heat sink (e.g., fig. 13). Re claim 38. The semiconductor device of claim 20, wherein the at least two vertical extensions 33 are bent to 90 degrees from the horizontal portion of the heat sink (e.g., fig. 13). Re claim 39. The semiconductor device of claim 26, wherein the at least two vertical extensions 33 are bent to 90 degrees from the horizontal portion of the heat sink (e.g., fig. 13). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 14-15, 19, 22, 28, 34 and 37 are rejected under 35 U.S.C. 103 as being unpatentable over Fujino et al, US Pub. No. 2020/0321261 A1. Re claim 14. Fujino et al. disclose A semiconductor device, comprising: an electrical component 11/12/41/5/42 etc. (e.g. fig. 13, the elements within and under the heat sink 3C); and a heat sink 3C (e.g., fig. 13) disposed over the electrical component, wherein the heat sink includes a horizontal portion at least partially disposed over the electrical component and further extending beyond a footprint of the electrical component (e.g., fig. 13) and at least two vertical extensions 33 formed at corners of the horizontal portion and extending from the horizontal portion at least partially but not completely down at least two opposing side surfaces of the electrical component (e.g., fig. 13) and in continuous contact with the at least two opposing side surfaces of the electrical component from the horizontal portion to an end of the at least two vertical extensions to prevent lateral movement of the heat sink with respect to the electrical component (e.g., fig. 13), see figs. 1-20 and pages 1-9 for more details. Although the exact recitation “as measured by substantially a same distance as the heat sink extends beyond the footprint of the electrical component” of the instant claim is not explicitly stated by Kobayashi et al. in the related text, it appears that Fig. 13 shows having about the same distance. Therefore, the instant claim appears to be Prima Facie obvious over Fujino et al. Furthermore, the distance range of claims 14, 22 and 28 are considered to involve routine optimization while has been held to be within the level of ordinary skill in the art. As noted in In re Aller, the selection of reaction parameters such as thickness, temperature and concentration etc. would have been obvious: “Normally, it is to be expected that a change in temperature, or in concentration, or in both, would be an unpatentable modification. Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art...such ranges are termed Acritical ranges and the applicant has the burden of proving such criticality.... More particularly, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller 105 USPQ233, 255 (CCPA 1955). See also In re Waite 77 USPQ 586 (CCPA 1948); In re Scherl 70 USPQ 204 (CCPA 1946); In re Irmscher 66 USPQ 314 (CCPA 1945); In re Norman 66 USPQ 308 (CCPA 1945); In re Swenson 56 USPQ 372 (CCPA 1942); In re Sola 25 USPQ 433 (CCPA 1935); In re Dreyfus 24 USPQ 52 (CCPA 1934). Therefore, one of ordinary skill in the requisite art before the invention was made would have used any distance range suitable to the device of Fujino et al. in order to optimize the performance of the device. Re claim 15. The semiconductor device of claim 14, further including a thermal interface material 2 (e.g., fig. 13) disposed between the heat sink and electrical component. Re claim 19. The semiconductor device of claim 14, wherein the electrical component includes a flipchip (e.g., paragraphs 36, 37 etc.) semiconductor die. Re claim 34. The semiconductor device of claim 14, wherein the at least two vertical extensions 33 of the heat sink extending at least partially down and in contact with the at least two opposing side surfaces of the electrical component are 90 degrees with respect to a surface of the horizontal portion of the heat sink (fig. 13). Re claim 37. The semiconductor device of claim 14, wherein the at least two vertical extensions 33 are bent to 90 degrees from the horizontal portion of the heat sink (e.g., fig. 13). Response to Arguments Applicant's arguments filed 4/3/2026 have been fully considered but they are not persuasive for reasons herein above. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACK CHEN whose telephone number is (571)272-1689. The examiner can normally be reached Monday to Friday, 8am to 4pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J. Green can be reached at (571)270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JACK S CHEN/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Show 18 earlier events
Oct 09, 2025
Request for Continued Examination
Oct 12, 2025
Response after Non-Final Action
Oct 16, 2025
Response Filed
Feb 23, 2026
Non-Final Rejection mailed — §102, §103, §112
Apr 03, 2026
Response Filed
Apr 03, 2026
Response after Non-Final Action
Apr 16, 2026
Response Filed
Jul 14, 2026
Final Rejection mailed — §102, §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

7-8
Expected OA Rounds
77%
Grant Probability
82%
With Interview (+5.6%)
2y 11m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 576 resolved cases by this examiner. Grant probability derived from career allowance rate.

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