Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Response to Arguments
Applicant’s arguments with respect to claim(s) #1-10, 12-19, 22, 23, filed on 05/04/25, have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) #1, 2, 6, 23 are rejected under 35 U.S.C. 102(a)(2) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Chang et al., (U.S. Pub. No. 2020/0020785), hereinafter referred to as “Chang”.
Chang shows, with respect to claim #1, a method comprising: forming a first trench (fig. #8, item 151) and a second trench (fig. #8, item 251) in a base structure (fig. #8, item 100 and 200) (paragraph 0025), wherein the first trench has a first aspect ratio, and the second trench has a second aspect ratio lower than the first aspect ratio (fig. #10, item 151 and 251) (paragraph 0030); performing a deposition process to deposit a layer comprising: a first portion (fig. #8, item 151) extending into the first trench, wherein the first portion has a first thickness (fig. #9, item 156); and a second portion extending into the second trench, wherein the second portion has a second thickness (fig. #8, item 256) greater than the first thickness by a first difference (paragraph 0026); and performing an etch-back process to etch the layer, wherein after the etch-back process, the first portion has a third thickness, and the second portion has a fourth thickness (fig. #14, item 100 and 200), and wherein a second difference between the third thickness and the fourth thickness is smaller than the first difference (paragraph 0033-0035), wherein the first thickness and the third thickness (Below, fig. #Ex1, item 166 and FT1) are measured at a bottom of the first trench, and the second thickness (Below, fig. #Ex1, item D1) and the fourth thickness are measured at a bottom of the second trench (paragraph 0033-0035)
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Chang discloses the claimed invention except for explicitly stating that the thickness are different. It would have been obvious to one having ordinary skill in the art at the time the invention was made to understand that different size (different aspect ratios) trenches accrue different thicknesses within the trench body as the material is deposited within the trench area. Since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re A11er, 105 USPQ 233. Furthermore, Under U.S. patent case law, device characteristics can give patentable weight to method claims if they structurally define or limit how the method steps are performed. However, if a device characteristic merely describes the intended use or environment of a known device without changing the manipulative steps, it carries no patentable weight: MPEP 2111. (Evidence Supporting/Against Functional Relationships.)
Chang shows, with respect to claim #2, a method further comprising forming additional features (fig. #17, item 78, 80) over the first portion and the second portion of the layer, wherein at a time the additional features are formed, the fourth thickness is equal to the third thickness (paragraph 0052).
Chang shows, with respect to claim #6, a method further comprising forming the base structure comprising: forming a first dummy gate stack (fig. #3, item 30, fig. #7, item 130) (paragraph 0015, 0022) and a second dummy gate stack (fig. #7, item 230) on a first semiconductor region and a second semiconductor region, respectively (paragraph 0015, 0022); forming first gate spacers (fig. #7, item 238) and second gate spacers (fig. #7, item 238) on opposing sides of the first dummy gate stack and the second dummy gate stack (paragraph 0026); and removing the first dummy gate stack and the second dummy gate stack to form the first trench between the first gate spacers and the second trench between the second gate spacers (paragraph 0024).
Chang shows, with respect to claim #23, a method wherein the first thickness (Above, fig. #Ex1, item H1; Also, fig. #13, item 100) and the third thickness (Above, fig. #Ex1, item FT1) are horizontal portions of the first portion of the layer, and the second thickness (Below, fig. #Ex4, item ST4) and the fourth thickness (Below, fig. #Ex5, item FT5) are horizontal portions of the second portion of the layer (paragraph 0033-0035, 0037, 0039), and wherein the first portion (fig. #3, item 30) (paragraph 0015) and the second portion overlap a first semiconductor fin (fig. #3, item 24’) and a second semiconductor fin, respectively (paragraph 0015).
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Claim #3-5, 7 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al., (U.S. Pub. No. 2020/0020785), hereinafter referred to as “Chang” as shown in the rejection of claim #1 above and in view of Lilak et al., (U.S. Pub. No. 2020/0403033), hereinafter referred to as "Lilak".
Chang substantially shows the claimed invention as shown in the rejection of claim #1 above.
Chang, fails to show, with respect to claim #3, a method wherein the etch-back process is performed through an atomic layer etching process.
Lilak teaches, with respect to claim #3, a method wherein the etch-back process is performed through an atomic layer etching process (paragraph 0064).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #3, to modified the invention of Chang, with the modification so the invention of Lilak, which teaches, a method wherein the etch-back process is performed through an atomic layer etching process, to incorporate a structure with high selectivity, as compared to other surrounding materials such that the desired voids between conductive material layers may be defined/removed without damaging the surrounding structure, as taught by Lilak.
Chang, fails to show, with respect to claim #4, a method wherein the layer comprises a high-k dielectric layer, and the etch-back process comprises a fluorination cycle followed by a ligand exchange cycle.
Lilak teaches, with respect to claim #4, a method wherein the layer comprises a high-k dielectric layer, and the etch-back process comprises a fluorination cycle followed by a ligand exchange cycle (paragraph 0032).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #4, to modified the invention of Chang, with the modification of the invention of Lilak, which teaches, a method wherein the layer comprises a high-k dielectric layer, and the etch-back process comprises a fluorination cycle followed by a ligand exchange cycle, to incorporate a structure material to improve device performance, as taught by Lilak.
Chang fails to show, with respect to claim #5, a method wherein the layer comprises hafnium oxide, and the etch-back process is performed through atomic layer etching using SF4 and TiCl4 as process gases.
Lilac teaches, with respect to claim #5, a method wherein the layer comprises hafnium oxide, and the etch-back process is performed through atomic layer etching using SF4 and TiCl4 as process gases (paragraph 0063-0064).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #5, to modified the invention of Chang with the modification of the invention of Lilac, which teaches, a method wherein the layer comprises hafnium oxide, and the etch-back process is performed through atomic layer etching using SF4 and TiCl4 as process gases, to incorporate a structure with high selectivity to other surrounding materials such that the desired voids between conductive material layers may be defined without damaging the surrounding structure, as taught by Lilak.
Chang fails to show, with respect to claim #7, a method wherein the deposition process is performed through Atomic-Layer Deposition (ALD).
Lilak teaches, with respect to claim #7, a method wherein the deposition process is performed through Atomic-Layer Deposition (ALD) (paragraph 0052, 0067).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #7, to modified the invention of Chang, with the modification of the invention of Lilak, which teaches, a method wherein the deposition process is performed through Atomic-Layer Deposition (ALD), to incorporate a structural condition that would have enhanced isolation properties with minimal voids, as taught by Lilak.
//
Claim #8, 9, 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al., (U.S. Pub. No. 2021/0328030), hereinafter referred to as "Kim" and in view of Shroff et al., (U.S. Pub. No. 2012/0267758), hereinafter referred to as "Shroff".
Kim shows, with respect to claim #8, a method comprising: forming a first dummy gate stack (fig. #13, item 161) and a second dummy gate stack (fig. #13, item 162) on a first semiconductor region (fig. #13, item I) and a second semiconductor region (fig. #13, item II), respectively (paragraph 0127); forming first gate spacers (fig. #13, item 111) and second gate spacers (fig. #13, item 121) on opposing sides of the first dummy gate stack and the second dummy gate stack (paragraph 0033-0034, 0053-0054); removing the first dummy gate stack and the second dummy gate stack to form a first trench (fig. #15, item GT1) between the first gate spacers and a second trench (fig. #15, item GT2) between the second gate spacers (paragraph 0034, 0039, 0055-0056); depositing a first dielectric layer (fig. #16, item 112) extending into the first trench (paragraph 0037); depositing a second dielectric layer (fig. #16, item 122) extending into the second trench (paragraph 0053); and performing an etch-back process to simultaneously etch-back the first dielectric layer and the second dielectric layer and to reduce a thickness difference between the first dielectric layer and the second dielectric layer (fig. #17, item 112 and 122) (paragraph 0137-0138).
Kim substantially shows the claimed invention as shown in the rejection of claim #8 above.
Kim fails to show, with respect to claim #8, a method wherein performing an etch-back process to simultaneously etch-back the first dielectric layer and the second dielectric layer and to reduce a thickness difference between a first bottom portion of the first dielectric layer and a second bottom portion of the second dielectric layer, wherein the first bottom portion and the second bottom portion are at bottoms of the first trench and the second trench, respectively.
Shroff teaches, with respect to claim #8, a method wherein performing an etch-back process to simultaneously etch-back the first dielectric layer (trench #1, item 108) and the second dielectric layer (fig. #13, trench #110 & 112, item 108) (paragraph 0030, 0045, 0047) and to reduce a thickness difference between a first bottom portion of the first dielectric layer and a second bottom portion of the second dielectric layer, wherein the first bottom portion and the second bottom portion are at bottoms of the first trench and the second trench, respectively (paragraph 0045, 0047) .
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #8, to modified the invention of Kim with the modification of the invention of Shroff, which teaches, a method wherein performing an etch-back process to simultaneously etch-back the first dielectric layer and the second dielectric layer and to reduce a thickness difference between a first bottom portion of the first dielectric layer and a second bottom portion of the second dielectric layer, wherein the first bottom portion and the second bottom portion are at bottoms of the first trench and the second trench, respectively, to incorporate a structural condition that would provide the required decoupling capacitance at the bottom of the trench while the thickness of the sidewall dielectric layer is sufficient to electrically isolate the decoupling trench capacitor from adjacent active device operation, as taught by Shroff.
Kim shows, with respect to claim #9, a method wherein the first dielectric layer and the second dielectric layer are deposited in a common deposition process (paragraph 0137-0138).
Kim shows, with respect to claim #12, a method wherein the depositing the first dielectric layer (fig. #3, item 112) and the depositing the second dielectric layer (fig. #3, item 122) comprise depositing high-k dielectric layers (paragraph 0037).
Kim shows, with respect to claim #13, a method wherein the depositing the first dielectric layer and the depositing the second dielectric layer comprise depositing a hafnium oxide layer (paragraph 0037).
//
Claim #10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al., (U.S. Pub. No. 2021/0328030), hereinafter referred to as "Kim", as shown in the rejection of claim #9 above and in view of Lilak et al., (U.S. Pub. No. 2020/0403033), hereinafter referred to as "Lilak".
Kim substantially shows the claimed invention as shown in the rejection of claim #9 above.
Kim shows, with respect to claim #10, a method and wherein a first thickness of the first dielectric layer (fig. #16, item 112) at a first bottom of the first trench is smaller than a second thickness of the second dielectric layer (fig. #16, item 122) at a second bottom of the second trench, and after the etch-back process, the first dielectric layer and the second dielectric layer has a substantially same thickness (fig. #16, item 112 and 122) (paragraph 0130).
Kim fails to show, with respect to claim #10, a method wherein the etch-back process is performed through an atomic layer etching process.
Lilak teaches, with respect to claim #10, a method wherein the first dielectric layer and the second dielectric layer are deposited in an atomic layer deposition process (paragraph 0064).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #10, to modified the invention of Song, with the modification so the invention of Lilak, which teaches, a method wherein the first dielectric layer and the second dielectric layer are deposited in an atomic layer deposition process, to incorporate a structure with high selectivity, as compared to other surrounding materials such that the desired voids between conductive material layers may be defined/removed without damaging the surrounding structure, as taught by Lilak.
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Claim #14, 15 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al., (U.S. Pub. No. 2021/0328030), hereinafter referred to as "Kim", as shown in the rejection of claim #13 above and in view of Lilak et al., (U.S. Pub. No. 2020/0403033), hereinafter referred to as "Lilak".
Kim substantially shows the claimed invention as shown in the rejection of claim #13 above.
Kim fails to show, with respect to claim #14, a method wherein the etch-back process is performed through an atomic layer etching process.
Lilak teaches, with respect to claim #14, a method wherein the first dielectric layer and the second dielectric layer are deposited in an atomic layer deposition process (paragraph 0064).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #14, to modified the invention of Kim, with the modification so the invention of Lilak, which teaches, a method wherein the first dielectric layer and the second dielectric layer are deposited in an atomic layer deposition process, to incorporate a structure with high selectivity, as compared to other surrounding materials such that the desired voids between conductive material layers may be defined/removed without damaging the surrounding structure, as taught by Lilak.
Kim substantially shows the claimed invention as shown in the rejection of claim #14 above.
Kim fails to show, with respect to claim #15, a method wherein the atomic layer etching process comprises a fluorination reaction and a ligand exchange reaction.
Lilak teaches, with respect to claim #15, a method wherein the atomic layer etching process comprises a fluorination reaction and a ligand exchange reaction (ALE) (paragraph 0064).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #15, to modified the invention of Kim, with the modification so the invention of Lilak, which teaches, a method wherein the atomic layer etching process comprises a fluorination reaction and a ligand exchange reaction, to incorporate a structure with high selectivity, as compared to other surrounding materials such that the desired voids between conductive material layers may be defined/removed without damaging the surrounding structure, as taught by Lilak.
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Claim #16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al., (U.S. Pub. No. 2020/0020785), hereinafter referred to as "Chang" and in view of Lilac et al., (U.S. Pub. No. 2020/0403033), hereinafter referred to as "Lilac".
Chang shows, with respect to claim #16, method comprising: forming a first dummy gate stack (fig. #3, item 30) on a first portion of a first protruding semiconductor fin (fig. #3, item 30) (paragraph 0015); removing a second portion of the first protruding semiconductor fin to form a recess (paragraph 0017); forming an epitaxy region from the recess (paragraph 0018); forming a contact etch stop layer (fig. #6, item 46) and an inter-layer dielectric on the epitaxy region; removing the first dummy gate stack to form a first trench, wherein the first portion of the first protruding semiconductor fin is exposed (paragraph 0011, 0040); forming an interlayer dielectric (fig. #6, item 48) on the first portion of the first protruding semiconductor fin (paragraph 0021); depositing a first high-k dielectric layer extending into the first trench (paragraph 0026).
Chang substantially shows the claimed invention as shown in the rejection of claim #16 shown above.
Chang fails to show, with respect to claim #16, a method wherein performing an etch-back process using atomic layer etching to thin down the first high-k dielectric layer.
Lilac teaches, with respect to claim #16, a method wherein performing an etch-back process using atomic layer etching to thin down the first high-k dielectric layer (paragraph 0063-0064).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #16, to modified the invention of Chang, with the modification so the invention of Lilac, which teaches, a method wherein performing an etch-back process using atomic layer etching to thin down the first high-k dielectric layer, to incorporate a method that would allow structurally critical etching within the dimensions of a trench area and to incorporate a structure with high selectivity to other surrounding materials such that the desired voids between conductive material layers may be defined without damaging the surrounding structure, as taught by Lilac.
Chang shows, with respect to claim #17, a method further comprising: forming a second dummy gate stack (fig. #3, item 30) on a second protruding semiconductor fin (fig. #3, item 30) (paragraph 0015); removing the second dummy gate stack to form a second trench (paragraph 0017), wherein the second protruding semiconductor fin is exposed (paragraph 0011, 0040); and depositing a second high-k dielectric layer extending into the second trench, wherein the etch-back process further thins down the second high-k dielectric layer, and wherein before the etch-back process, the first high-k dielectric layer and the second high-k dielectric layer have a first thickness difference (paragraph 0026), and after the etch-back process, the first high-k dielectric layer and the second high-k dielectric layer have a second thickness difference smaller than the first thickness difference (paragraph 0034-0035).
Chang shows, with respect to claim #18, a method wherein the etch-back process is stopped before the first high-k dielectric layer is fully removed (paragraph 0034-0035).
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Claim #19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al., (U.S. Pub. No. 2020/0020785), hereinafter referred to as "Chang", as shown in the rejection of claim #16 above and in view of Lilak et al., (U.S. Pub. No. 2020/0403033), hereinafter referred to as "Lilak".
Chang substantially shows the claimed invention as shown in the rejection of claim #16 above.
Chang fails to show, with respect to claim #19, a method wherein the atomic layer etching comprises: pulsing and purging SF4; and pulsing and purging TiCl4.
Lilak teaches, with respect to claim #19, a method wherein the atomic layer etching comprises: pulsing and purging SF4; and pulsing and purging TiCl4 (paragraph 0063-0064).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #19, to modified the invention of Chang, with the modification so the invention of Lilak, which teaches, a method wherein the atomic layer etching comprises: pulsing and purging SF4; and pulsing and purging TiCl4, to incorporate a structure vapor phase etch processes may be chosen so as to have high selectivity to other surrounding materials such that the desired voids between conductive material layers may be defined without damaging the surrounding structure, as taught by Lilak.
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Claim #21 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al., (U.S. Pub. No. 2020/0020785), hereinafter referred to as “Chang”, as shown in the rejection of claim #1 above and in further view of Shroff et al., (U.S. Pub. No. 2012/0267758), hereinafter referred to as "Shroff".
Chang substantially shows the claimed invention as shown in the rejection of claim #1 above.
Chang fails to show, with respect to claim 21, a method wherein the first thickness and the third thickness are measured at a bottom of the first trench, and the second thickness and the fourth thickness are measured at a bottom of the second trench.
Shroff teaches, with respect to claim #21, a method wherein the first thickness (fig. #4, item 20; Below, Fig. #Ex2, item ST) and the third thickness (Below, Fig. #Ex3, item TT) are measured at a bottom (paragraph 0029) of the first trench (fig. #13, item 110), and the second thickness (fig. #4, item 20; Below, Fig. #Ex2, item ST) and the fourth thickness (Below, Fig. #Ex3, item FT2) are measured at a bottom of the second trench (fig. #13, item 112) (paragraph 0030, 0045, 0047) .
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It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #21, to modified the invention of Chang with the modifications of Shroff, which teaches, a method wherein the first thickness and the third thickness are measured at a bottom of the first trench, and the second thickness and the fourth thickness are measured at a bottom of the second trench, to incorporate a structural condition that would provide the required decoupling capacitance at the bottom of the trench while the thickness of the sidewall dielectric layer is sufficient to electrically isolate the decoupling trench capacitor from adjacent active device operation, as taught by Shroff.
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Claim #22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al., (U.S. Pub. No. 2020/0020785), hereinafter referred to as "Chang" as modified by Lilac et al., (U.S. Pub. No. 2020/0403033), hereinafter referred to as "Lilac" as shown in the rejection of claim #16 above and in further view of Shroff et al., (U.S. Pub. No. 2012/0267758), hereinafter referred to as "Shroff".
Chang as modified by Lilac substantially shows the claimed invention as shown in the rejection of claim #16 above.
Chang as modified by Lilac fails to show, with respect to claim 22, a method wherein the first thickness and the third thickness are measured at a bottom of the first trench, and the second thickness and the fourth thickness are measured at a bottom of the second trench.
Shroff teaches, with respect to claim #22, a method wherein in the etch-back process, a portion of the first high-k dielectric layer at a bottom of the first trench is thinned down (paragraph 0030, 0045, 0047) .
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #22, to modified the invention of Chang as modified by the invention of Lilac, with the modifications of Shroff, which teaches, a method wherein in the etch-back process, a portion of the first high-k dielectric layer at a bottom of the first trench is thinned down, to incorporate a structural condition that would provide the required decoupling capacitance at the bottom of the trench while the thickness of the sidewall dielectric layer is sufficient to electrically isolate the decoupling trench capacitor from adjacent active device operation, as taught by Shroff.
EXAMINATION NOTE
The rejections above rely on the references for all the teachings expressed in the text of the references and/or one of ordinary skill in the art would have reasonably understood or implied from the texts of the references. To emphasize certain aspects of the prior art, only specific portions of the texts have been pointed out. Each reference as a whole should be reviewed in responding to the rejection, since other sections of the same reference and/or various combinations of the cited references may be relied on in future rejections in view of amendments.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Andre’ Stevenson whose telephone number is (571) 272 1683 (Email Address, Andre.Stevenson@USPTO.GOV). The examiner can normally be reached on Monday through Friday from 7:30 am to 4:30 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached on 571-272 2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Andre’ Stevenson Sr./
Art Unit 2899
06/17/2026
/ZANDRA V SMITH/ Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights