DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
1. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/14/2025 has been entered.
Status of the Application
2. Acknowledgement is made of the amendment received on 10/14/2025. Claims 1-20 are pending in this application.
Claim Objections
3. The claims are objected because of the following reasons:
Re claim 1, line 6: after “extending” insert --from--.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1, 4-7, 9-14 are rejected under 35 U.S.C. 103 as being unpatentable over Pogge et al. (US 2006/0121690) in view of Pogge et al. (US 2004/0097002) and
Kwon et al. (US 2004/0097002).
Re claim 1, Pogge90 teaches, Figs. 1A-1E, [0015-0022], a method comprising:
-forming (*) a first opening in a first bonding layer (26) of a first integrated circuit structure (Fig. 1D);
-patterning a second opening (13) in a second bonding layer (1) of a second integrated circuit structure (Fig. 1C);
-forming a connector (27) in the first opening, wherein the connector (27) comprising a single layer of uniform material extending a first lateral surface (2a) of the first bonding layer (26) to above a second lateral surface (opposite 2a) of the first bonding layer (26), wherein a width of the connector (27) is less than a width of the second opening (13);
-forming a contact pad (14) on a sidewall and a bottom surface of the second opening (13); and
-after the forming the connector (27) and after the forming the contact pad (14), bonding the first and the second integrated circuit structures (Fig.1E), wherein bonding the first and the second integrated circuit structures comprises:
bonding the first bonding layer (26) to the second bonding layer (1) wherein the second lateral surface (opposite 2a) of the first bonding layer (26) faces the second bonding layer (1), and wherein the first lateral surface (2a) of the first bonding layer (26) is distal to the second integrated circuit structure (Fig. 1E); and
bonding the connector (27) to the contact pad (14), wherein the connector (27) is partially disposed in the second opening (13), wherein the single layer of the connector (27) contacts the contact pad (14).
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Pogge90 does not explicitly teach patterning a first opening in the first bonding layer.
Pogge teaches, Fig. 8A, [0032, 0033], patterning a first opening in the first bonding layer (83).
As taught by Pogge, one of ordinary skill in the art would utilize & modify the above teaching to obtain step of patterning a first opening in the first bonding layer as claimed, because it is known as common technique to form a connector/contact through a bonding layer to improve electrical connection.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Pogge in combination with Pogge90 due to above reason.
Pogge90/Pogge does not explicitly teach wherein the single layer of uniform material of the connector physically contacts the contact pad.
Kwon teaches, Fig. 5A, [0046], the single layer of uniform material of the connector (122p) physically contacts the contact pad (206u).
As taught by Kwon, one of ordinary skill in the art would utilize & modify the above teaching to obtain the single layer of uniform material of the connector physically contacts the contact pad as claimed, because it aids in achieving structure having improved physical and electrical characteristics.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Kwon in combination with Pogge90/Pogge due to above reason.
Re claim 4, Pogge90 teaches, Fig. 1E, after forming the contact pad (14), a lateral dimension of the second opening (13) is greater than a lateral dimension of the connector (27) in the first opening.
Re claim 5, Pogge90 teaches, Figs. 1C-E, forming the contact pad (14) comprises forming the contact pad (14) to surround a portion of the second opening (13), and wherein forming the connector (27) comprises controlling an area of a portion of the connector (27 with 28) extending past a lateral surface of the first bonding layer (1) to be about 95% to about 100% of an area of the portion of the second opening (13) surrounded by the contact pad (14) (e.g., based on temperature & pressure, solder either partially or completely fills opening 13) [0022].
Re claim 6, Pogge90 teaches, Fig. 1E, bonding the first and the second integrated circuit structures comprises forming an air gap in the second opening (13) (e.g., result of partially filled solder) [0022].
Re claim 7, in combination cited above, Pogge teaches, Figs. 7C & 8A, [0032], patterning the first opening exposes a first conductive element (82) in the first integrated circuit structure, and wherein patterning the second opening (74) exposes a second conductive element (57) in the second integrated circuit structure. (See also teaching in Pogge90, Figs. 1C & 1D).
Re claim 9, Pogge90 teaches, under BRI, Figs. 1A-1E, [0015-0022], a method comprising:
-forming a first contact (27, 28) protruding from a first insulating layer (26) on a first substrate (2), wherein the first contact comprises a first conductive layer (27), wherein the first conductive layer (27) is a single layer of uniform material that extends from within a first recess in the first insulating layer (26) to protruding from the first insulating layer (26);
-forming a contact pad (14) in a second recess (13) in a second insulating layer (*) (1) on a second substrate (15), wherein a width of the second recess (13) is greater than a greatest width of the first conductive layer (27); and
-bonding the first substrate (2) and the second substrate (15) by inserting the first contact (27, 28) protruding from the first insulating layer (26) into the second recess (13) in the second insulating layer (1), wherein the first conductive layer (27) of the first contact directly contacts (contact in straight line via 28) the contact pad (14).
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Note: directly contact # physically contact.
Pogge90 does not teach (*) a second insulating layer, and wherein the bonding deforms the first conductive layer.
Pogge teaches, Figs. 8A-B, [0031-0033], a second insulating layer (73), and wherein the bonding deforms the first conductive layer (85).
As taught by Pogge, one of ordinary skill in the art would utilize & modify the above teaching to obtain t a second insulating layer, and wherein the bonding deforms the first conductive layer as claimed, because it aids in achieving thinner structure having direct bonding & improved electrical connection.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Pogge in combination with Pogge90 due to above reason.
Pogge90/Pogge does not explicitly teach wherein the first conductive layer extends from a first lateral surface of the first insulating layer to protruding from a second lateral surface of the first insulating layer.
Kwon teaches, Fig.5A, [0046], the first conductive layer (122p) extends from a first lateral surface of the first insulating layer (130c) to protruding from a second lateral surface of the first insulating layer (130c).
As taught by Kwon, one of ordinary skill in the art would utilize & modify the above teaching to obtain the first conductive layer extends from a first lateral surface of the first insulating layer to protruding from a second lateral surface of the first insulating layer as claimed, because it aids in achieving structure having improved physical and electrical characteristics.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Kwon in combination with Pogge90/Pogge due to above reason.
Re claim 10, in combination cited above, Pogge teaches, Fig. 9B, the bonding further comprises bonding the first insulating layer (93) to the second insulating layer (63).
Re claims 11 & 12, in combination cited above, Pogge teaches the bonding comprises annealing (e.g., high temperature lamination process); wherein the annealing is performed at temperature greater than a melting temperature of first contact (e.g., solder 95 is caused to flow) [0036].
Re claim 13, Pogge90 teaches after bonding a gap exist in the second recess (e.g., solder 28 partially fills opening 13) [0022].
Re claim 14, in combination cited above, Pogge teaches, Fig.9B, after the bonding the first contact (94, 95) completely covers a surface of the contact pad (65) along a bottom of the second recess.
5. Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Pogge90 as modified by Pogge/Kwon as applied to claim 1 above, and further in view of Menard et al. (US 2012/0115262).
The teachings of Pogge90/Pogge/Kwon have been discussed above.
Re claim 2, Pogge90 teaches, Figs. 1C-E, [0022], bonding the first and the second integrated circuit structures (Fig. 1E) further comprises:
contacting the first bonding layer to the second bonding layer while heating the first integrated circuit structure at a first temperature (consider room temperature); and
performing an annealing process (e.g., bonding & lamination process) at a second temperature (200-400C) on the first and the second integrated circuit structures after contacting the first bonding layer (26) to the second bonding layer (1).
Pogge90/Pogge/Kwon does not explicitly teach wherein the first temperature is sufficient to form hydrogen bonds between the first bonding layer and the second bonding layer.
Menard teaches, [0060], wherein the first temperature is sufficient to form hydrogen bonds between the first bonding layer and the second bonding layer (e.g., between two solar cells).
As taught by Menard, one of ordinary skill in the art would utilize & modify the above teaching to obtain the first temperature is sufficient to form hydrogen bonds between the first bonding layer and the second bonding layer as claimed, because it aids in improving bond strength in the formed structure with being annealed.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Menard in combination with Pogge90/Pogge/Kwon due to above reason.
Re claim 3, Pogge90 teaches the first temperature (e.g., room temperature) is lower than a melting temperature of the connector (27, 28), and wherein the second temperature is at least as high as the melting temperature of the connector (of solder 28, caused to flow) [0022].
6. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Pogge90 as modified by Pogge/Kwon as applied to claim 1 above, and further in view of Sadaka (US 2012/0153484).
The teachings of Pogge90/Pogge/Kwon have been discussed above.
Re claim 8, Pogge90 teaches, Fig. 1C, forming a conformal conductive layer (14) over the second bonding layer and in the second opening (13).
Pogge90/Pogge/Kwon does not explicitly teach performing a planarization to remove portions of the conformal conductive layer over the second bonding layer.
Sadaka teaches CMP process to remove excess material (Figs. 3B-C, [0070]).
As taught by Sadaka, one of ordinary skill in the art would utilize & modify the above teaching to perform a planarization to remove portions of the conformal conductive layer over the second bonding layer as claimed, because CMP process is a known & widely used process in the art to remove and achieve desired film thickness.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Sadaka in combination with Pogge90/Pogge/Kwon due to above reason.
7. Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Pogge90 as modified by Pogge/Kwon as applied to claim 9 above, and further in view of Farooq et al. (US 2010/0264551).
The teachings of Pogge90/Pogge/Kwon have been discussed above.
Re claim 15, Pogge90/Pogge/Kwon does not explicitly teach the first substrate comprises an integrated circuit, wherein the integrated circuit comprises a semiconductor substrate and an interconnect structure, wherein after bonding the interconnect structure is between the semiconductor substrate and the second substrate, further comprising: after the bonding, forming a through via through the semiconductor substrate to a metal interconnect in the interconnect structure.
Faroog teaches, Figs. 6-7, claim 11, [0005, 0013, 0019], the first substrate comprises an integrated circuit (108, 106, 104), wherein the integrated circuit comprises a semiconductor substrate (e.g., a first IC device having a semiconductor substrate) and an interconnect structure (110 & wirings), wherein after bonding the interconnect structure is between the semiconductor substrate (of 1st IC) and the second substrate (of 2nd IC or 202), further comprising: after the bonding, forming a through via (306) through the semiconductor substrate to a metal interconnect in the interconnect structure (110 & wirings).
As taught by Faroog, one of ordinary skill in the art would utilize & modify the above teaching to obtain the first substrate comprises an integrated circuit, wherein the integrated circuit comprises a semiconductor substrate and an interconnect structure, wherein after bonding the interconnect structure is between the semiconductor substrate and the second substrate, further comprising: after the bonding, forming a through via through the semiconductor substrate to a metal interconnect in the interconnect structure as claimed, because it aids in achieving a desired 3D wafer stack having multiple IC devices at lower cost and greater integration.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Faroog in combination with Pogge90/Pogge/Kwon due to above reason.
Allowable Subject Matter
8. Claims 16-20 are allowed.
The allowable subject matter includes steps of “forming a first contact in the first opening, the first contact extending further from the first substrate than a distal surface of the first insulating layer, the first contact comprising a single conductive layer extending from a distal end of the first contact to a point closer to the first integrated circuit structure than an outer surface of the first insulating layer, the distal end of the first contact being an end furthest from the first integrated circuit structure;
forming a second insulating layer on a second integrated circuit structure, the second integrated circuit structure comprising a second substrate and a second interconnect structure on a first side of the second substrate;
forming a second opening in the second insulating layer, the second opening exposing a second conductive feature of the second interconnect structure, a width of the second opening being greater than a greatest width of the first contact;
forming a second contact in the second opening, the second contact having a recessed upper surface; and
after the forming the first contact and after forming the second contact, electrically coupling the first contact and the second contact by inserting the first contact into the recessed upper surface of the second contact, wherein the first contact contacts the second contact, wherein the single conductive layer expands during the electrically coupling the first contact and the second contact” (claim 16).
Response to Arguments
9. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
Conclusion
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EVA MONTALVO can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DUY T NGUYEN/Primary Examiner, Art Unit 2818 3/16/26