DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 28, 2026 has been entered.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed on January 28, 2026. Claims 10, 15, 17-18 and 20-21 have been amended. New claims 30-34 have been added. Claims 1-9, 14 and 26-29 have been canceled. Currently, claims 10-13, 15-25 and 30-34 are pending.
Response to Arguments
Applicant’s arguments with respect to claims 10, 15 and 21 have been considered but are moot as applied to the newly added claim limitations because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 25 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 25, the claim recites, “a first depth of the first layer relative to a center of the source/drain region, at a height of the third nanostructure channel, is greater relative to a second depth of the first layer relative to the center of the source/drain region at a height of the second nanostructure channel”, which does not have support in the disclosure. The specification and Figure 6 show the first epitaxial source/drain layer 504 adjacent the second nanostructure channel 208b and the third nanostructure channel 208c. As shown, the first layer 504 extends farther toward the center of the source/drain region at the height of the third nanostructure channel 208c than at the height of the second nanostructure channel 208b. Accordingly, the illustrated depth associated with the second nanostructure channel 208b (D2) is greater than the depth associated with the third nanostructure channel 208c (D1) that is, D2>D1.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 30-31 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
Regarding claim 30, the claim recites, “the exterior surface of the first inner spacer” which is indefinite and lacks antecedent basis. As per claim 10 each of the plurality of inner spacers comprise a first exterior surface and a second exterior surface. It is not clear if the “exterior surface” is the first exterior surface, the second exterior surface or any other exterior surface of the inner spacer.
The claim further recites, “the first nanostructure channel” which is indefinite and lacks antecedent basis.
Claim 31 depends upon claim 30 and does not rectify the problem therefore, it is also rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10-12 and 30-31 are rejected under 35 U.S.C. 103 as being unpatentable over Yeh et al. (US 2021/0249506 A1; hereafter Yeh) in view of Jang et al. (US 2020/0220018 A1; hereafter Jang), Bauer et al. (US 2011/0117732 A1; hereafter Bauer) and Young et al. (US 2021/0035870 A1; hereafter Young).
Regarding claim 10, Yeh teaches a method for forming a semiconductor device (see e.g., nanosheet-based structure 100, Figures 1-13), comprising:
forming a fin structure comprising a first portion above a substrate and a second portion over the first portion (see e.g., fin structure comprising a sub-fin 102A above a substrate 102 and a nanosheet stack 130 over the sub-fin 102A, Para [0038], Figure 1);
forming a source/drain recess in the second portion of the fin structure (see e.g., forming source/drain trenches 602 in the nanosheet stack 130, Para [0046], Figure 6),
wherein the second portion includes a plurality of sacrificial layers and a plurality of nanostructure channels that are arranged in an alternating manner (see e.g., the nanosheet stack 130 includes an alternating series of SiGe sacrificial nanosheet layers 122, 124, 126, 128 and Si nanosheet layers 114, 116, 118, Para [0035], Figure 1);
laterally etching the plurality of sacrificial layers through the source/drain recess to form cavities between end portions of the plurality of nanostructure channels (see e.g., laterally etching, to partially remove end regions of the sacrificial nanosheet regions 122, 124, 126, 128 to form inner spacer cavities 1002 through source/drain trenches 602, Para [0051], Figure 10);
forming, between the plurality of nanostructure channels, a gate structure and a plurality of inner spacers (see e.g., forming inner spacers 1102 in the cavities 1002 formed in the end regions of the sacrificial nanosheets 122, 124, 126, 128. These sacrificial nanosheet layers 122, 124, 126, 128 are removed and replaced with a HKMG structure 1302. The inner spacers 1102 are between the channel nanosheets 114, 116, 118, and the HKMG structure 1302, Paras [0052], [0055] – [0057], Figures 11,12 and 13);
….form a … layer of a source/drain region on sidewalls of the source/drain recess, wherein each of the plurality of inner spacers comprises a first exterior surface, entirely interfacing with a first portion of the gate structure, and a second exterior surface, opposite from the first exterior surface, entirely interfacing with the … layer of the source/drain region,
forming a … layer of the source/drain region on the … layer (see e.g., doped source/drain region 1202/1204 are formed in the source/drain trenches 602. The inner spacer 1102 comprises a first exterior surface entirely interfacing portion of the HKMG structure 1302 and a second exterior surface opposite the first exterior surface entirely interfacing the source/drain region 1202/1204, Para [0053], Figure 13).
Yeh does not explicitly teach
“performing a plurality of deposition and etch cycles to form a first layer of a source/drain region on sidewalls of the source/drain recess”
In a similar field of endeavor Bauer teaches forming epitaxial semiconductor material in recessed source/drain regions using repeated deposition and etch cycles. Bauer teaches that a deposition phase and an etch phase constitute a selective formation cycle and that cycle may be repeated two or more times until a desired thickness of epitaxial material is obtained in a recessed source/drain region.
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to employ cyclic deposition and etch epitaxial process to permit controlled selective epitaxial growth in a source/drain recess and allow the desired epitaxial thickness to be progressively obtained while selectively removing undesired or lower quality deposited material.
Yeh does not explicitly teach
“.. form a first layer of a source/drain region on sidewalls of the source/drain recess, wherein each of the plurality of inner spacers comprises …, a second exterior surface, ….., entirely interfacing with the first layer of the source/drain region,
forming a second layer of the source/drain region on the first layer”.
In a similar field of endeavor Jang teaches
….form a first layer of a source/drain region on sidewalls of the source/drain recess (see e.g., source/drain region 150b in semiconductor device 100b, a first epitaxial layer 152b may be disposed as a single layer extending along side surfaces of first to third channel layers 141, 142, and 143 of a channel structure 140 and side surfaces of internal spacer layers 130 and forming a lower surface of the source/drain region 150b at a lower end, Para [0060], Figures 7-8), wherein each of the plurality of inner spacers comprises …, a second exterior surface, ….., entirely interfacing with the first layer of the source/drain region (see e.g., one of the exterior surface of inner spacers 130 entirely interfacing the first epitaxial layer 152b, Figures 7-8),
forming a second layer of the source/drain region on the first layer (see e.g., second epitaxial layer 154b formed on first epitaxial layer 152b, Para [0060], Figures 7-8).
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to implement Jang’s teachings of .. form a first layer of a source/drain region on sidewalls of the source/drain recess, wherein each of the plurality of inner spacers comprises …, a second exterior surface, ….., entirely interfacing with the first layer of the source/drain region, forming a second layer of the source/drain region on the first layer in the method of Yeh to optimize source/drain boundaries allowing the critical interface adjacent to the channel ends and inner spacers to be independently controlled and optimized for enhanced electrical performance.
Yeh does not explicitly teach
“wherein each of the first exterior surface and the second exterior surface is curved;”
In a similar field of endeavor Young teaches
wherein each of the first exterior surface and the second exterior surface is curved (see e.g., the inner spacer 206A has a curved and recessed surface 420 facing the epitaxial source/drain features 210A and a concave surface 460 protruding towards the gate structure 250A, Paras [0056] – [0057], Figures 20-22);
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to implement Jung’s teachings of wherein each of the first exterior surface and the second exterior surface is curved in the method of Yeh as the curved profile provides a more favorable interface geometry for epitaxial growth and reduces the likelihood of incomplete fill, voids or seams in the source/drain region.
Regarding claim 11, Yeh, as modified by Bauer, Jang and Young, teaches the limitations of claim 10 as mentioned above. Yeh does not explicitly teach
“wherein performing a deposition and etch cycle of the plurality of deposition and etch cycles comprises:
performing a deposition operation using one or more silicon precursors; and
performing, after the deposition operation, an etch operation using hydrochloric acid (HCL)”.
In a similar field of endeavor Bauer teaches
wherein performing a deposition and etch cycle of the plurality of deposition and etch cycles comprises (see e.g., selective formation cycle including a deposition phase and an etch phase, Para 0054]):
performing a deposition operation using one or more silicon precursors; and (see e.g., During the first deposition phase, a pulse of a silicon-source vapor is introduced. The silicon-source vapor may be selected from silane (SiH.sub.4), dichlorosilane or DCS (SiCl.sub.2H.sub.2), disilane (Si.sub.2H.sub.6), monochlorodisilane or MCDS (Si.sub.2H.sub.5Cl), dichlorodisilane or DCDS (Si.sub.2H.sub.4Cl.sub.2), trisilane (Si.sub.3H.sub.8), and 2,2-dichlorotrisilane, Para [0047])
performing, after the deposition operation, an etch operation using hydrochloric acid (HCL) (see e.g., the etchant is comprised of a chlorine source, such as HCl or Cl.sub.2, Para [0055]).
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to implement Bauer’s teachings of wherein performing a deposition and etch cycle of the plurality of deposition and etch cycles comprises: performing a deposition operation using one or more silicon precursors; and performing, after the deposition operation, an etch operation using hydrochloric acid (HCL) in the method of Yeh for selective formation of high-quality epitaxial semiconductor material.
Regarding claim 12, Yeh, as modified by Bauer, Jang and Young, teaches the limitations of claim 11 as mentioned above. Yeh does not explicitly teach
“wherein the one or more silicon precursors comprise at least one of:
dichlorosilane (DCS), or silicon tetrahydride (SiH4)”.
In a similar field of endeavor Bauer teaches
wherein the one or more silicon precursors comprise at least one of:
dichlorosilane (DCS), or silicon tetrahydride (SiH4) (see e.g., During the first deposition phase, a pulse of a silicon-source vapor is introduced. The silicon-source vapor may be selected from silane (SiH.sub.4), dichlorosilane or DCS (SiCl.sub.2H.sub.2), disilane (Si.sub.2H.sub.6), monochlorodisilane or MCDS (Si.sub.2H.sub.5Cl), dichlorodisilane or DCDS (Si.sub.2H.sub.4Cl.sub.2), trisilane (Si.sub.3H.sub.8), and 2,2-dichlorotrisilane, Para [0047]).
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to implement Bauer’s teachings of wherein the one or more silicon precursors comprise at least one of: dichlorosilane (DCS), or silicon tetrahydride (SiH4) in the method of Yeh for selective formation of high-quality epitaxial semiconductor material.
Regarding claim 30, Yeh, as modified by Bauer, Jang and Young, teaches the limitations of claim 10 as mentioned above. Yeh further teaches
wherein the plurality of inner spacers comprises a first inner spacer residing below the first nanostructure channel (see e.g., the plurality of inner spacers 1102 comprises a first inner spacer below the first channel nanosheet 114, Figure 13),
Yeh does not explicitly teach
“wherein, in a cross section of the semiconductor device, the first layer of the source/drain region has a first width and a second width,
wherein the first width is measured from the exterior surface of the first inner spacer to a first portion of an exterior surface of the first layer of the source/drain region,
and wherein the second width is greater than the first width and is measured from an exterior surface of the first nanostructure channel to a second portion of the exterior surface of the first layer of the source/drain region”.
In a similar field of endeavor Jang teaches
wherein, in a cross section of the semiconductor device, the first layer of the source/drain region has a first width and a second width (see e.g., the first epitaxial layer 152b has a third maximum thickness T3 and a fifth maximum thickness T5, Para [0062], Figures 7-8),
wherein the first width is measured from the exterior surface of the first inner spacer to a first portion of an exterior surface of the first layer of the source/drain region (see e.g., the fifth thickness T5 from the exterior surface of the inner spacer to the exterior surface of the first epitaxial layer 152b, Para [0062], Figures 7-8),
and wherein the second width is greater than the first width and is measured from an exterior surface of the first nanostructure channel to a second portion of the exterior surface of the first layer of the source/drain region (see e.g., third thickness T3 from the exterior surface of the channel layer 141 to the exterior surface of the first epitaxial layer 152b. The fifth thickness T5 is less than the third thickness T3, Para [0062], Figures 7-8).
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to implement Jang’s teachings of wherein, in a cross section of the semiconductor device, the first layer of the source/drain region has a first width and a second width,
wherein the first width is measured from the exterior surface of the first inner spacer to a first portion of an exterior surface of the first layer of the source/drain region,
and wherein the second width is greater than the first width and is measured from an exterior surface of the first nanostructure channel to a second portion of the exterior surface of the first layer of the source/drain region in the method of Yeh as it would be a matter of routine optimization to enhance structural integrity and performance of the semiconductor device.
Regarding claim 31, Yeh, as modified by Bauer, Jang and Young, teaches the limitations of claim 30 as mentioned above. Yeh does not explicitly teach
“wherein the first layer of the source/drain region comprises a curved segment that comprises the first width and the second width,
wherein, in the cross section of the semiconductor device, the curved segment has a first end, within a top surface and a bottom surface of the first inner spacer, and a second end, within a top surface and a bottom surface of a second inner spacer of the plurality of inner spacers, wherein:
the second inner spacer resides on the first nanostructure channel,
the first width is measured relative the first end, and
the second width is measured relative to a middle portion of the curved segment”.
In a similar field of endeavor Jang teaches
wherein the first layer of the source/drain region comprises a curved segment that comprises the first width and the second width (see e.g., curved segment of the first epitaxial layer 152b as shown in annotated Figure 8),
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Annotated Figure 8, Jang
wherein, in the cross section of the semiconductor device, the curved segment has a first end, within a top surface and a bottom surface of the first inner spacer (see e.g., first end of the curved segment within a top surface and bottom surface of the inner spacer as shown in the annotated Figure 8), and a second end, within a top surface and a bottom surface of a second inner spacer of the plurality of inner spacers (see e.g., second end of the curved segment within the top surface and bottom surface of the inner spacer as shown in annotated Figure 8), wherein:
the second inner spacer resides on the first nanostructure channel (see e.g., inner spacer over the channel nanosheet 142 as shown in annotated Figure 8),
the first width is measured relative the first end, and (see e.g., the fifth thickness T5 is measured relative the first end as shown in annotated Figure 8)
the second width is measured relative to a middle portion of the curved segment (see e.g., the third thickness T3 is measured relative to a middle portion of the curved segment as shown in annotated Figure 8).
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to implement Jang’s teachings of wherein the first layer of the source/drain region comprises a curved segment that comprises the first width and the second width, wherein, in the cross section of the semiconductor device, the curved segment has a first end, within a top surface and a bottom surface of the first inner spacer, and a second end, within a top surface and a bottom surface of a second inner spacer of the plurality of inner spacers, wherein: the second inner spacer resides on the first nanostructure channel, the first width is measured relative the first end, and the second width is measured relative to a middle portion of the curved segment in the method of Yeh as it would be a matter of routine optimization to enhance structural integrity and performance of the semiconductor device.
Claims 13 is rejected under 35 U.S.C. 103 as being unpatentable over Yeh et al. (US 2021/0249506 A1; hereafter Yeh) in view of Jang et al. (US 2020/0220018 A1; hereafter Jang), Bauer et al. (US 2011/0117732 A1; hereafter Bauer) and Young et al. (US 2021/0035870 A1; hereafter Young) and further in view of Kim et al. (US 2008/0026549 A1; hereafter Kim).
Regarding claim 13, Yeh, as modified by Bauer, Jang and Young, teaches the limitations of claim 12 as mentioned above. Yeh does not explicitly teach
“wherein a ratio of DCS to SiH4 is in a range of approximately 5:1 to approximately 10:1”.
"[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929).
In a similar field of endeavor Kim teaches
wherein a ratio of DCS to SiH4 is in a range of approximately 5:1 to approximately 10:1 (see e.g., during deposition cycle the amount of SiH.sub.4 and DCS may be varied to control the morphology of the epitaxially deposited semiconductor material, Para [0024]).
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to optimize relative amounts of DCS and SiH.sub.4 as the relative proportion of these silicon precursor gases affects the morphology and quality of the epitaxially grown semiconductor material. Selecting a DCS to SiH.sub.4 ratio within the claimed range of approximately 5:1 to approximately 10:1 would have been an obvious optimization of a known process parameter.
Claims 15-18 and 32-34 are rejected under 35 U.S.C. 103 as being unpatentable over Yeh et al. (US 2021/0249506 A1; hereafter Yeh) in view of Jang et al. (US 2020/0220018 A1; hereafter Jang), Young et al. (US 2021/0035870 A1; hereafter Young), Chen et al. (US 2013/0207166 A1; hereafter Chen) and Xie et al. (US 2020/0365687 A1; hereafter Xie).
Regarding claim 15, Yeh teaches a method for forming a semiconductor device (see e.g., nanosheet-based structure 100, Figures 1-13), comprising:
forming a fin structure comprising a first portion above a substrate and a second portion over the first portion (see e.g., fin structure comprising a sub-fin 102A above a substrate 102 and a nanosheet stack 130 over the sub-fin 102A, Para [0038], Figure 1);
forming a source/drain recess in the second portion of the fin structure (see e.g., forming source/drain trenches 602 in the nanosheet stack 130, Para [0046], Figure 6),
wherein the second portion includes a plurality of sacrificial layers and a plurality of nanostructure channels that are arranged in an alternating manner (see e.g., the nanosheet stack 130 includes an alternating series of SiGe sacrificial nanosheet layers 122, 124, 126, 128 and Si nanosheet layers 114, 116, 118, Para [0035], Figure 1);
laterally etching the plurality of sacrificial layers through the source/drain recess to form cavities between the plurality of nanostructure channels (see e.g., laterally etching, to partially remove end regions of the sacrificial nanosheet regions 122, 124, 126, 128 to form inner spacer cavities 1002 through source/drain trenches 602, Para [0051], Figure 10);
forming, between the plurality of nanostructure channels, a gate structure and a plurality of inner spacers in the cavities (see e.g., forming inner spacers 1102 in the cavities 1002 formed in the end regions of the sacrificial nanosheets 122, 124, 126, 128. These sacrificial nanosheet layers 122, 124, 126, 128 are removed and replaced with a HKMG structure 1302. The inner spacers 1102 are between the channel nanosheets 114, 116, 118, and the HKMG structure 1302, Paras [0052], [0055] – [0057], Figures 11,12 and 13),
wherein each of the plurality of inner spacers comprises a first exterior surface and a second exterior surface (see e.g., each of the plurality of inner spacers 1102 has a first exterior surface contacting the HKMG structure 1302 and a second exterior surface contacting the doped source/drain region 1202/1204, Figure 13),
Yeh does not explicitly teach
“wherein each of the first exterior surface and the second exterior surface is curved and recessed with respect to sidewalls of the nanostructure channels”;
In a similar field of endeavor Young teaches
wherein each of the first exterior surface and the second exterior surface is curved and recessed with respect to sidewalls of the nanostructure channels (see e.g., the inner spacer 206A has a curved and recessed surface 420 facing the epitaxial source/drain features 210A and a concave surface 460 protruding towards the gate structure 250A, Paras [0056] – [0057], Figures 20-22);
Therefore, it would have been obvious to one skilled in art at time the time the invention was effectively filed to implement Young’s teachings of wherein each of the first exterior surface and the second exterior surface is curved and recessed with respect to sidewalls of the nanostructure channels in the method of Yeh as the curved profile provides a more favorable interface geometry for epitaxial growth and reduces the likelihood of incomplete fill, voids or seams in the source/drain region.
Yeh does not explicitly teach
“forming a buffer layer at a bottom of the source/drain recess;”.
In a similar field of endeavor Xie teaches
forming a buffer layer at a bottom of the source/drain recess (see e.g., semiconductor buffer layer 702 formed at the bottom of the source/drain recess, Para [0058], Figure 7);
Therefore, it would have been obvious to one skilled in art at time the time the invention was effectively filed to implement Xie’s teachings of forming a buffer layer at a bottom of the source/drain recess in the method of Yeh to improve the source/drain epitaxial growth quality and process control.
Yeh does not explicitly teach
“forming a continuous lightly-doped silicon layer of a source/drain region over … and over the plurality of inner spacers in the source/drain recess; and
forming a highly-doped silicon layer of the source/drain region on the continuous lightly-doped silicon layer”.
In a similar field of endeavor Jang teaches
forming a continuous lightly-doped silicon layer of a source/drain region over … and over the plurality of inner spacers in the source/drain recess; and (see e.g., forming a first epitaxial layer 152 comprising SiAs or SiP extending along the inner spacers 130 and the nanosheet channels. The concentration of impurities included in the first epitaxial layer 152 may be within a range of approximately 2×10.sup.20/cm.sup.3 to 8×10.sup.20/cm.sup.3, Para [0032], Figures 7-8)
forming a highly-doped silicon layer of the source/drain region on the continuous lightly-doped silicon layer (see e.g., second epitaxial layer 154 comprising SiP formed over the first epitaxial layer 152. The first epitaxial layer 152 may include first impurities of a first conductivity type in a first concentration, and the second epitaxial layer 154 may include first or second impurities of the same first conductivity type in a second concentration higher than the first concentration. The second concentration may be within a range of 10 times to 20 times the first concentration. A concentration of impurities included in the second epitaxial layer 154 may be within a range of approximately 3.1×10.sup.21/cm.sup.3to 3.9×10.sup.21/cm.sup.3, Para [0034], Figures 7-8).
Therefore, it would have been obvious to one skilled in art at time the time the invention was effectively filed to implement Jang’s teachings of forming a continuous lightly-doped silicon layer of a source/drain region over the buffer layer and over the plurality of inner spacers in the source/drain recess; and forming a highly-doped silicon layer of the source/drain region on the continuous lightly-doped silicon layer in the method of Yeh so the lightly-doped layer provides a controlled source/drain junction and limit excessive dopant diffusion toward the channel region while the heavily doped second source/drain layer over the first layer reduces source/drain resistance and improve electrical conductivity.
Yeh does not explicitly teach
“forming a continuous lightly-doped silicon layer of a source/drain region over the buffer layer”
In a similar field of endeavor Chen teaches
forming a continuous lightly-doped silicon layer of a source/drain region over the buffer layer (see e.g., a multilayer epitaxial source/drain structure including a bottom epitaxial layer 25 comprising boron-doped silicon germanium, followed by additional epitaxial semiconductor layers 27 through 35 formed successively over the bottom layer 25. Accordingly, the bottom epitaxial layer 25 provides an underlying semiconductor layer upon which subsequently formed source/drain epitaxial layers are grown, Para [0015], Figure 5).
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively field to implement Chen’s teachings of forming a continuous lightly-doped silicon layer of a source/drain region over the buffer layer in the method of Yeh so that different epitaxial layers may be independently selected and doped to provide desired strain, junction and electrical characteristics within the source/drain region.
Regarding claim 16, Yeh, as modified by Jang, Young, Chen and Xie, teaches the limitations of claim 15 as mentioned above. Yeh does not explicitly teach
“wherein the buffer layer includes a (100) grain orientation”.
In a similar field of endeavor Xie teaches
wherein the buffer layer includes a (100) grain orientation (see e.g., the source and drain regions 704 can be formed by epitaxial growth from the <100> surface (i.e., the top surface) of the semiconductor buffer layer 702, epitaxial growth from a <100> surface is much faster and will dominate the overall epitaxial growth process, Para [0059], Figure 7).
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to implement Xie’s teachings of wherein the buffer layer includes a (100) grain orientation in the method of Yeh to improve the source/drain epitaxial growth quality and process control.
Regarding claim 17, Yeh, as modified by Jang, Young, Chen and Xie, teaches the limitations of claim 15 as mentioned above.
Yeh does not explicitly teach
“wherein the buffer layer comprises silicon (Si) or silicon germanium (SiGe);”
In a similar field of endeavor Xie teaches
wherein the buffer layer comprises silicon (Si) or silicon germanium (SiGe) (see e.g., the semiconductor buffer layer 702 can be made of suitable material such as for example, silicon or silicon germanium, Para [0058], Figure 7);
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to implement Xie’s teachings of wherein the buffer layer comprises silicon (Si) or silicon germanium (SiGe) in the method of Yeh to improve the source/drain epitaxial growth quality and process control
Yeh does not explicitly teach
“wherein the continuous lightly-doped silicon layer comprises an arsenic- doped silicon (SiAs) or a boron-doped silicon germanium (SiGe:B); and
wherein the highly-doped silicon layer comprises a phosphor-doped silicon (SiP) or a boron-doped silicon germanium (SiGe:B)”.
In a similar field of endevaor Jang teaches
wherein the continuous lightly-doped silicon layer comprises an arsenic- doped silicon (SiAs) or a boron-doped silicon germanium (SiGe:B); and (see e.g., the first epitaxial layer 152 may be a SiAs epitaxial layer, Para [0034], Figures 7-8)
wherein the highly-doped silicon layer comprises a phosphor-doped silicon (SiP) or a boron-doped silicon germanium (SiGe:B) (see e.g., the second epitaxial layer 154 may be a SiP epitaxial layer, Para [0034], Figures 7-8).
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to implement Jang’s teachings of wherein the continuous lightly-doped silicon layer comprises an arsenic- doped silicon (SiAs) or a boron-doped silicon germanium (SiGe:B); and
wherein the highly-doped silicon layer comprises a phosphor-doped silicon (SiP) or a boron-doped silicon germanium (SiGe:B) in the method of Yeh so the lightly-doped layer provides a controlled source/drain junction and limit excessive dopant diffusion toward the channel region while the heavily doped second source/drain layer over the first layer reduces source/drain resistance and improve electrical conductivity.
Regarding claim 18, Yeh, as modified by Jang, Young, Chen and Xie, teaches the limitations of claim 15 as mentioned above. Yeh does not explicitly teach
“wherein the continuous lightly-doped silicon layer is configured to shield the highly-doped silicon layer”.
In a similar field of endeavor Jang teaches
wherein the continuous lightly-doped silicon layer is configured to shield the highly-doped silicon layer (see e.g., the lightly doped first epitaxial layer 152 separates the highly doped second epitaxial layer 154 from the channels and thereby provides a shielding or buffering region between the two, Figures 7-8).
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to implement wherein the continuous lightly-doped silicon layer is configured to shield the highly-doped silicon layer in the method of Yeh to reduce the influence and diffusion of the higher dopant concentration toward the channel region while still permitting the bulk source/drain region to be highly doped for reduced source/drain resistance.
Regarding claim 32, Yeh, as modified by Jang, Young, Chen and Xie, teaches the limitations of claim 15 as mentioned above. Yeh further teaches
wherein the plurality of inner spacers comprises a first inner spacer and the plurality of nanostructure channels comprises a first nanostructure channel residing on the first inner spacer (see e.g., the plurality of inner spacers 1102 comprises a first inner spacer and the plurality of nanosheet channels comprises a first nanosheet channel 114 residing on the first inner spacer, Figure 13),
Yeh does not explicitly teach
“wherein, in a cross section of the semiconductor device, the continuous lightly-doped silicon layer has a first width and a second width,
wherein the first width is measured from the exterior surface of the first inner spacer to a first portion of an exterior surface of the continuous lightly-doped silicon layer, and
wherein the second width is greater than the first width and is measured from an exterior surface of the first nanostructure channel to a second portion of the exterior surface of the continuous lightly-doped silicon layer”.
In a similar field of endeavor Jang teaches
wherein, in a cross section of the semiconductor device, the continuous lightly-doped silicon layer has a first width and a second width (see e.g., the first epitaxial layer 152b has a third maximum thickness T3 and a fifth maximum thickness T5, Para [0062], Figures 7-8),
wherein the first width is measured from the exterior surface of the first inner spacer to a first portion of an exterior surface of the continuous lightly-doped silicon layer, and (see e.g., the fifth thickness T5 from the exterior surface of the inner spacer to the exterior surface of the first epitaxial layer 152b, Para [0062], Figures 7-8)
wherein the second width is greater than the first width and is measured from an exterior surface of the first nanostructure channel to a second portion of the exterior surface of the continuous lightly-doped silicon layer (see e.g., third thickness T3 from the exterior surface of the channel layer 141 to the exterior surface of the first epitaxial layer 152b. The fifth thickness T5 is less than the third thickness T3, Para [0062], Figures 7-8).
Therefore, it would have been obvious to one skilled in the art at time the invention was effectively filed to implement wherein, in a cross section of the semiconductor device, the continuous lightly-doped silicon layer has a first width and a second width, wherein the first width is measured from the exterior surface of the first inner spacer to a first portion of an exterior surface of the continuous lightly-doped silicon layer, and wherein the second width is greater than the first width and is measured from an exterior surface of the first nanostructure channel to a second portion of the exterior surface of the continuous lightly-doped silicon layer as it would be a matter of routine optimization to enhance structural integrity and performance of the semiconductor device.
Regarding claim 33, Yeh, as modified by Jang, Young, Chen and Xie, teaches the limitations of claim 32 as mentioned above. Yeh does not explicitly teach
“wherein the continuously lightly-doped silicon layer comprises a first portion and a second portion,
wherein, in the cross section of the semiconductor device, the first portion resides continuously across an entirety of a bottom portion of the buffer layer and has a height that is approximately equal to or greater than a height of a second nanostructure channel of the plurality of nanostructure channels, wherein the first inner spacer residing on the second nanostructure channel, and
wherein second portion resides above the first portion and includes the first width and the second width”.
In a similar field of endeavor Jang teaches
wherein the continuously lightly-doped silicon layer comprises a first portion and a second portion (see e.g., a first epitaxial layer 152b may be disposed as a single layer extending along side surfaces of first to third channel layers 141, 142, and 143 of a channel structure 140 and side surfaces of internal spacer layers 130 and forming a lower surface of the source/drain region 150b at a lower end, Para [0060], Figures 7-8),
wherein, in the cross section of the semiconductor device, the first portion resides continuously across an entirety of a bottom portion of the ..layer (see e.g., first portion of the first epitaxial layer 152b formed on a lower surface of the source/drain region 150b at a lower end, figures 7-8) and
has a height that is approximately equal to or greater than a height of a second nanostructure channel of the plurality of nanostructure channels,
Jang teaches the first portion of the epitaxial layer 152b has a thickness T4 being thicker than the thickness of the epitaxial layer 152b extending along side surfaces of the channels and inner spacers. One of ordinary skill in art would have recognized the vertical extent of the bottom epitaxial portion as a process parameter that may be varied by optimizing and controlling epitaxial growth conditions and growth duration.
wherein the first inner spacer residing on the second nanostructure channel, and (see e.g., inner spacer 133 in between channel layers 141 and 142, Figures 7-8)
wherein second portion resides above the first portion and includes the first width and the second width (see e.g., second portion of the first epitaxial layer 152b disposed along side surfaces of channel layers 141, 142 and 143, and internal spacer layers 130 above the first portion and has a first width T5 and a second width T3, Figures 7-8).
Regarding claim 34, Yeh, as modified by Jang, Young, Chen and Xie, teaches the limitations of claim 15 as mentioned above. Yeh does not explicitly teach
“wherein the continuous lightly-doped silicon layer interfaces with the plurality of inner spacers and the plurality of nanostructure channels”.
In a similar field of endeavor Jang teaches
wherein the continuous lightly-doped silicon layer interfaces with the plurality of inner spacers and the plurality of nanostructure channels (see e.g., a first epitaxial layer 152b may be disposed as a single layer extending along side surfaces of first to third channel layers 141, 142, and 143 of a channel structure 140 and side surfaces of internal spacer layers 130, Para [0060], Figures 7-8).
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to implement Jang’s teachings of wherein the continuous lightly-doped silicon layer interfaces with the plurality of inner spacers and the plurality of nanostructure channels in the method of Yeh to predictably provide improved control of the source/drain to channel junction and reduced undesired diffusion of the higher dopant concentration toward the channel.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Yeh et al. (US 2021/0249506 A1; hereafter Yeh) in view of Jang et al. (US 2020/0220018 A1; hereafter Jang), Young et al. (US 2021/0035870 A1; hereafter Young), Chen et al. (US 2013/0207166 A1; hereafter Chen) and Xie et al. (US 2020/0365687 A1; hereafter Xie) and further in view of Cho et al. (US 2020/0381546 A1; hereafter Cho).
Regarding claim 19, Yeh, as modified by Jang, Young, Chen and Xie, teaches the limitations of claim 15 as mentioned above. Yeh further teaches
further comprising:
forming a gate structure that includes a plurality of portions that wrap fully around the plurality of nanostructure channels (see e.g., HKMG structure 1302 having a dielectric layer and a metal gate structure wrapped around the nanosheet channels 114, 116 and 118, Para [0056], Figure 13),
Yeh does not explicitly teach
“wherein a length of at least a subset of the plurality of inner spacers is greater relative to a thickness of at least a subset of the plurality of portions of the gate structure”.
In a similar field of endeavor Cho teaches
wherein a length of at least a subset of the plurality of inner spacers is greater relative to a thickness of at least a subset of the plurality of portions of the gate structure (see e.g., first spacer 144 contacting the sidewalls of the first gate structure 162a. The length of the first spacer 144 is greater than the thickness of the corresponding gate structure 162a portion, Paras [0043], [0048], Figure 1A).
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to implement Cho’s teachings of wherein a length of at least a subset of the plurality of inner spacers is greater relative to a thickness of at least a subset of the plurality of portions of the gate structure in the method of Yeh in order to predictable reduce undesired gate to source/drain capacitive coupling and leakage while maintain electrical isolation between the gate and source/drain regions in the stacked channel transistor structure.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Yeh et al. (US 2021/0249506 A1; hereafter Yeh) in view of Jang et al. (US 2020/0220018 A1; hereafter Jang), Young et al. (US 2021/0035870 A1; hereafter Young), Chen et al. (US 2013/0207166 A1; hereafter Chen) and Xie et al. (US 2020/0365687 A1; hereafter Xie) and further in view of Chen et al. (US 2013/0207166 A1; hereafter Chen).
Regarding claim 20, Yeh, as modified by Jang, Young, Chen and Xie, teaches the limitations of claim 15 as mentioned above. Yeh does not explicitly teach
“further comprising:
forming a capping layer on the highly-doped silicon layer,
wherein the capping layer comprises a phosphor-doped silicon (SiP) or a boron- doped silicon germanium (SiGe:B)”.
In a similar field of endeavor Chen teaches
further comprising:
forming a capping layer on the highly-doped silicon layer,
wherein the capping layer comprises a phosphor-doped silicon (SiP) or a boron- doped silicon germanium (SiGe:B) (see e.g., a cap layer 45, boron doped SiGe layer, is formed over the highly doped SiGe layer 35, Para [0031], Figure 5).
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to implement Chen’s teachings of forming a capping layer on the highly-doped silicon layer, wherein the capping layer comprises a phosphor-doped silicon (SiP) or a boron- doped silicon germanium (SiGe:B) in the method of Yeh in order to reduce contact resistance and sheet resistance at the surface for enhanced contact performance.
Claims 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Yeh et al. (US 2021/0249506 A1; hereafter Yeh) in view of Young et al. (US 2021/0035870 A1; hereafter Young) and Cho et al. (US 2020/0381546 A1; hereafter Cho).
Regarding claim 21, Yeh teaches a method (see e.g., nanosheet-based structure 100, Figures 1-13), comprising:
forming a plurality of nanostructures channels above a portion of a fin structure (see e.g., fin structure comprising a sub-fin 102A above a substrate 102 and a nanosheet stack 130 over the sub-fin 102A, Para [0038], Figure 1);
forming a gate structure that includes a plurality of portions that wrap fully around the plurality of nanostructure channels (see e.g., HKMG gate structure wrapped around the plurality of channel nanosheets 114, 116 and 118, paras [0052], [0055] – [0057], Figures 11, 12 and 13);
forming a plurality of inner spacers between the plurality of portions of the gate structure and a recess adjacent to the plurality of nanostructure channels (see e.g., forming inner spacers 1102 in the cavities 1002 formed in the end regions of the sacrificial nanosheets 122, 124, 126, 128. These sacrificial nanosheet layers 122, 124, 126, 128 are removed and replaced with a HKMG structure 1302. The inner spacers 1102 are between the channel nanosheets 114, 116, 118, and the HKMG structure 1302, Paras [0052], [0055] – [0057], Figures 11,12 and 13),
wherein each of the plurality of inner spacers comprises a first exterior surface and a second exterior surface (see e.g., each of the plurality of inner spacers 1102 has a first exterior surface contacting the HKMG structure 1302 and a second exterior surface contacting the doped source/drain region 1202/1204, Figure 13),
forming a source/drain region in the fin structure (see e.g., doped source/drain region 1202/1204 are formed in the source/drain trenches 602, Para [0053], Figure 13).
Yeh does not explicitly teach
“wherein each of the first exterior surface and the second exterior surface is curved and recessed with respect to sidewalls of the nanostructure channels”,
In a similar field of endeavor Young teaches
wherein each of the first exterior surface and the second exterior surface is curved and recessed with respect to sidewalls of the nanostructure channels (see e.g., the inner spacer 206A has a curved and recessed surface 420 facing the epitaxial source/drain features 210A and a concave surface 460 protruding towards the gate structure 250A, Paras [0056] – [0057], Figures 20-22);
Therefore, it would have been obvious to one skilled in art at time the time the invention was effectively filed to implement Young’s teachings of wherein each of the first exterior surface and the second exterior surface is curved and recessed with respect to sidewalls of the nanostructure channels in the method of Yeh as the curved profile provides a more favorable interface geometry for epitaxial growth and reduces the likelihood of incomplete fill, voids or seams in the source/drain region.
Yeh does not explicitly teach
“wherein a length of at least a subset of the inner spacers is greater relative to a thickness of at least a subset of the plurality of portions of the gate structure, and wherein the length of at least the subset of the inner spacers is lesser relative to a thickness of the plurality of nanostructure channels”;
Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929).
In a similar field of endeavor Cho teaches
wherein a length of at least a subset of the inner spacers is greater relative to a thickness of at least a subset of the plurality of portions of the gate structure (see e.g., first spacer 144 contacting the sidewalls of the first gate structure 162a. The vertical length of the first spacer 144 is greater than the vertical length of the corresponding gate structure 162a portion, Paras [0043], [0048], Figures 1A and 3).
and wherein the length of at least the subset of the inner spacers is lesser relative to a thickness of the plurality of nanostructure channels
Cho does not explicitly state that the vertical length of spacer 144 is less than the vertical thickness of the semiconductor pattern 132a, one of ordinary skill in the art would have recognized the relative vertical dimensions of the channel and spacer as result effective structural parameters affecting channel cross-sectional area and gate to source/drain isolation. Determining the relative channel and spacer dimensions to achieve the desired balance between channel conduction and electrical isolation would have involved routine optimization of known device dimensions.
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to implement Cho’s teachings of wherein a length of at least a subset of the inner spacers is greater relative to a thickness of at least a subset of the plurality of portions of the gate structure and wherein the length of at least the subset of the inner spacers is lesser relative to a thickness of the plurality of nanostructure channels in the method of Yeh in order to predictable reduce undesired gate to source/drain capacitive coupling and leakage while maintain electrical isolation between the gate and source/drain regions in the stacked channel transistor structure.
Regarding claim 22, Yeh, as modified by Young and Cho, teaches the limitations of claim 21 as mentioned above. Yeh does not explicitly teach
“wherein a ratio of the length of at least the subset of the inner spacers to the thickness of at least the subset of the plurality of portions of the gate structure is in a range of approximately 1.05 to approximately 1.5”.
"[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929).
In a similar field of endeavor Cho teaches first spacer 144 contacting the sidewalls of the first gate structure 162a. The vertical length of the first spacer 144 is greater than the vertical length of the corresponding gate structure 162a portion.
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to optimize the ratio of spacer length to gate structure thickness within the known relationship of spacer length greater than gate thickness in order to provide sufficient gate to source/drain isolation while avoiding unnecessary spacer dimensions that could adversely affect available channel or gate space. Selection of a claimed ratio would have amounted to routine optimization of known dimensional parameters to obtain desired balance between electrical isolation and device scaling.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Yeh et al. (US 2021/0249506 A1; hereafter Yeh) in view of Young et al. (US 2021/0035870 A1; hereafter Young) and Cho et al. (US 2020/0381546 A1; hereafter Cho) and further in view of Chan et al. (US 2022/0093734 A1; hereafter Chan).
Regarding claim 23, Yeh, as modified by Young and Cho, teaches the limitations of claim 21 as mentioned above. Yeh does not explicitly teach
“wherein a ratio of the thickness of the plurality of nanostructure channels to the thickness of at least the subset of the plurality of portions of the gate structure is in a range of approximately 1.2 to approximately 1.8”.
"[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929).
In a similar field of endeavor Chan teaches channel layer portions 25 having a thickness of 5-15nm such as 10nm. The sacrificial layer portions 23, replaced by gate stacks 34, have a thickness of 5-15nm such as 7nm (see e.g., Figures 2e and 3a). Therefore, the ratio of channel thickness (10nm) to thickness of gate structure (7nm) is 1.43 within the claimed range.
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to optimize select respective thickness to provide sufficient semiconductor thickness for the channel while also providing sufficient inter channel spacing for formation of the replacement gate structure.
Claims 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over Yeh et al. (US 2021/0249506 A1; hereafter Yeh) in view of Young et al. (US 2021/0035870 A1; hereafter Young) and Cho et al. (US 2020/0381546 A1; hereafter Cho) and further in view of Chen et al. (US 2013/0207166 A1; hereafter Chen).
Regarding claim 24, Yeh, as modified by Young and Cho, teaches the limitations of claim 21 as mentioned above. Yeh further teaches
wherein the plurality of nanostructure channels comprises:
a first nanostructure channel above the portion of the fin structure (see e.g., above the sub-fin 102A the nanosheet stack comprises first channel 114, Para [0050], Figure 13);
a second nanostructure channel above the first nanostructure channel; and (see e.g., a second channel 116 above the first channel 114, Figure 13)
a third nanostructure channel above the second nanostructure channel, (see e.g., third channel 118 above the second channel 116, Figure 13)
Yeh does not explicitly teach
“wherein the source/drain region comprises:
a first layer formed .. over the plurality of inner spacers; and
a second layer formed over the first layer”.
In a similar field of endeavor Cho teaches
wherein the source/drain region comprises:
a first layer formed .. over the plurality of inner spacers; and (see e.g., first semiconductor layer 152a extending along side surfaces of the channel layers 132a and side surfaces of the internal spacer layers 144, Para [0054], Figure 3)
a second layer formed over the first layer (see e.g., a second semiconductor layer 152 formed over the first semiconductor layer 152, Para [0059], Figure 3).
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively field to implement Cho’s teachings of wherein the source/drain region comprises:
a first layer formed .. over the plurality of inner spacers; and a second layer formed over the first layer in the method of Yeh to optimize source/drain boundaries allowing the critical interface adjacent to the channel ends and inner spacers to be independently controlled and optimized for enhanced electrical performance.
Yeh does not explicitly teach
“a first layer formed over a buffer layer”
In a similar field of endeavor Chen teaches
a first layer formed over a buffer layer (see e.g., a multilayer epitaxial source/drain structure including a bottom boron doped SiGe layer 25 followed by additional epitaxial layers 27 through 35 formed successively over the bottom layer 25, Para [0015], Figure 5)
Therefore, it would have been obvious to one skilled in art at time the invention was effectively field to implement Chen’s teachings of a first layer formed over a buffer layer in the method of Yeh as different epitaxial layers may be independently selected and doped to provide desired strain, junction and electrical characteristics within the source/drain region.
Regarding claim 25, Yeh, as modified by Young, Cho and Chen, teaches the limitations of claim 24 as mentioned above. Yeh does not explicitly teach
“wherein a first depth of the first layer relative to a center of the source/drain region, at a height of the third nanostructure channel, is greater relative to a second depth of the first layer relative to the center of the source/drain region at a height of the second nanostructure channel”.
"[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929).
In a similar field of endeavor Cho teaches the first semiconductor layer 150a which is a non-uniform layer with thickness varying along the semiconductor patterns 132a and the first spacers 144.
Cho, however, does not explicitly recite the first epitaxial layer being thicker near the top of the source/drain region than at a lower portion thereof. The relative lateral extent of the first epitaxial layer at the respective channel heights would have been a known controllable process parameter.
Therefore, it would have been obvious to one skilled in art at time the invention was effectively field to optimize and provide greater thickness of the first epitaxial layer near the upper portion of the source/drain region where such a profile was desired to obtain the intended source/drain geometry and epitaxial coverage. Selecting such as non-uniform profile would have involved routine experimentation with known epitaxial process parameters and would have yielded predictable results.
Conclusion
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/FAKEHA SEHAR/ Examiner, Art Unit 2893
/YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893
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