Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
Claims 1, 3-4, 6, 13, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Chiou (PGPub No. 2012/0292783 A1) in view of Bae (PGPub No. 2020/0312934 A1) Hsiao (PGPub No. 2010/0279463 A1), and Clarke (PGPub No. 2019/0214559 A1).
Regarding claim 1, Chiou teaches a method comprising: bonding a first wafer to a second wafer (Fig. 1A, 10, 12, & 14; [0010]); and forming an interconnect structure over the first wafer (Fig. 2A, 11a; [0011]), wherein the interconnect structure is electrically connected to integrated circuit devices in the first wafer (Fig. 1A, 10a; [0010]). Specifically, Chiou teaches a wafer 10 attached to a carrier 12 through an adhesive layer 14 ([0010]); and the front surface 11a of a semiconductor substrate wherein interconnect structures are formed ([0011]), with said structures connected by way of integrated circuits formed on the first surface 10a ([0010]). The term “attached … through an adhesive layer” is interpreted to mean the same as “bonding” due to the synonymity between “attached” and “bonding”, as well as their similar application of combining two wafers. The term “carrier” is interpreted to mean the same as “second wafer” due to the claimed invention’s own use of these as interchangeable terms (e.g., the first and second wafers of claim 1 versus the device and carrier wafers of claim 13). The term “connected” is interpreted to mean the same as “electrically connected” due to assumed electrical nature as a connection between integrated circuits and interconnect structures.
Chiou fails to teach (1) performing a trimming process on the first wafer, wherein an edge portion of the first wafer is removed, and after the trimming process, the first wafer has a first sidewall laterally recessed from a second sidewall of the second wafer; (2) depositing a protection layer contacting a sidewall of the first wafer, wherein the depositing the protection layer comprises depositing a non-oxygen-containing material in contact with the first sidewall, (3) wherein the depositing the protection layer comprises: depositing a first sub layer formed of the non-oxygen-containing material; (4) depositing a second sub layer on the first sub layer, wherein the second sub layer is formed of a material different from the non-oxygen-containing material; and (5) removing a horizontal portion of the protection layer that overlaps the first wafer.
Hsiao teaches performing a trimming process on the first wafer, wherein an edge portion of the first wafer is removed (Figs. 4-5, 117 & 103), and after the trimming process, the first wafer has a first sidewall (Fig. 5, 123; [0034]) laterally recessed from a second sidewall of the second wafer (Fig. 5, 101; [0027] & [0034]). Specifically, Hsiao teaches the removal of the edge portion 117 of the wafer 103, creating a sidewall 123 defined by the remaining portion of the wafer 103 recessed from a sidewall of a carrier 101. Thus, it would have been obvious to a person of ordinary skill in the art (POSITA) prior to the filing date of the claimed invention to trim the structure taught by Chiou according to the process taught by Hsiao in order to properly adjust the element values of the overall device and create a refined structure that allows for further manipulation of the first wafer without changing or manipulating the second wafer.
Chiou in view of Hsiao still fails to teach depositing a protection layer contacting a sidewall of the first wafer, wherein the depositing the protection layer comprises depositing a non-oxygen-containing material in contact with the first sidewall; wherein the depositing the protection layer comprises: depositing a first sub layer formed of the non-oxygen-containing material; depositing a second sub layer on the first sub layer, wherein the second sub layer is formed of a material different from the non-oxygen-containing material; and removing a horizontal portion of the protection layer that overlaps the first wafer.
Clarke teaches depositing a protection layer contacting a sidewall of the first wafer, wherein the depositing the protection layer comprises depositing a non-oxygen-containing material in contact with the first sidewall (Fig. 3J, 315; [0104]); and removing a horizontal portion of the protection layer that overlaps the first wafer (Fig.3K, 316; [0105]). Specifically, Clarke teaches a dielectric spacer layer 315 made of a material such as, but not limited to, silicon nitride, silicon carbide, carbon-doped silicon nitride, or any suitable non-oxygen containing material ([0104]), which later becomes spacer 316 following an anisotropic plasma etch that removes the horizontal portion ([0105]). The term “dielectric spacer layer” is interpreted to mean the same as “protection layer” due to their similar composition as well as their similar application, i.e., as outer layers that insulate the regions below them before their horizontal portion is selectively removed. Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Chiou et al. with those of Clarke, such that the protective layer of Clarke coats the structure of Chiou and is then selectively removed in order to provide specific protection to the now coated regions.
Chiou in further view of Hsiao and Clarke still fails to teach wherein the depositing the protection layer comprises: depositing a first sub layer formed of the non-oxygen-containing material; and depositing a second sub layer on the first sub layer, wherein the second sub layer is formed of a material different from the non-oxygen-containing material.
Bae teaches wherein the depositing the protection layer comprises: depositing a first sub layer formed of the non-oxygen-containing material (Fig. 2, 201; [0075]); and depositing a second sub layer on the first sub layer, wherein the second sub layer is formed of a material different from the non-oxygen-containing material (Id.). Specifically, Bae teaches a display panel comprising a buffer layer 201 (protection layer) which includes a double layer of a silicon nitride layer (first sub layer) and a silicon oxide layer (second sub layer) (Id.). Bae is considered analogous to Chiou et al. due to Bae teaching that said display panel may be implemented utilizing any suitable firmware (e.g., an application-specific integrated circuit) ([0207]); for example, the various components of the display panel may be formed on one integrated circuit (IC) chip or on separate IC chips (Id.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Chiou et al. with those of Bae, such that the protection layer comprises a first material such as silicon nitride to act as a strong barrier against oxygen infiltration, and a second material such as silicon oxide to mitigate any defects in the first material layer and prevent crack formation that would otherwise allow for oxygen infiltration.
Regarding claim 3, Bae teaches wherein the depositing the second sub layer comprises depositing an oxygen-containing material (Fig. 2, 201; [0076]). Specifically, Bae teaches a display panel comprising a buffer layer 201 (protection layer) which includes a double layer of a silicon nitride layer and a silicon oxide layer (second sub layer) (Id.). Bae is considered analogous to Chiou et al. due to Bae teaching that said display panel may be implemented utilizing any suitable firmware (e.g., an application-specific integrated circuit) ([0207]); for example, the various components of the display panel may be formed on one integrated circuit (IC) chip or on separate IC chips (Id.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Chiou et al. with those of Bae, such that the protection layer comprises a second material such as silicon oxide to mitigate any defects in the first material layer and prevent crack formation that would otherwise allow for oxygen infiltration.
Regarding claim 4, Bae teaches wherein the depositing the first sub layer comprises depositing silicon nitride and the depositing the second sub layer comprises depositing silicon oxide (Fig. 2, 201; [0076]). Specifically, Bae teaches a display panel comprising a buffer layer 201 (protection layer) which includes a double layer of a silicon nitride layer and a silicon oxide layer (second sub layer) (Id.). Bae is considered analogous to Chiou et al. due to Bae teaching that said display panel may be implemented utilizing any suitable firmware (e.g., an application-specific integrated circuit) ([0207]); for example, the various components of the display panel may be formed on one integrated circuit (IC) chip or on separate IC chips (Id.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Chiou et al. with those of Bae, such that the protection layer comprises a first material such as silicon nitride to act as a strong barrier against oxygen infiltration, and a second material such as silicon oxide to mitigate any defects in the first material layer and prevent crack formation that would otherwise allow for oxygen infiltration.
Regarding claim 6, Bae teaches wherein an entirety of the protection layer comprises the non-oxygen-containing material (Fig. 2, 201; [0067]). Specifically, Bae teaches a display panel comprising a buffer layer 201 (protection layer) which may include an inorganic insulating material such as silicon nitride (non-oxygen-containing material) and may include a single layer (an entirety of the protection layer) or a multi-layer (Id.). Bae is considered analogous to Chiou et al. due to Bae teaching that said display panel may be implemented utilizing any suitable firmware (e.g., an application-specific integrated circuit) ([0207]); for example, the various components of the display panel may be formed on one integrated circuit (IC) chip or on separate IC chips (Id.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Chiou et al. with those of Bae, such that the protection layer is solely comprised of a single non-oxygen-containing material such as silicon nitride in order to reduce the costs of fabrication while maintaining proper protection against oxygen infiltration.
Regarding claim 13, Chiou teaches a method comprising: bonding a device wafer over a carrier wafer (Fig. 1A, 10, 12, & 14; [0010]); and forming an interconnect structure over the device wafer (Fig. 2A, 11a; [0011]), wherein the interconnect structure is electrically connected to integrated circuit devices in the device wafer (Fig. 1A, 10a; [0010]). Specifically, Chiou teaches a wafer 10 attached to a carrier 12 through an adhesive layer 14 ([0010]); and the front surface 11a of a semiconductor substrate wherein interconnect structures are formed ([0011]), with said structures connected by way of integrated circuits formed on the first surface 10a ([0010]). The term “attached … through an adhesive layer” is interpreted to mean the same as “bonding” due to the synonymity between “attached” and “bonding”, as well as their similar application of combining two wafers. The term “a wafer” is interpreted to mean the same as “device wafer” due to the claimed invention’s own use of these as interchangeable terms (e.g., the first and second wafers of claim 1 versus the device and carrier wafers of claim 13). The term “connected” is interpreted to mean the same as “electrically connected” due to assumed electrical nature as a connection between integrated circuits and interconnect structures.
Chiou fails to teach (1) thinning a semiconductor substrate of the device wafer; (2) trimming the device wafer, wherein an edge portion of the device wafer is trimmed; (3) depositing a protection layer on the device wafer and the carrier wafer, wherein the depositing the protection layer comprises: depositing a first sub layer comprising a first material; and depositing a second sub layer comprising a second material different from the first material; and (4) revealing a top surface of the device wafer.
Hsiao teaches thinning a semiconductor substrate of the device wafer (Fig. 2A, 103; [0029]); and trimming the device wafer, wherein an edge portion of the device wafer is trimmed (Figs. 4-5, 117 & 103). Specifically, Hsiao teaches a method of forming a plurality stacked-die package comprising a thinning process of wafer 103, the removal (trimming) of the edge portion 117 of the wafer 103, creating a sidewall 123 defined by the remaining portion of the wafer 103 recessed from a sidewall of a carrier 101 (Figs. 2A, 4 & 5; [0029]). The term “wafer” is interpreted to mean the same as both “substrate” and “device wafer” as used in the claimed invention due to Hsiao stating that “the term "wafer" herein generally refers to a semiconductor substrate on which various layers and device structures are formed” ([0027]). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to trim the structure taught by Chiou according to the process taught by Hsiao in order to properly adjust the element values of the overall device and create a refined structure that allows for further manipulation of the first wafer without changing or manipulating the second wafer.
Chiou in view of Hsiao fails to teach depositing a protection layer contacting a sidewall of the first wafer, wherein the depositing the protection layer comprises depositing a non-oxygen-containing material in contact with the first sidewall; and removing a horizontal portion of the protection layer that overlaps the first wafer.
Clarke teaches depositing a protection layer on the device wafer and the carrier wafer, wherein the depositing the protection layer comprises: depositing a protection layer on the device wafer and the carrier wafer, wherein the depositing the protection layer comprises: depositing a first sub layer comprising a first material (Fig. 3J, 315; [0104]); and depositing a second sub layer comprising a second material different from the first material (Fig. 3L, 315; [0107]); and revealing a top surface of the device wafer (Fig.3K & 3M; [0105] & [0108]). Specifically, Clarke teaches a dielectric spacer layer 315 made of a material such as, but not limited to, silicon nitride, silicon carbide, carbon-doped silicon nitride, or any suitable non-oxygen containing material ([0104]), which later becomes spacer 316 following an anisotropic plasma etch that removes the horizontal portion ([0105]). Clarke also teaches the formation of a second dielectric material 318 covering any underlying layers (Fig. 3L; [0107]), which later has its top horizontal surface removed (Fig. 3M; [0108]). The term “dielectric spacer layer” is interpreted to mean the same as “protection layer” due to their similar composition as well as their similar application, i.e., as outer layers that insulate the regions below them before their horizontal portion is selectively removed. The term “second dielectric material” is interpreted to be a material that is similar to yet distinct from the dielectric spacer layer based upon the specific wording used, specifically the words “dielectric” and “second”, respectively. Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Clarke with those of Chiou, such that the protective layers of Clarke coat the structure of Chiou and are then selectively removed in order to provide specific protection to the now coated regions.
Regarding claim 15, Bae teaches wherein the second sub layer has better oxygen-blocking ability than the first sub layer (Fig. 2, 201; [0076]). Specifically, Bae teaches a display panel comprising a buffer layer 201 (protection layer) which includes a double layer of a silicon nitride layer and a silicon oxide layer (second sub layer) (Id.). It is interpreted that the oxygen-blocking ability of each sub layer is an inherent characteristic of the material used to form said layers; in other words, if the sub layers comprise the same material(s) as listed in the claimed invention (see [0034 – 0036]), then one of ordinary skill in the art would obviously infer the differences in oxygen-blocking ability as claimed. Bae is considered analogous to Chiou et al. due to Bae teaching that said display panel may be implemented utilizing any suitable firmware (e.g., an application-specific integrated circuit) ([0207]); for example, the various components of the display panel may be formed on one integrated circuit (IC) chip or on separate IC chips (Id.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Chiou et al. with those of Bae, such that the protection layer comprises a first material such as silicon nitride to act as an initial barrier against oxygen infiltration, and a second material such as silicon oxide that can further increase and support the capabilities of the overall protection layer.
Regarding claim 21, Hsiao teaches wherein the thinning the semiconductor substrate results a surface of the semiconductor substrate to be generated (Fig. 2A and [0029] point to a thinning process of wafer 103. It is considered obvious that the act of thinning a semiconductor substrate would result in the generation of a surface.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Chiou et al. and Hsiao, such that semiconductor substrate is thinned in order to adjust the element values of the overall device and create a refined structure that allows for further manipulation of the first wafer without changing or manipulating the second wafer.
Hsiao fails to teach wherein the protection layer forms an interface with the surface of the semiconductor substrate.
Clarke teaches wherein the protection layer forms an interface with the surface of the semiconductor substrate (Figs. 3J and 3K point to a dielectric spacer layer 315 (protection layer) formed over a substrate 301. It is considered obvious that the dielectric spacer layer 315 forms an interface with the top surface of substrate 301 via the first dielectric layer 302.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Chiou et al. and Clarke, such that the protection layer interfaces with the semiconductor substrate in order to extend protection against oxygen infiltration and/or external damage to the substrate.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Chiou et al. in further view of Tsiang (US Patent No. 10515796 B2).
Regarding claim 5, Tsiang teaches between the depositing the first sub layer and the depositing the second sub layer, depositing a third sub layer (Fig. 3, 305), wherein during the depositing the third sub layer, process gases gradually transition from first process gases for depositing the first sub layer to second process gases for depositing the second sub layer (Fig. 3, 300; Col. 8, lines 10-12). Specifically, Tsiang teaches the transition process 300 to the depositing of a bulk silicon nitride layer 305, in order to transition from the first process gas set to the second process gas set (Col. 8, lines 10-12). The term “bulk silicon nitride layer” is interpreted to mean the same as “third sub layer” due to its relation to semiconductor device formation as well as the notable composition of silicon nitride, which cited in multiple locations of the claimed invention as a necessary material for at least one of the sub layers that make up the protection layer, such as in claim 4, which has already been analyzed. Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to deposit an additional sub layer between the two sub layers as taught in Chiou et al., where the additional sub layer allows the transition from first process gases to second process gases as per Tsiang’s teachings, in order to ensure that both of the other sub layers are properly applied without any faults or defects.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Chiou et al. in further view of Lu (PGPub No. 2008/0017956 A1).
Regarding claim 7, Lu teaches after the interconnect structure is formed, removing the second wafer from the first wafer ([0033]). Specifically, Lu teaches a method for forming a semiconductor package, consisting of steps where first interconnect layers are formed in a substrate, then later said substrate (called a wafer) is then mounted to a wafer carrier, and finally, after the formation of trenches and application of solder paste, said wafer carrier is then removed ([0033]). The term “wafer carrier” is interpreted to mean the same as “second wafer” due to the claimed invention’s own use of these as interchangeable terms (e.g., the first and second wafers of claim 1 versus the device and carrier wafers of claim 13). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Lu with those of Chiou et al. in order to minimize the space taken up by the overall structure.
Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Chiou et al. in further view of Chuang (PGPub No. 2020/0212537 A1).
Regarding claim 8, Chuang teaches performing a singulation process (Fig. 23, 220) on the first wafer to separate the first wafer into a plurality of device dies (Fig. 8, 40 & 56; [0023]). Specifically, Chuang teaches the performance of a singulation process 220, in which wafer 40 is sawed apart into a plurality of device dies 56 ([0023]). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Chuang with those of Chiou et al. and create an overall semiconductor structure with a plurality of device dies in order to provide functionality to said structure.
Regarding claim 9, Chuang teaches wherein the plurality of device dies (Fig. 15, 56) are free from remaining portions of the protection layer (Fig. 15, 74). Specifically, Chuang teaches an embodiment Fig. 15, where the plurality of device dies 56 are located above and thus free from the remaining dielectric layer 74, which may be made from silicon nitride, silicon oxide, or the like ([0028]). The term “dielectric layer” is interpreted to mean the same as “protection layer” due to the similarities in application, as both layers are shown protecting underlying regions, composition, as both are shown to comprise of silicon nitride and/or silicon oxide (e.g., claim 4 as previously analyzed above), and in wording, as it has already been established that the term “dielectric spacer layer” used in Clarke was interpreted to mean the same as “protection layer” (see claims 1 and 13 as discussed above). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Chuang with those of Chiou et al. such that a plurality of dies similar to the ones discussed in claim 8 would be formed in a way that is free from an existing protection layer so as to ensure functionality.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Chiou et al. in further view of Lee (US Patent No. 8921185 B2).
Regarding claim 12, Lee teaches wherein the removing the horizontal portion of the protection layer comprises performing a polishing process (Fig. 1I, 130). Specifically, Lee teaches a planarization process, shown here as a chemical mechanical polishing (CMP) process, where the horizontal portion of the protection layer 130 is removed (Col. 6, lines 56-67). The term “chemical mechanical polishing” is interpreted to mean the same as “polishing” due to the broad nature of the word “polishing” as well as the fact the word “polishing” is used in both terms. Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Lee with those of Chiou et al. such that removal of the horizontal portion of the protection layer taught in Chiou et al. comprises the polishing process taught in Lee so as to ensure proper removal of said layer without the removal or damaging of any other regions.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Chiou et al. in further view of Han (US Patent No. 9947769 B1).
Regarding claim 14, Han teaches wherein the first sub layer (Figs. 1-2, 16 & 22) has a lower oxygen atomic percentage than the second sub layer (Fig. 1-2, 18 & 24). Specifically, Han teaches the inner conformal layer 16 and spacer 22 may have a lower atomic percentage of oxygen than the outer conformal layer 18 and spacer 24, respectively (Col. 6, lines 24-26). The term “conformal layer” is interpreted to mean the same as “sub layer” due to the fact that said “sub layer” is in reference to the overall “protective layer” of claim 13. The term “spacer” is interpreted to mean the same as “sub layer” due to the fact that said “sub layer” is in reference to the overall “protective layer” of claim 13, a term which “spacer” has already been shown to mean the same (e.g., claim 1 as analyzed above). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Han with those of Chiou et al. such that the protection layer of Chiou et al. comprises two sub layers where the inner sub layer has a lower oxygen atomic percentage, in order to create an overall structure that is properly protected from oxidation and damage to the underlying regions.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Chiou et al. in further view of Lin (PGPub No. 2013/0134559 A1).
Regarding claim 16, Lin teaches after the protection layer is deposited (Fig. 7A, 62), forming through-vias (Fig. 7A, 24) penetrating through the semiconductor substrate to electrically connect to conductive features (Fig. 8, 64) underlying the semiconductor substrate. Specifically, Lin teaches the formation of insulation layer 62, wherein TSVs (through-substrate vias) 24 extend through said layer ([0018]); insulation layer 62 may include silicon oxide, silicon nitride, or the like (Id.). Conductive features 64 are formed over insulation layer 62 and connected to TSVs 24 ([0019]). The term “insulation layer” is interpreted to mean the same as “protection layer” due to their similar composition as well as their similar application, i.e., as outer layers that insulate the regions below them before being selectively removed. The term “connected” is interpreted to mean the same as “electrically connected” as the relationship between conductive feature and through-via is also defined as “electrically coupled” within the Abstract of Lin. Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to form through-vias in the manner described in the claimed invention using the teachings of Lin, i.e., using them such that the overall structure mostly retains the protection provided by a protective layer while also being able to make use of conductive features.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Chiou et al. in further view of Chen (US Patent No. 9012324 B2).
Regarding claim 17, Chen teaches wherein the forming the interconnect structure (Fig. 12, 250) comprises depositing a dielectric layer (Fig. 12, 230) on the device wafer (Fig. 12, 210), wherein the dielectric layer extends on a sidewall of the protection layer (Fig. 12, r2). Specifically, Chen teaches a flow of a via last process after metal interconnects are formed, where an interdielectric layer 230 and a multilayer interconnect structure 250 are formed on a substrate 210, then a recess r2 is formed in said structure 250, and an insulating layer (not shown) is formed on the sidewalls and bottom of the recess r2 (see Col. 5, lines 64-67, and Col. 6, lines 1-7). The term “insulating layer” is interpreted to mean the same as “protection layer” due to the similarities in application, i.e., coating a part of the overall structure in order to protect said part, and in composition, as Chen teaches that the “insulating layer” may be an oxide layer or a nitride layer (Col. 4, lines 48-49), similar to how the claimed invention’s “protection layer” can be made of silicon nitride and/or silicon oxide. Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Chiou et al. with those in Chen, where the interconnect structure of Chiou et al. is formed with a dielectric layer as taught by Chen, which would improve the efficacy of the overall structure while retaining protection via the protection layer.
Election/Restrictions
This application contains claims directed to the following patentably distinct species:
Species I – A first and second embodiment of a method for protection layer formation in a wafer bonding process as shown in Figs. 1-10 and 12-14 having a protection layer 62, generally corresponding to claims 1-17 and 21
Species II – A third embodiment of a method for protection layer formation in a wafer bonding process as shown in Fig. 11 having a device wafer 30 with all portion of the protection layer removed, generally corresponding to claims 18-20, 22, and 24
Newly submitted claims 18-20, 22, and 24 are directed to an invention that is independent or distinct from the invention originally claimed for the following reasons: the claims to the different species recite the mutually exclusive characteristics of such species. Specifically, claim 18 discloses “removing all portions of the protection layer from the device wafer”, which is not recited in any other species within the claimed invention.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claims 18-20, 22, and 24 are withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Response to Arguments
Applicant's arguments filed 11/20/2025 regarding Examiner’s previous “response to arguments” in the Office Action filed 05/19/2025 are considered unpersuasive. Specifically, Applicant argues against 1) the combination of Chiou and Clarke in terms of “memory device” and “RRAM” respectively, and 2) the combination of Chiou and Bae in regards to “semiconductor devices” and “integrated circuits”. Examiner considers both arguments presented to be incorrect interpretations of “analogous art”. Regarding the first argument, simply stating that “a memory chip” does not support the formation of a RRAM is conclusory: a RRAM, or resistive random access memory, device clearly falls under the definition of a memory chip, and although “a memory chip” may not necessarily point to a RRAM device, it nonetheless defines a broad category of chips/devices that includes RRAMs. Regarding the second argument, Applicant incorrectly states that “semiconductor devices” and “integrated circuits” are too broadly defined to simply be stated as analogous; both semiconductor devices and integrated circuits are commonly known to fall under the art solid state devices, which alone makes the two categories analogous to one another. Thus, Applicant’s arguments are considered unpersuasive, and the previous counter-arguments made by Examiner (along with the related rejection(s) in question) are upheld.
Applicant’s arguments, see Remarks, filed 05/19/2025, with respect to the rejections of claims 18-20, 22, and 24 under 35 U.S.C. §112(a) have been fully considered and are persuasive. The rejections of said claims have been withdrawn.
However, Applicant fails to address the Election requirement in the previous Office Action, and as such the election is treated as a final election without traverse wherein claims 18-20, 22, and 24 are withdrawn from consideration as being directed to a non-elected invention.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Patrick L Cullen whose telephone number is (703)756-1221. The examiner can normally be reached Monday - Friday, 8:30AM - 5PM EST.
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/PATRICK CULLEN/Assistant Examiner, Art Unit 2899
/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899