DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1 and 32 are rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0357769 A1 to Chen et al. (hereinafter “Chen ‘769” – previously cited reference) in view of US 2015/0108644 A1 to Kuang et al. (hereinafter “Kuang” – previously cited reference).
Regarding claim 1, Chen ‘769 discloses a method comprising:
forming a first dielectric layer on a first wafer, wherein the first wafer comprises a first semiconductor substrate (device die wafer 10 having dielectric layer 14 disposed over substrate 12 as shown in Fig. 1A; abstract; paragraphs [0014]-[0015]);
forming a first bond pad comprising a continuous edge that is straight and vertical, wherein the continuous edge penetrates through the first dielectric layer, wherein the first bond pad is in contact with a first surface of the first semiconductor substrate (bond pads 16 having continuous straight vertical edge disposed through dielectric layer 14 and in contact with substrate 12 as shown in Fig. 1A; paragraph [0015]);
forming a second dielectric layer on a second wafer, wherein the second wafer comprises a second semiconductor substrate (dielectric layer 36A formed over substrate 22A of device die 20A as shown in Fig. 2; paragraphs [0021], [0025]);
forming a second bond pad extending into the second dielectric layer (bond pads 34 disposed through dielectric layer 36A as shown in Fig. 2; paragraph [0025]);
sawing the first wafer into a plurality of dies, with the first bond pad being in a first die in the plurality of dies (die-saw step is performed to separate composite wafer into a plurality of packages 78 including wafer having bond pads 16 as shown in Fig. 11; paragraphs [0048], [0058], [0062]); and
bonding the first bond pad to the second bond pad (bond pads 16 are bonded to bond pads 34; Fig. 3; paragraph [0027]).
Chen ‘769 fails to disclose forming a first plurality of dielectric layers over a first semiconductor substrate of a first wafer, wherein the first plurality of dielectric layers comprise a first dielectric layer as a surface layer of the first plurality of dielectric layers; and wherein the continuous edge penetrates through the first plurality of dielectric layers.
However, Kuang discloses forming a first plurality of dielectric layers over a first semiconductor substrate of a first wafer, wherein the first plurality of dielectric layers comprise a first dielectric layer as a surface layer of the first plurality of dielectric layers; and wherein the continuous edge penetrates through the first plurality of dielectric layers (bond pads 130 having straight vertical edge disposed through some of a plurality of vertically stacked dielectric layers 108, 110, 114, 116, 118, 120 which are formed over substrate 102 of wafer; abstract; Figs. 1-5; paragraphs [0010]-[0020]).
Chen ‘769 and Kuang are both considered to be analogous to the claimed invention because they are in the same field of integrated circuit packages. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen ‘769 to incorporate the teaching of Kuang in order to potentially provide reduced risk of dielectric cracking and deformation, superior performance in environmental stresses, and greater flexibility for routing of circuitry under the pad.
Regarding claim 32, Chen ‘769 in view of Kuang discloses the method of claim 1. Chen ‘769 further discloses further comprising: forming a third bond pad in the first dielectric layer, wherein the first bond pad and the third bond pad are over the first semiconductor substrate (third bond pad 16 in layer 14 where first and third bond pads 16 are disposed over substrate 12; Fig. 1A).
Chen ‘769 fails to disclose wherein the third bond pad has a bottom surface higher than lower layers of the first plurality of dielectric layers.
However, Kuang discloses wherein the third bond pad has a bottom surface higher than lower layers of the first plurality of dielectric layers (third bond pad 130 disposed above lower layers 108, 110, 114 of the plurality of vertically stacked dielectric layers 108, 110, 114, 116, 118, 120; Fig. 5).
Chen ‘769 and Kuang are both considered to be analogous to the claimed invention because they are in the same field of integrated circuit packages. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen ‘769 to incorporate the teaching of Kuang in order to potentially provide minimized dielectric cracking and deformation, suppressed sub-layer metal deformation, compatibility with low-cost bonding processes, improved long-term reliability under stress, and freed-up lower dielectric layers for routing, ESD protection, active devices etc.
Claims 1, 10, 21-22, 24 and 31 are rejected under 35 U.S.C. 103 as being unpatentable over Chen ‘769 (noting that claim 1 is being rejected twice).
Regarding claim 1, Chen ‘769 discloses a method comprising:
forming a first dielectric layer on a first wafer, wherein the first wafer comprises a first semiconductor substrate (device die wafer 10 having dielectric layer 14 disposed over substrate 12 as shown in Fig. 1A; abstract; paragraphs [0014]-[0015]);
forming a first bond pad comprising a continuous edge that is straight and vertical, wherein the continuous edge penetrates through the first dielectric layer, wherein the first bond pad is in contact with a first surface of the first semiconductor substrate (bond pads 16 having continuous straight vertical edge disposed through dielectric layer 14 and in contact with substrate 12 as shown in Fig. 1A; paragraph [0015]);
forming a second dielectric layer on a second wafer, wherein the second wafer comprises a second semiconductor substrate (dielectric layer 36A formed over substrate 22A of device die 20A as shown in Fig. 2; paragraphs [0021], [0025]);
forming a second bond pad extending into the second dielectric layer (bond pads 34 disposed through dielectric layer 36A as shown in Fig. 2; paragraph [0025]);
sawing the first wafer into a plurality of dies, with the first bond pad being in a first die in the plurality of dies (die-saw step is performed to separate composite wafer into a plurality of packages 78 including wafer having bond pads 16 as shown in Fig. 11; paragraphs [0048], [0058], [0062]); and
bonding the first bond pad to the second bond pad (bond pads 16 are bonded to bond pads 34; Fig. 3; paragraph [0027]).
Chen ‘769 fails to disclose forming a first plurality of dielectric layers over a first semiconductor substrate of a first wafer, wherein the first plurality of dielectric layers comprise a first dielectric layer as a surface layer of the first plurality of dielectric layers; and wherein the continuous edge penetrates through the first plurality of dielectric layers.
However, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen ‘769 to use a bond pad disposed through a plurality of dielectric layers versus only being disposed through one dielectric layer in order to potentially provide superior mechanical strength and stress distribution, improved crack isolation and prevention of propagation, and enhanced bonding reliability and yield. Further, in a plurality of dielectric layers, the bond pad might similarly extend through all layers as a continuous via or pad which involves applying the same known technique taught by Chen ‘769 to the duplicated layers to yield a predictable result in an art where multilayer dielectric stacks are well-known.
Regarding claim 10, Chen ‘769 discloses the method of claim 1, wherein the first wafer is free from active devices and passive devices therein (device die wafer 10 is free from active and passive devices as shown in Fig. 1A; paragraph [0014]).
Regarding claim 21, Chen ‘769 discloses a method comprising:
forming a first die comprising:
forming a first dielectric layer over a first semiconductor substrate (device die wafer 10 having dielectric layer 14 disposed over substrate 12 as shown in Fig. 1A; abstract; paragraphs [0014]-[0015]); and
forming a first bond pad over and physically joining to the first semiconductor substrate, wherein the first bond pad extends into the first dielectric layer (bond pads 16 disposed through dielectric layer 14 and in contact with substrate 12 as shown in Fig. 1A; paragraph [0015]); and
bonding a second die to the first die (device die 20A bonded to device die wafer 10; abstract; paragraph [0021]), the second die comprising:
a second semiconductor substrate (device die 20A having substrate 22A; paragraph [0022]);
a second dielectric layer under the second semiconductor substrate, wherein the second dielectric layer is bonded to the first dielectric layer (dielectric layer 36A disposed under substrate 22A and bonded to dielectric layer 14 through fusion bonding as part of hybrid bonding process; Fig. 2; paragraphs [0027], [0057], [0062]);
a second bond pad under the second semiconductor substrate (bond pads 34 disposed under substrate 22A and through dielectric layer 36A; Fig. 2; paragraph [0025]), wherein the second bond pad is bonded to the first bond pad (bond pads 16 are bonded to bond pads 34; Fig. 3; paragraph [0027]);
wherein the second bond pad comprises a straight edge extending from a surface of the second semiconductor substrate to a bottom surface of the second dielectric layer (bond pads 34 each having straight side edge extending from surface of substrate 22A to bottom surface of dielectric layer 36A as shown in Fig. 2; paragraph [0025]).
This interpretation of Chen ‘769 fails to disclose a third dielectric layer between the second dielectric layer and the second semiconductor substrate.
However, another interpretation of Chen ‘769 discloses a third dielectric layer between the second dielectric layer and the second semiconductor substrate (dielectric gap-filling material 40 layer disposed between dielectric layer 36A and substrate 22B as shown in Fig. 3; paragraph [0030]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen ‘769 in this manner in order to at least provide improved electrical insulation and signal integrity, enhanced mechanical reliability and stress management, and improved adhesion to the substrate.
Regarding claim 22, Chen ‘769 discloses the method of claim 21, wherein the second bond pad physically contacts a bottom surface of the second semiconductor substrate (bond pads 34 physically contacts bottom of substrate 22A as shown in Fig. 2).
Regarding claim 24, Chen ‘769 discloses the method of claim 21, wherein the second bond pad is formed as fully encircled by dielectric materials (bond pads 34 are encircled by dielectric gap-filling material 40; paragraphs [0030]-[0031]).
Regarding claim 31, Chen ‘769 discloses the method of claim 1, wherein the continuous edge extends to an interface level between the first bond pad and the second bond pad (bond pads 16, 34 together form a continuous edge extending through an interface therebetween as shown in Fig. 3; paragraphs [0015], [0025]).
Claims 8-9 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Chen ‘769 in further view of US 2020/0006309 A1 to Chen et al. (hereinafter “Chen ‘309” – previously cited reference).
Regarding claim 8, Chen ‘769 in view of Chen ‘309 discloses the method of claim 1. Chen ‘769 fails to disclose forming a shallow bond pad in the first dielectric layer, wherein the shallow bond pad is electrically floating.
However, Chen ‘309 discloses forming a shallow bond pad in the first dielectric layer, wherein the shallow bond pad is electrically floating (bond pad 50A disposed at top surface of dielectric layer 52A and encased therein as shown Fig. 2).
Chen ‘769 and Chen ‘309 are both considered to be analogous to the claimed invention because they are in the same field of integrated circuit packages. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen ‘769 to incorporate the teaching of Chen ‘309 in order to optimize electrical performance via reduced capacitance and improved isolation, enhance mechanical reliability, and support scaling and flexibility demands of advanced IC packaging.
Regarding claim 9, Chen ‘769 discloses the method of claim 1, but fails to disclose wherein a second plurality of dielectric layers are formed under the second semiconductor substrate, with the second dielectric layer being a surface layer of the second plurality of dielectric layers, and wherein the second bond pad has a bottom surface contacting a top surface of an additional dielectric layer in the second plurality of dielectric layers.
However, Chen ‘309 discloses wherein a second plurality of dielectric layers are formed under the second semiconductor substrate, with the second dielectric layer being a surface layer of the second plurality of dielectric layers (plurality of dielectric layers 24, 32, 34 formed on the front side of the substrate 20 with layer 34 being surface layer as shown in Fig. 1; paragraphs [0017]-[0018], [0020]), and wherein the second bond pad has a bottom surface contacting a top surface of an additional dielectric layer in the second plurality of dielectric layers (bond pad 36A has bottom surface contacting top surface of dielectric layer 32 of the plurality of dielectric layers 24, 32, 34 as shown in Fig. 2).
Chen ‘769 and Chen ‘309 are both considered to be analogous to the claimed invention because they are in the same field of integrated circuit packages. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen ‘769 to incorporate the teaching of Chen ‘309 in order to increase electrical connectivity, improve signal integrity, and provide greater design flexibility by allowing for complex routing of signals between different layers of the package, especially in high-density applications where space is critical.
Regarding claim 23, Chen ‘769 discloses the method of claim 21, but fails to disclose wherein the second die further comprises an additional dielectric layer over and contacting the second dielectric layer, wherein the second bond pad penetrates through the additional dielectric layer.
However, Chen ‘309 discloses wherein the second die further comprises an additional dielectric layer over and contacting the second dielectric layer (device wafer 2 having top dielectric layer 34 disposed over plurality of dielectric layers 32 as shown in Fig. 2; paragraph [0018]), wherein the second bond pad penetrates through the additional dielectric layer (bond pad 36A disposed through top dielectric layer 34 as shown in Fig. 2; paragraph [0018]).
Chen ‘769 and Chen ‘309 are both considered to be analogous to the claimed invention because they are in the same field of integrated circuit packages. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen ‘769 to incorporate the teaching of Chen ‘309 in order to at least provide optimized electrical performance via reduced capacitance and improved isolation, enhanced mechanical reliability, and support for scaling and flexibility demands of advanced IC packaging.
Claims 5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Chen ‘769 in further view of Chen ‘309 and US 2019/0333871 A1 to Chen et al. (hereinafter “Chen ‘871”).
Regarding claim 5, Chen ‘769 in view of Chen ‘309 discloses the method of claim 1. Chen ‘769 fails to disclose forming integrated circuits on a front side of the first semiconductor substrate; and forming an active bond pad in the first dielectric layer, wherein the active bond pad is electrically connected to the integrated circuits.
However, Chen ‘871 discloses forming integrated circuits on a front side of the first semiconductor substrate (integrated circuit devices 46A formed on first side of substrate 44A as shown in Fig. 2; paragraph [0020]); and forming an active bond pad in the first dielectric layer, wherein the active bond pad is electrically connected to the integrated circuits (bond pad 50A electrically coupled to integrated circuit devices 46A via interconnect structure 53A as shown in Fig. 2; paragraph [0020]).
Chen ‘769, Chen ‘309, and Chen ‘871 are all considered to be analogous to the claimed invention because they are in the same field of integrated circuit packages. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen ‘769 to incorporate the teaching of Chen ‘871 in order to optimize electrical performance via shorter paths and lower parasitics, enhance mechanical and thermal reliability, and support scalability and complexity of modern IC packaging designs.
Regarding claim 7, Chen ‘769 in view of Chen ‘309 and Chen ‘871 discloses the method of claim 5. Chen ‘769 further discloses wherein the first bond pad is formed on a backside of the first die, and wherein the backside is opposite to the front side (bond pads 16 and dielectric layer 14 are formed on first side of substrate 12 opposite a second side; Fig. 1A; paragraphs [0014]-[0015]).
Claims 26-27 are rejected under 35 U.S.C. 103 as being unpatentable over Chen ‘769 in further view of Chen ‘871.
Regarding claim 26, Chen ‘769 discloses the method of claim 21, but fails to disclose wherein the first die is formed as a device die that comprises integrated circuits on the first semiconductor substrate.
However, Chen ‘871 discloses wherein the first die is formed as a device die that comprises integrated circuits on the first semiconductor substrate (device die 42A having integrated circuit devices 46A formed on first side of substrate 44A as shown in Fig. 2; paragraph [0020]).
Chen ‘769 and Chen ‘871 are both considered to be analogous to the claimed invention because they are in the same field of integrated circuit packages. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen ‘769 to incorporate the teaching of Chen ‘871 in order to at least provide performance advantages including speed, efficiency, and signal quality, manufacturing benefits including cost, scalability, and reliability, and design flexibility including miniaturization and customization.
Regarding claim 27, Chen ‘769 discloses the method of claim 21, but fails to disclose forming a through-via penetrating through the first semiconductor substrate, wherein the first bond pad is further in physical contact with the through-via.
However, Chen ‘871 discloses forming a through-via penetrating through the first semiconductor substrate, wherein the first bond pad is further in physical contact with the through-via (via 36 extending from bond pad 40 and through substrate 20 in form of TSV 66 as shown; Fig. 7; paragraphs [0015]-[0016], [0034]).
Chen ‘769 and Chen ‘871 are both considered to be analogous to the claimed invention because they are in the same field of integrated circuit packages. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen ‘769 to incorporate the teaching of Chen ‘871 in order to at least provide advantages in electrical performance via shorter paths and lower parasitics, optimized thermal and power management, mechanical reliability, and integration density.
Claims 28 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Chen ‘309 in further view of Chen ‘871.
Regarding claim 28, Chen ‘309 discloses a method comprising: forming a first die (device wafer 2 of die 4; Fig. 1; paragraph [0015]) comprising: forming a plurality of dielectric layers over and on the front side of the first semiconductor substrate (plurality of dielectric layers 32, 34 formed over and on the front side of the substrate 20 as shown in Fig. 1; paragraphs [0017]-[0018], [0020]); forming a first deep bond pad penetrating through the plurality of dielectric layers (deep bond pads of plurality of bond pads 36A/36 extending through plurality of dielectric layers 32, 34 as shown in Fig. 1; paragraph [0021]); and forming a first active bond pad in a first top surface layer of the plurality of dielectric layers (shallow bond pads of plurality of bond pads 36A/36 formed in a top surface dielectric layer 34 as shown in Fig. 1; paragraph [0021]), wherein the first active bond pad comprises a first top surface coplanar with a second top surface of the first deep bond pad (shallow bond pads of plurality of bond pads 36A/36 having top surfaces coplanar with top surfaces of deep bond pads of plurality of bond pads 36A/36 as shown in Fig. 1).
Chen ‘309 fails to disclose forming integrated circuits over and on a front side of a first semiconductor substrate.
However, Chen ‘871 discloses forming integrated circuits over and on a front side of a first semiconductor substrate (device die 42A having integrated circuit devices 46A formed on first side of substrate 44A as shown in Fig. 2; paragraph [0020]).
Chen ‘309 and Chen ‘871 are both considered to be analogous to the claimed invention because they are in the same field of integrated circuit packages. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen ‘309 to incorporate the teaching of Chen ‘871 in order to at least provide performance advantages including speed, efficiency, and signal quality, manufacturing benefits including cost, scalability, and reliability, and design flexibility including miniaturization and customization.
Regarding claim 30, Chen ‘309 in view of Chen ‘871 discloses the method of claim 28. Chen ‘309 further discloses bonding a second die over the first die (device die 42A bonded over device wafer 2 as shown in Fig. 2), wherein the second die comprises: a second semiconductor substrate (substrate 44A; Fig. 1; [0024]); a shallow bond pad bonded to and physically contacting the first deep bond pad (first bond pad of plurality of bond pads 50A bonded to and contacting deep bond pads of plurality of bond pads 36A/36 as shown in Fig. 2), wherein the shallow bond pad is physically separated from the second semiconductor substrate by at least one dielectric layer (first bond pad of plurality of bond pads 50A is physically separated from substrate 44A by dielectric layer 52A as shown in Fig. 2); and a second active bond pad bonding to the first active bond pad (second bond pad of plurality of bond pads 50A bonded to shallow bond pads of plurality of bond pads 36A/36 as shown in Fig. 2).
Claim 29 is rejected under 35 U.S.C. 103 as being unpatentable over Chen ‘309 in view of Chen ‘871, as applied to claim 28, in further view of Chen ‘769.
Regarding claim 29, Chen ‘309 in view of Chen ‘871 discloses the method of claim 28. Chen ‘309 further discloses bonding a second die to the first die (device die 42A bonded to device wafer 2 as shown in Fig. 2), wherein the second die comprises: a second semiconductor substrate (substrate 44A; Fig. 1; [0024]); and a second active bond pad bonding to the first active bond pad (bond pad 50A bonded to shallow bond pads of plurality of bond pads 36A/36 as shown in Fig. 2).
Chen ‘309 fails to disclose a second deep bond pad contacting the second semiconductor substrate, wherein the second deep bond pad is bonded to and physically contacting the first deep bond pad.
However, Chen ‘769 discloses a second deep bond pad contacting the second semiconductor substrate, wherein the second deep bond pad is bonded to and physically contacting the first deep bond pad (bond pads 34 disposed through dielectric layer 36A and contact bonded to bond pads 16 as shown in Figs. 2-3; paragraphs [0025], [0027]).
Chen ‘309, Chen ‘871 and Chen ‘769 are all considered to be analogous to the claimed invention because they are in the same field of integrated circuit packages. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen ‘309 to incorporate the teaching of Chen ‘769 in order to at least provide advantages in mechanical robustness, thermal management, electrical connectivity, and compatibility with specific contexts such as thick-die power electronics, substrate-grounded designs, or hybrid bonding applications.
Claim 34 is rejected under 35 U.S.C. 103 as being unpatentable over Chen ‘769 in further view of US 2020/0161263 A1 to Chen et al. (hereinafter “Chen ‘263” – newly cited reference).
Regarding claim 34, Chen ‘769 discloses the method of claim 21. Chen ‘769 fails to disclose bonding a dummy die to the first die, wherein the dummy die comprises a conductive path penetrating through the dummy die, and wherein the conductive path comprises the first bond pad at one end.
However, Chen ‘263 discloses bonding a dummy die to the first die, wherein the dummy die comprises a conductive path penetrating through the dummy die, and wherein the conductive path comprises the first bond pad at one end (dummy die 32-1 bonded to die 70, where die 32-1 comprises via containing metal pads 27 which have bond pads 152D at one end; Fig. 29; paragraph [0047]).
Chen ‘769 and Chen ‘263 are both considered to be analogous to the claimed invention because they are in the same field of integrated circuit packages. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen ‘769 to incorporate the teaching of Chen ‘263 in order to potentially provide improved bond strength and reliability, warpage and stress reduction, and enhanced thermal management.
Claim 35 is rejected under 35 U.S.C. 103 as being unpatentable over Chen ‘309 and Chen ‘871 in further view of Chen ‘263.
Regarding claim 35, Chen ‘309 in view of Chen ‘871 discloses the method of claim 28. Chen ‘309 fails to disclose bonding a dummy die to the first die, wherein the dummy die comprises a conductive path penetrating through the dummy die, and wherein the conductive path comprises the first die at one end.
However, Chen ‘263 discloses bonding a dummy die to the first die, wherein the dummy die comprises a conductive path penetrating through the dummy die, and wherein the conductive path comprises the first die at one end (dummy die 32-1 bonded to die 70, where die 32-1 comprises via containing metal pads 27 which have die 70 at one end; Fig. 29; paragraph [0047]).
Chen ‘309 and Chen ‘263 are both considered to be analogous to the claimed invention because they are in the same field of integrated circuit packages. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen ‘309 to incorporate the teaching of Chen ‘263 in order to potentially provide improved bond strength and reliability, warpage and stress reduction, and enhanced thermal management.
Allowable Subject Matter
Claim 33 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed February 24, 2026 have been fully considered. Applicant submitted new claims 33-35 and arguments regarding Examiner’s motivation statements previously argued in prior Applicant responses.
Regarding the motivation statement in the rejection of claim 1 using Chen ‘769 in view of Kuang, Applicant argues that Examiner is merely offering conclusory speculation and is required to provide a reference in support. However, Applicant does not provide any support for why Examiner’s motivation is merely conclusory speculation, which renders the assertion conclusory itself. Further, Applicant does not cite any legal rule or precedent that requires Examiner to provide a reference in support of the motivation statements provided. As a reminder, Examiner is only required to provide a clear, reasoned explanation as to why a PHOSITA would have been motivated to combine or modify the prior art reference(s). Specifically, MPEP 2143 and 2144 emphasize that the rationale for obviousness does not have to be expressly stated in the prior art. Examiner maintains that the motivation was not derived from personal speculation, but rather from what a skilled artisan would intuit from the art.
Regarding the rejection of claim 1 using Chen ‘769, Applicant states that Examiner failed to provide a reference that discloses the claim element lacked in Chen ‘769, despite the fact that Applicant’s previous assertion was directly related to the rejection using Kuang which is a reference that discloses the claim element lacked in Chen ‘769. Therefore, it is unclear what Applicant is asserting in this regard. Applicant further recites Examiner’s previous rebuttal to the reiterated arguments presented by Applicant and does not provide their own rebuttal of these arguments, but merely asserts a conclusory statement that Examiner has not provided a correct and well-founded motivation, which is non-responsive to Examiner’s rebuttal.
Regarding the rejection of claim 21, Applicant claims a conflict is created with regard to “the second dielectric layer” between the two interpretations of Chen ‘769. However, the two interpretations of Chen ‘769 are independent of one another. Applicant asserts that the relationship “the second dielectric layer and the second substrate are comprised in a same second device die” cannot be ignored. However, this quoted text does not appear in claim 21, but Examiner does agree that the limitations related to the second die comprising the second dielectric layer and second substrate cannot be ignored, which is why they were listed as being disclosed by the first interpretation of Chen ‘769.
Regarding the rejection of claim 27, Applicant again disagrees with Examiner’s motivation statement and, similar to claim 1 above, asserts that Examiner must provide “reference support” and so Examiner directs Applicant to the above rebuttal in the second paragraph of the instant remarks.
Regarding the rejection of claims 28 and 30, Applicant reiterates arguments that have been previously-rebutted by Examiner as cited by Applicant. Applicant does not provide their own rebuttal of Examiner’s arguments in this regard and so Applicant’s reiterated arguments are non-responsive to Examiner’s previously-stated rebuttal arguments.
Finally, as stated above, newly added claim 33 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IAN DEGRASSE whose telephone number is (571) 272-0261. The examiner can normally be reached Monday through Friday 8:30a until 5:00p.
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/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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